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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-cpu-opp.dtsi10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
53 opp-supported-hw = <0x1F 0x0C01>;
60 opp-supported-hw = <0x1F 0x0200>;
67 opp-supported-hw = <0x1F 0x0C00>;
[all …]
H A Dtegra124-peripherals-opp.dtsi10 opp-supported-hw = <0x0003>;
16 opp-supported-hw = <0x0008>;
22 opp-supported-hw = <0x0010>;
28 opp-supported-hw = <0x0004>;
34 opp-supported-hw = <0x0003>;
40 opp-supported-hw = <0x0008>;
46 opp-supported-hw = <0x0010>;
52 opp-supported-hw = <0x0004>;
58 opp-supported-hw = <0x0003>;
64 opp-supported-hw = <0x0008>;
[all …]
/freebsd/crypto/openssl/crypto/conf/
H A Dconf_def.h43 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
44 0x0000, 0x0010, 0x0010, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000,
45 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
46 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
47 0x0010, 0x0200, 0x0040, 0x0080, 0x1000, 0x0200, 0x0200, 0x0040,
48 0x0000, 0x0000, 0x0200, 0x0200, 0x0200, 0x0200, 0x0200, 0x0200,
49 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001,
50 0x0001, 0x0001, 0x0000, 0x0200, 0x0000, 0x0000, 0x0000, 0x0200,
51 0x0200, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002,
52 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra132-peripherals-opp.dtsi11 opp-supported-hw = <0x0003>;
17 opp-supported-hw = <0x0008>;
23 opp-supported-hw = <0x0010>;
29 opp-supported-hw = <0x0004>;
35 opp-supported-hw = <0x0003>;
41 opp-supported-hw = <0x0008>;
47 opp-supported-hw = <0x0010>;
53 opp-supported-hw = <0x0004>;
59 opp-supported-hw = <0x0003>;
65 opp-supported-hw = <0x0008>;
[all …]
/freebsd/sys/dev/sk/
H A Dxmaciireg.h43 #define XM_DEVICEID 0x00E0AE20
44 #define XM_XAQTI_OUI 0x00E0AE
46 #define XM_XMAC_REV(x) (((x) & 0x000000E0) >> 5)
48 #define XM_XMAC_REV_B2 0x0
49 #define XM_XMAC_REV_C1 0x1
51 #define XM_MMUCMD 0x0000
52 #define XM_POFF 0x0008
53 #define XM_BURST 0x000C
54 #define XM_VLAN_TAGLEV1 0x0010
55 #define XM_VLAN_TAGLEV2 0x0014
[all …]
H A Dyukonreg.h19 #define YUKON_GPSR 0x0000
21 #define YU_GPSR_SPEED 0x8000 /* speed 0 - 10Mbps, 1 - 100Mbps */
22 #define YU_GPSR_DUPLEX 0x4000 /* 0 - half duplex, 1 - full duplex */
23 #define YU_GPSR_FCTL_TX 0x2000 /* Tx flow control, 1 - disabled */
24 #define YU_GPSR_LINK 0x1000 /* link status (down/up) */
25 #define YU_GPSR_PAUSE 0x0800 /* flow control enable/disable */
26 #define YU_GPSR_TX_IN_PROG 0x0400 /* transmit in progress */
27 #define YU_GPSR_EXCESS_COL 0x0200 /* excessive collisions occurred */
28 #define YU_GPSR_LATE_COL 0x0100 /* late collision occurred */
29 #define YU_GPSR_MII_PHY_STC 0x0020 /* MII PHY status change */
[all …]
/freebsd/sys/dev/vte/
H A Dif_vtereg.h36 #define VENDORID_RDC 0x17F3
41 #define DEVICEID_RDC_R6040 0x6040 /* PMX-1000 */
43 /* MAC control register 0 */
44 #define VTE_MCR0 0x00
45 #define MCR0_ACCPT_ERR 0x0001
46 #define MCR0_RX_ENB 0x0002
47 #define MCR0_ACCPT_RUNT 0x0004
48 #define MCR0_ACCPT_LONG_PKT 0x0008
49 #define MCR0_ACCPT_DRIBBLE 0x0010
50 #define MCR0_PROMISC 0x0020
[all …]
/freebsd/sys/dev/mii/
H A Dbrgphyreg.h42 #define BRGPHY_MII_BMCR 0x00
43 #define BRGPHY_BMCR_RESET 0x8000
44 #define BRGPHY_BMCR_LOOP 0x4000
45 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
46 #define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
47 #define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
48 #define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
49 #define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
50 #define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
51 #define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
[all …]
H A Dbmtphyreg.h41 #define MII_BMTPHY_AUX_CTL 0x10 /* auxiliary control */
42 #define AUX_CTL_TXDIS 0x2000 /* transmitter disable */
43 #define AUX_CTL_4B5B_BYPASS 0x0400 /* bypass 4b5b encoder */
44 #define AUX_CTL_SCR_BYPASS 0x0200 /* bypass scrambler */
45 #define AUX_CTL_NRZI_BYPASS 0x0100 /* bypass NRZI encoder */
46 #define AUX_CTL_RXALIGN_BYPASS 0x0080 /* bypass rx symbol alignment */
47 #define AUX_CTL_BASEWANDER_DIS 0x0040 /* disable baseline wander correction */
48 #define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */
50 #define MII_BMTPHY_AUX_STS 0x11 /* auxiliary status */
51 #define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */
[all …]
H A Dnsgphyreg.h43 #define NSGPHY_MII_STRAPOPT 0x10 /* Strap options */
44 #define NSGPHY_STRAPOPT_PHYADDR 0xF800 /* PHY address */
45 #define NSGPHY_STRAPOPT_COMPAT 0x0400 /* Broadcom compat mode */
46 #define NSGPHY_STRAPOPT_MMSE 0x0200 /* Manual master/slave enable */
47 #define NSGPHY_STRAPOPT_ANEG 0x0100 /* Autoneg enable */
48 #define NSGPHY_STRAPOPT_MMSV 0x0080 /* Manual master/slave setting */
49 #define NSGPHY_STRAPOPT_1000HDX 0x0010 /* Advertise 1000 half-duplex */
50 #define NSGPHY_STRAPOPT_1000FDX 0x0008 /* Advertise 1000 full-duplex */
51 #define NSGPHY_STRAPOPT_100_ADV 0x0004 /* Advertise 100 full/half-duplex */
52 #define NSGPHY_STRAPOPT_SPEED1 0x0002 /* speed selection */
[all …]
H A Dnsphyterreg.h44 #define MII_NSPHYTER_PHYSTS 0x10 /* PHY status */
45 #define PHYSTS_REL 0x8000 /* receive error latch */
46 #define PHYSTS_CIML 0x4000 /* CIM latch */
47 #define PHYSTS_FCSL 0x2000 /* false carrier sense latch */
48 #define PHYSTS_DEVRDY 0x0800 /* device ready */
49 #define PHYSTS_PGRX 0x0400 /* page received */
50 #define PHYSTS_ANEGEN 0x0200 /* autoneg. enabled */
51 #define PHYSTS_MIIINTR 0x0100 /* MII interrupt */
52 #define PHYSTS_REMFAULT 0x0080 /* remote fault */
53 #define PHYSTS_JABBER 0x0040 /* jabber detect */
[all …]
H A Dciphyreg.h44 #define CIPHY_MII_BMCR 0x00
45 #define CIPHY_BMCR_RESET 0x8000
46 #define CIPHY_BMCR_LOOP 0x4000
47 #define CIPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
48 #define CIPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
49 #define CIPHY_BMCR_PDOWN 0x0800 /* Power down */
50 #define CIPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
51 #define CIPHY_BMCR_FDX 0x0100 /* Duplex mode */
52 #define CIPHY_BMCR_CTEST 0x0080 /* Collision test enable */
53 #define CIPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
[all …]
/freebsd/sys/dev/usb/net/
H A Dif_urereg.h30 #define URE_CONFIG_IDX 0 /* config number 1 */
31 #define URE_IFACE_IDX 0
33 #define URE_CTL_READ 0x01
34 #define URE_CTL_WRITE 0x02
39 #define URE_BYTE_EN_DWORD 0xff
40 #define URE_BYTE_EN_WORD 0x33
41 #define URE_BYTE_EN_BYTE 0x11
42 #define URE_BYTE_EN_SIX_BYTES 0x3f
49 #define URE_PLA_IDR 0xc000
50 #define URE_PLA_RCR 0xc010
[all …]
H A Dif_axereg.h46 * the data length (0 to 15) and D represents the direction (0 for vendor read,
50 #define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8)
51 #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12)
52 #define AXE_CMD_CMD(x) ((x) & 0x00FF)
54 #define AXE_172_CMD_READ_RXTX_SRAM 0x2002
55 #define AXE_182_CMD_READ_RXTX_SRAM 0x8002
56 #define AXE_172_CMD_WRITE_RX_SRAM 0x0103
57 #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103
58 #define AXE_172_CMD_WRITE_TX_SRAM 0x0104
59 #define AXE_CMD_MII_OPMODE_SW 0x0106
[all …]
/freebsd/sys/dev/ntb/ntb_hw/
H A Dntb_hw_intel.h42 * Params: [in] P = Bit position of start of the bit field (lsb is 0).
51 #define NTB_LINK_STATUS_ACTIVE 0x2000
52 #define NTB_LINK_SPEED_MASK 0x000f
53 #define NTB_LINK_WIDTH_MASK 0x03f0
67 #define XEON_SPCICMD_OFFSET 0x0504
68 #define XEON_DEVCTRL_OFFSET 0x0598
69 #define XEON_DEVSTS_OFFSET 0x059a
70 #define XEON_LINK_STATUS_OFFSET 0x01a2
71 #define XEON_SLINK_STATUS_OFFSET 0x05a2
73 #define XEON_PBAR2LMT_OFFSET 0x0000
[all …]
/freebsd/sys/dev/le/
H A Dlancereg.h139 #define LE_CSR0 0x0000 /* Control and status register */
140 #define LE_CSR1 0x0001 /* low address of init block */
141 #define LE_CSR2 0x0002 /* high address of init block */
142 #define LE_CSR3 0x0003 /* Bus master and control */
143 #define LE_CSR4 0x0004 /* Test and features control */
144 #define LE_CSR5 0x0005 /* Extended control and Interrupt 1 */
145 #define LE_CSR6 0x0006 /* Rx/Tx Descriptor table length */
146 #define LE_CSR7 0x0007 /* Extended control and interrupt 2 */
147 #define LE_CSR8 0x0008 /* Logical Address Filter 0 */
148 #define LE_CSR9 0x0009 /* Logical Address Filter 1 */
[all …]
/freebsd/sys/dev/xl/
H A Dif_xlreg.h35 #define XL_EE_READ 0x0080 /* read, 5 bit address */
36 #define XL_EE_WRITE 0x0040 /* write, 5 bit address */
37 #define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */
38 #define XL_EE_EWEN 0x0030 /* erase, no data needed */
39 #define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */
40 #define XL_EE_BUSY 0x8000
42 #define XL_EE_EADDR0 0x00 /* station address, first word */
43 #define XL_EE_EADDR1 0x01 /* station address, next word, */
44 #define XL_EE_EADDR2 0x02 /* station address, last word */
45 #define XL_EE_PRODID 0x03 /* product ID code */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dspear300.dtsi15 ranges = <0x60000000 0x60000000 0x50000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0x99000000 0x1000>;
25 reg = <0x60000000 0x1000>;
34 reg = <0x94000000 0x1000 /* FSMC Register */
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
37 0x80010000 0x0010>; /* NAND Base CMD */
44 reg = <0x70000000 0x100>;
51 reg = <0x50000000 0x1000>;
[all …]
H A Dspear310.dtsi15 ranges = <0x40000000 0x40000000 0x10000000
16 0xb0000000 0xb0000000 0x10000000
17 0xd0000000 0xd0000000 0x30000000>;
21 reg = <0xb4000000 0x1000>;
29 reg = <0x44000000 0x1000 /* FSMC Register */
30 0x40000000 0x0010 /* NAND Base DATA */
31 0x40020000 0x0010 /* NAND Base ADDR */
32 0x40010000 0x0010>; /* NAND Base CMD */
39 reg = <0xb4000000 0x1000>;
49 ranges = <0xb0000000 0xb0000000 0x10000000
[all …]
H A Dspear320.dtsi15 ranges = <0x40000000 0x40000000 0x80000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0xb3000000 0x1000>;
26 reg = <0x90000000 0x1000>;
36 reg = <0x4c000000 0x1000 /* FSMC Register */
37 0x50000000 0x0010 /* NAND Base DATA */
38 0x50020000 0x0010 /* NAND Base ADDR */
39 0x50010000 0x0010>; /* NAND Base CMD */
46 reg = <0x70000000 0x100>;
54 reg = <0xb3000000 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dfsmc-nand.txt15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
46 reg = <0xd1800000 0x1000 /* FSMC Register */
47 0xd2000000 0x0010 /* NAND Base DATA */
48 0xd2020000 0x0010 /* NAND Base ADDR */
49 0xd2010000 0x0010>; /* NAND Base CMD */
54 timings = /bits/ 8 <0 0 0 2 3 0>;
57 partition@0 {
/freebsd/sys/dev/e1000/
H A De1000_80003es2lan.h38 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
39 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
40 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
41 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
43 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
44 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
45 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
47 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
48 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
49 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
[all …]
/freebsd/contrib/wpa/src/utils/
H A Dradiotap.h24 * @it_version: radiotap version, always 0
44 /* version is always 0 */
45 #define PKTHDR_RADIOTAP_VERSION 0
49 IEEE80211_RADIOTAP_TSFT = 0,
81 IEEE80211_RADIOTAP_F_CFP = 0x01,
82 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
83 IEEE80211_RADIOTAP_F_WEP = 0x04,
84 IEEE80211_RADIOTAP_F_FRAG = 0x08,
85 IEEE80211_RADIOTAP_F_FCS = 0x10,
86 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]
/freebsd/sys/dev/sound/pci/
H A Dallegro_reg.h49 #define PCI_LEGACY_AUDIO_CTRL 0x40
50 #define SOUND_BLASTER_ENABLE 0x00000001
51 #define FM_SYNTHESIS_ENABLE 0x00000002
52 #define GAME_PORT_ENABLE 0x00000004
53 #define MPU401_IO_ENABLE 0x00000008
54 #define MPU401_IRQ_ENABLE 0x00000010
55 #define ALIAS_10BIT_IO 0x00000020
56 #define SB_DMA_MASK 0x000000C0
57 #define SB_DMA_0 0x00000040
58 #define SB_DMA_1 0x00000040
[all …]
/freebsd/sys/ofed/include/rdma/
H A Dib_pma.h50 #define IB_PMA_CLASS_PORT_INFO cpu_to_be16(0x0001)
51 #define IB_PMA_PORT_SAMPLES_CONTROL cpu_to_be16(0x0010)
52 #define IB_PMA_PORT_SAMPLES_RESULT cpu_to_be16(0x0011)
53 #define IB_PMA_PORT_COUNTERS cpu_to_be16(0x0012)
54 #define IB_PMA_PORT_COUNTERS_EXT cpu_to_be16(0x001D)
55 #define IB_PMA_PORT_SAMPLES_RESULT_EXT cpu_to_be16(0x001E)
67 u8 counter_width; /* resv: 7:3, counter width: 2:0 */
110 u8 link_overrun_errors; /* LocalLink: 7:4, BufferOverrun: 3:0 */
121 #define IB_PMA_SEL_SYMBOL_ERROR cpu_to_be16(0x0001)
122 #define IB_PMA_SEL_LINK_ERROR_RECOVERY cpu_to_be16(0x0002)
[all …]

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