Lines Matching +full:0 +full:x0010
46 * the data length (0 to 15) and D represents the direction (0 for vendor read,
50 #define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8)
51 #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12)
52 #define AXE_CMD_CMD(x) ((x) & 0x00FF)
54 #define AXE_172_CMD_READ_RXTX_SRAM 0x2002
55 #define AXE_182_CMD_READ_RXTX_SRAM 0x8002
56 #define AXE_172_CMD_WRITE_RX_SRAM 0x0103
57 #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103
58 #define AXE_172_CMD_WRITE_TX_SRAM 0x0104
59 #define AXE_CMD_MII_OPMODE_SW 0x0106
60 #define AXE_CMD_MII_READ_REG 0x2007
61 #define AXE_CMD_MII_WRITE_REG 0x2108
62 #define AXE_CMD_MII_READ_OPMODE 0x1009
63 #define AXE_CMD_MII_OPMODE_HW 0x010A
64 #define AXE_CMD_SROM_READ 0x200B
65 #define AXE_CMD_SROM_WRITE 0x010C
66 #define AXE_CMD_SROM_WR_ENABLE 0x010D
67 #define AXE_CMD_SROM_WR_DISABLE 0x010E
68 #define AXE_CMD_RXCTL_READ 0x200F
69 #define AXE_CMD_RXCTL_WRITE 0x0110
70 #define AXE_CMD_READ_IPG012 0x3011
71 #define AXE_172_CMD_WRITE_IPG0 0x0112
72 #define AXE_178_CMD_WRITE_IPG012 0x0112
73 #define AXE_172_CMD_WRITE_IPG1 0x0113
74 #define AXE_178_CMD_READ_NODEID 0x6013
75 #define AXE_172_CMD_WRITE_IPG2 0x0114
76 #define AXE_178_CMD_WRITE_NODEID 0x6114
77 #define AXE_CMD_READ_MCAST 0x8015
78 #define AXE_CMD_WRITE_MCAST 0x8116
79 #define AXE_172_CMD_READ_NODEID 0x6017
80 #define AXE_172_CMD_WRITE_NODEID 0x6118
82 #define AXE_CMD_READ_PHYID 0x2019
83 #define AXE_172_CMD_READ_MEDIA 0x101A
84 #define AXE_178_CMD_READ_MEDIA 0x201A
85 #define AXE_CMD_WRITE_MEDIA 0x011B
86 #define AXE_CMD_READ_MONITOR_MODE 0x101C
87 #define AXE_CMD_WRITE_MONITOR_MODE 0x011D
88 #define AXE_CMD_READ_GPIO 0x101E
89 #define AXE_CMD_WRITE_GPIO 0x011F
91 #define AXE_CMD_SW_RESET_REG 0x0120
92 #define AXE_CMD_SW_PHY_STATUS 0x0021
93 #define AXE_CMD_SW_PHY_SELECT 0x0122
96 #define AXE_CMD_READ_VLAN_CTRL 0x4027
97 #define AXE_CMD_WRITE_VLAN_CTRL 0x4028
99 #define AXE_772B_CMD_RXCTL_WRITE_CFG 0x012A
100 #define AXE_772B_CMD_READ_RXCSUM 0x002B
101 #define AXE_772B_CMD_WRITE_RXCSUM 0x012C
102 #define AXE_772B_CMD_READ_TXCSUM 0x002D
103 #define AXE_772B_CMD_WRITE_TXCSUM 0x012E
105 #define AXE_SW_RESET_CLEAR 0x00
106 #define AXE_SW_RESET_RR 0x01
107 #define AXE_SW_RESET_RT 0x02
108 #define AXE_SW_RESET_PRTE 0x04
109 #define AXE_SW_RESET_PRL 0x08
110 #define AXE_SW_RESET_BZ 0x10
111 #define AXE_SW_RESET_IPRL 0x20
112 #define AXE_SW_RESET_IPPD 0x40
115 #define AXE_178_RESET_MAGIC 0x40
117 #define AXE_178_MEDIA_GMII 0x0001
118 #define AXE_MEDIA_FULL_DUPLEX 0x0002
119 #define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004
122 #define AXE_178_MEDIA_MAGIC 0x0004
123 /* AX88772 documentation says to always write 0 to bit 3 */
124 #define AXE_178_MEDIA_ENCK 0x0008
125 #define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010
126 #define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010
127 #define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020
128 #define AXE_178_MEDIA_JUMBO_EN 0x0040
129 #define AXE_178_MEDIA_LTPF_ONLY 0x0080
130 #define AXE_178_MEDIA_RX_EN 0x0100
131 #define AXE_178_MEDIA_100TX 0x0200
132 #define AXE_178_MEDIA_SBP 0x0800
133 #define AXE_178_MEDIA_SUPERMAC 0x1000
135 #define AXE_RXCMD_PROMISC 0x0001
136 #define AXE_RXCMD_ALLMULTI 0x0002
137 #define AXE_172_RXCMD_UNICAST 0x0004
138 #define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004
139 #define AXE_RXCMD_BROADCAST 0x0008
140 #define AXE_RXCMD_MULTICAST 0x0010
141 #define AXE_RXCMD_ACCEPT_RUNT 0x0040 /* AX88772B */
142 #define AXE_RXCMD_ENABLE 0x0080
143 #define AXE_178_RXCMD_MFB_MASK 0x0300
144 #define AXE_178_RXCMD_MFB_2048 0x0000
145 #define AXE_178_RXCMD_MFB_4096 0x0100
146 #define AXE_178_RXCMD_MFB_8192 0x0200
147 #define AXE_178_RXCMD_MFB_16384 0x0300
148 #define AXE_772B_RXCMD_HDR_TYPE_0 0x0000
149 #define AXE_772B_RXCMD_HDR_TYPE_1 0x0100
150 #define AXE_772B_RXCMD_IPHDR_ALIGN 0x0200
151 #define AXE_772B_RXCMD_ADD_CHKSUM 0x0400
152 #define AXE_RXCMD_LOOPBACK 0x1000 /* AX88772A/AX88772B */
155 #define AXE_PHY_SEL_SEC 0
156 #define AXE_PHY_TYPE_MASK 0xE0
161 #define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */
167 #define AXE_PHY_NO_MASK 0x1F
170 #define AXE_772_PHY_NO_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */
172 #define AXE_GPIO0_EN 0x01
173 #define AXE_GPIO0 0x02
174 #define AXE_GPIO1_EN 0x04
175 #define AXE_GPIO1 0x08
176 #define AXE_GPIO2_EN 0x10
177 #define AXE_GPIO2 0x20
178 #define AXE_GPIO_RELOAD_EEPROM 0x80
180 #define AXE_PHY_MODE_MARVELL 0x00
181 #define AXE_PHY_MODE_CICADA 0x01
182 #define AXE_PHY_MODE_AGERE 0x02
183 #define AXE_PHY_MODE_CICADA_V2 0x05
184 #define AXE_PHY_MODE_AGERE_GMII 0x06
185 #define AXE_PHY_MODE_CICADA_V2_ASIX 0x09
186 #define AXE_PHY_MODE_REALTEK_8211CL 0x0C
187 #define AXE_PHY_MODE_REALTEK_8211BN 0x0D
188 #define AXE_PHY_MODE_REALTEK_8251CL 0x0E
189 #define AXE_PHY_MODE_ATTANSIC 0x40
192 #define AXE_SW_PHY_SELECT_EXT 0x0000
193 #define AXE_SW_PHY_SELECT_EMBEDDED 0x0001
194 #define AXE_SW_PHY_SELECT_AUTO 0x0002
195 #define AXE_SW_PHY_SELECT_SS_MII 0x0004
196 #define AXE_SW_PHY_SELECT_SS_RVRS_MII 0x0008
197 #define AXE_SW_PHY_SELECT_SS_RVRS_RMII 0x000C
198 #define AXE_SW_PHY_SELECT_SS_ENB 0x0010
201 #define AXE_VLAN_CTRL_ENB 0x00001000
202 #define AXE_VLAN_CTRL_STRIP 0x00002000
203 #define AXE_VLAN_CTRL_VID1_MASK 0x00000FFF
204 #define AXE_VLAN_CTRL_VID2_MASK 0x0FFF0000
206 #define AXE_RXCSUM_IP 0x0001
207 #define AXE_RXCSUM_IPVE 0x0002
208 #define AXE_RXCSUM_IPV6E 0x0004
209 #define AXE_RXCSUM_TCP 0x0008
210 #define AXE_RXCSUM_UDP 0x0010
211 #define AXE_RXCSUM_ICMP 0x0020
212 #define AXE_RXCSUM_IGMP 0x0040
213 #define AXE_RXCSUM_ICMP6 0x0080
214 #define AXE_RXCSUM_TCPV6 0x0100
215 #define AXE_RXCSUM_UDPV6 0x0200
216 #define AXE_RXCSUM_ICMPV6 0x0400
217 #define AXE_RXCSUM_IGMPV6 0x0800
218 #define AXE_RXCSUM_ICMP6V6 0x1000
219 #define AXE_RXCSUM_FOPC 0x8000
221 #define AXE_RXCSUM_64TE 0x0100
222 #define AXE_RXCSUM_PPPOE 0x0200
223 #define AXE_RXCSUM_RPCE 0x8000
225 #define AXE_TXCSUM_IP 0x0001
226 #define AXE_TXCSUM_TCP 0x0002
227 #define AXE_TXCSUM_UDP 0x0004
228 #define AXE_TXCSUM_ICMP 0x0008
229 #define AXE_TXCSUM_IGMP 0x0010
230 #define AXE_TXCSUM_ICMP6 0x0020
231 #define AXE_TXCSUM_TCPV6 0x0100
232 #define AXE_TXCSUM_UDPV6 0x0200
233 #define AXE_TXCSUM_ICMPV6 0x0400
234 #define AXE_TXCSUM_IGMPV6 0x0800
235 #define AXE_TXCSUM_ICMP6V6 0x1000
237 #define AXE_TXCSUM_64TE 0x0001
238 #define AXE_TXCSUM_PPPOE 0x0002
242 #define AXE_CTL_READ 0x01
243 #define AXE_CTL_WRITE 0x02
245 #define AXE_CONFIG_IDX 0 /* config number 1 */
246 #define AXE_IFACE_IDX 0
249 #define AXE_EEPROM_772B_NODE_ID 0x04
250 #define AXE_EEPROM_772B_PHY_PWRCFG 0x18
257 #define AX88772B_MFB_2K 0
268 #define AXE_HDR_LEN_MASK 0xFFFF
272 #define AXE_TX_CSUM_PSEUDO_HDR 0x4000
273 #define AXE_TX_CSUM_DIS 0x8000
289 #define AXE_CSUM_HDR_LEN_MASK 0x07FF
290 #define AXE_CSUM_HDR_CRC_ERR 0x1000
291 #define AXE_CSUM_HDR_MII_ERR 0x2000
292 #define AXE_CSUM_HDR_RUNT 0x4000
293 #define AXE_CSUM_HDR_BMCAST 0x8000
296 #define AXE_CSUM_HDR_VLAN_MASK 0x0007
297 #define AXE_CSUM_HDR_VLAN_STRIP 0x0008
298 #define AXE_CSUM_HDR_VLAN_PRI_MASK 0x0070
299 #define AXE_CSUM_HDR_L4_CSUM_ERR 0x0100
300 #define AXE_CSUM_HDR_L3_CSUM_ERR 0x0200
301 #define AXE_CSUM_HDR_L4_TYPE_UDP 0x0400
302 #define AXE_CSUM_HDR_L4_TYPE_ICMP 0x0800
303 #define AXE_CSUM_HDR_L4_TYPE_IGMP 0x0C00
304 #define AXE_CSUM_HDR_L4_TYPE_TCP 0x1000
305 #define AXE_CSUM_HDR_L4_TYPE_TCPV6 0x1400
306 #define AXE_CSUM_HDR_L4_TYPE_MASK 0x1C00
307 #define AXE_CSUM_HDR_L3_TYPE_IPV4 0x2000
308 #define AXE_CSUM_HDR_L3_TYPE_IPV6 0x4000
340 #define AXE_FLAG_LINK 0x0001
341 #define AXE_FLAG_STD_FRAME 0x0010
342 #define AXE_FLAG_CSUM_FRAME 0x0020
343 #define AXE_FLAG_772 0x1000 /* AX88772 */
344 #define AXE_FLAG_772A 0x2000 /* AX88772A */
345 #define AXE_FLAG_772B 0x4000 /* AX88772B */
346 #define AXE_FLAG_178 0x8000 /* AX88178 */