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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124-nyan-blaze-emc.dtsi92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x00000008
[all …]
H A Dtegra124-apalis-emc.dtsi108 0x40040001 0x8000000a
109 0x00000001 0x00000001
110 0x00000002 0x00000000
111 0x00000002 0x00000001
112 0x00000003 0x00000008
113 0x00000003 0x00000002
114 0x00000003 0x00000006
115 0x06030203 0x000a0502
116 0x77e30303 0x70000f03
117 0x001f0000
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi104 0x40040001
105 0x8000000a
106 0x00000001
107 0x00000001
108 0x00000002
109 0x00000000
110 0x00000002
111 0x00000001
112 0x00000003
113 0x00000008
[all …]
H A Dtegra124-nyan-big-emc.dtsi263 0x40040001 /* MC_EMEM_ARB_CFG */
264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
272 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap4460.dtsi12 cpu0: cpu@0 {
32 reg = <0x4a002260 0x4
33 0x4a00232C 0x4
34 0x4a002378 0x18>;
36 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
39 #thermal-sensor-cells = <0>;
45 reg = <0x4a307bd
[all...]
/freebsd/sys/powerpc/include/
H A Dtlb.h36 #define MAS0_TLBSEL(x) ((x << 28) & 0x10000000)
37 #define MAS0_ESEL(x) ((x << 16) & 0x003F0000)
39 #define MAS0_TLBSEL1 0x10000000
40 #define MAS0_TLBSEL0 0x00000000
41 #define MAS0_ESEL_TLB1MASK 0x000F0000
42 #define MAS0_ESEL_TLB0MASK 0x00030000
44 #define MAS0_NV_MASK 0x00000003
45 #define MAS0_NV_SHIFT 0
47 #define MAS1_VALID 0x80000000
48 #define MAS1_IPROT 0x40000000
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am62.dtsi55 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
56 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
57 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
58 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
59 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
60 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
61 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
62 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
63 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
64 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62p.dtsi53 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
57 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
58 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
62 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62a.dtsi54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-j722s.dtsi24 #size-cells = <0>;
46 cpu0: cpu@0 {
48 reg = <0x000>;
51 i-cache-size = <0x8000>;
54 d-cache-size = <0x8000>;
58 clocks = <&k3_clks 135 0>;
63 reg = <0x001>;
66 i-cache-size = <0x8000>;
69 d-cache-size = <0x8000>;
73 clocks = <&k3_clks 136 0>;
[all …]
H A Dk3-am64.dtsi54 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
58 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
63 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
[all …]
/freebsd/sys/arm/ti/clk/
H A Dti_clk_clkctrl.c39 #if 0
49 #define GPIO_X_GDBCLK_MASK 0x00040000
50 #define IDLEST_MASK 0x00030000
51 #define MODULEMODE_MASK 0x00000003
53 #define GPIOX_GDBCLK_ENABLE 0x00040000
54 #define GPIOX_GDBCLK_DISABLE 0x00000000
55 #define IDLEST_FUNC 0x00000000
56 #define IDLEST_TRANS 0x00010000
57 #define IDLEST_IDLE 0x00020000
58 #define IDLEST_DISABLE 0x00030000
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Dmac.h9 #define cut_version_to_mask(cut) (0x1 << ((cut) + 1))
14 #define ILLEGAL_KEY_GROUP 0xFAAAAA00
17 #define OCPBASE_RXBUF_FW_88XX 0x18680000
18 #define OCPBASE_TXBUF_88XX 0x18780000
19 #define OCPBASE_ROM_88XX 0x00000000
20 #define OCPBASE_IMEM_88XX 0x00030000
21 #define OCPBASE_DMEM_88XX 0x00200000
22 #define OCPBASE_EMEM_88XX 0x00100000
28 #define RSVD_PG_CPU_INSTRUCTION_NUM 0
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dqoriq-thermal.txt6 Register (IPBRR0) at offset 0x0BF8.
10 0x01900102 T1040
32 reg = <0xf0000 0x1000>;
33 interrupts = <18 2 0 0>;
34 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
35 fsl,tmu-calibration = <0x00000000 0x00000025
36 0x00000001 0x00000028
37 0x00000002 0x0000002d
38 0x00000003 0x00000031
39 0x00000004 0x00000036
[all …]
H A Dqoriq-thermal.yaml20 Register (IPBRR0) at offset 0x0BF8.
24 0x01900102 T1040
82 reg = <0xf0000 0x1000>;
83 interrupts = <18 2 0 0>;
84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
85 fsl,tmu-calibration = <0x00000000 0x00000025>,
86 <0x00000001 0x00000028>,
87 <0x00000002 0x0000002d>,
88 <0x00000003 0x00000031>,
89 <0x00000004 0x00000036>,
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212phy.h23 #define AR_PHY_BASE 0x9800 /* base address of phy regs */
26 #define AR_PHY_TEST 0x9800 /* PHY test control */
27 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */
29 #define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */
30 #define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */
31 #define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */
33 #define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */
36 #define AR_PHY_TURBO 0x9804 /* frame control register */
37 #define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */
38 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm953012hr.dts50 reg = <0x80000000 0x10000000>;
55 partition@0 {
57 reg = <0x00000000 0x00200000>;
62 reg = <0x00200000 0x00400000>;
66 reg = <0x00600000 0x00a00000>;
70 reg = <0x01000000 0x07000000>;
82 partition@0 {
84 reg = <0x00000000 0x000d0000>;
88 reg = <0x000d0000 0x00030000>;
92 reg = <0x00100000 0x00600000>;
[all …]
H A Dbcm953012k.dts48 reg = <0x80000000 0x10000000>;
53 nand@0 {
55 reg = <0>;
64 partition@0 {
66 reg = <0x00000000 0x00200000>;
71 reg = <0x00200000 0x00400000>;
75 reg = <0x00600000 0x00a00000>;
79 reg = <0x01000000 0x07000000>;
92 partition@0 {
94 reg = <0x00000000 0x000d0000>;
[all …]
/freebsd/sys/contrib/ncsw/inc/
H A Dxx_common.h46 #define MODULE_UNKNOWN 0x00000000
47 #define MODULE_FM 0x00010000
48 #define MODULE_FM_MURAM 0x00020000
49 #define MODULE_FM_PCD 0x00030000
50 #define MODULE_FM_RTC 0x00040000
51 #define MODULE_FM_MAC 0x00050000
52 #define MODULE_FM_PORT 0x00060000
53 #define MODULE_MM 0x00070000
54 #define MODULE_FM_SP 0x00080000
55 #define MODULE_FM_MACSEC 0x00090000
[all …]
/freebsd/sys/dev/bhnd/
H A Dbhndreg.h32 #define BHND_DEFAULT_CHIPC_ADDR 0x18000000
38 #define BHND_DEFAULT_CORE_SIZE 0x1000
43 #define BHND_DEFAULT_ENUM_SIZE 0x00100000
56 #define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */
57 #define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */
58 #define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */
59 #define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */
60 #define BHND_CCS_FORCE_MASK 0x0000000F
62 #define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */
63 #define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */
[all …]
/freebsd/sys/powerpc/ps3/
H A Dif_glcreg.h110 #define GELIC_GET_MAC_ADDRESS 0x0001
111 #define GELIC_GET_LINK_STATUS 0x0002
112 #define GELIC_SET_LINK_MODE 0x0003
113 #define GELIC_LINK_UP 0x0001
114 #define GELIC_FULL_DUPLEX 0x0002
115 #define GELIC_AUTO_NEG 0x0004
116 #define GELIC_SPEED_10 0x0010
117 #define GELIC_SPEED_100 0x0020
118 #define GELIC_SPEED_1000 0x0040
119 #define GELIC_GET_VLAN_ID 0x0004
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx_gptreg.h33 #define IMX_GPT_CR 0x0000 /* Control Register R/W */
38 #define GPT_CR_OM3_MASK 0x1c000000
40 #define GPT_CR_OM2_MASK 0x03800000
42 #define GPT_CR_OM1_MASK 0x00700000
43 #define GPT_CR_OMX_NONE 0
49 #define GPT_CR_IM2_MASK 0x000c0000
51 #define GPT_CR_IM1_MASK 0x00030000
52 #define GPT_CR_IMX_NONE 0
59 #define GPT_CR_CLKSRC_NONE (0 << 6)
70 #define GPT_CR_EN (1 << 0)
[all …]
/freebsd/sys/dev/usb/controller/
H A Dohcireg.h37 #define PCI_CBMEM 0x10 /* configuration base memory */
38 #define PCI_INTERFACE_OHCI 0x10
41 #define OHCI_REVISION 0x00 /* OHCI revision */
42 #define OHCI_REV_LO(rev) ((rev) & 0xf)
43 #define OHCI_REV_HI(rev) (((rev)>>4) & 0xf)
44 #define OHCI_REV_LEGACY(rev) ((rev) & 0x100)
45 #define OHCI_CONTROL 0x04
46 #define OHCI_CBSR_MASK 0x00000003 /* Control/Bulk Service Ratio */
47 #define OHCI_RATIO_1_1 0x00000000
48 #define OHCI_RATIO_1_2 0x00000001
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Diss4xx-mpic.dts17 /memreserve/ 0x01f00000 0x00100000;
24 dcr-parent = <&{/cpus/cpu@0}>;
32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
62 cpu-release-addr = <0 0x01f00100>;
78 cpu-release-addr = <0 0x01f00200>;
94 cpu-release-addr = <0 0x01f00300>;
100 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
107 dcr-reg = <0xffc00000 0x00030000>;
[all …]
/freebsd/sys/fs/nfs/
H A Drpcv2.h47 #define RPCAUTH_NULL 0
70 #define RPCAUTHGSS_DATA 0
79 #define RPCAUTHGSS_MAXSEQ 0x80000000
90 #define GSS_KERBV_QOP 0
107 #define RPCPROG_GSSD 0x20101010
122 #define RPCPROG_NFSUSERD 0x21010101
133 #define GSS_S_COMPLETE 0x00000000
134 #define GSS_S_CONTINUE_NEEDED 0x00000001
135 #define GSS_S_DUPLICATE_TOKEN 0x00000002
136 #define GSS_S_OLD_TOKEN 0x00000004
[all …]

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