Lines Matching +full:0 +full:x00030000
33 #define IMX_GPT_CR 0x0000 /* Control Register R/W */
38 #define GPT_CR_OM3_MASK 0x1c000000
40 #define GPT_CR_OM2_MASK 0x03800000
42 #define GPT_CR_OM1_MASK 0x00700000
43 #define GPT_CR_OMX_NONE 0
49 #define GPT_CR_IM2_MASK 0x000c0000
51 #define GPT_CR_IM1_MASK 0x00030000
52 #define GPT_CR_IMX_NONE 0
59 #define GPT_CR_CLKSRC_NONE (0 << 6)
70 #define GPT_CR_EN (1 << 0)
72 #define IMX_GPT_PR 0x0004 /* Prescaler Register R/W */
73 #define GPT_PR_VALUE_SHIFT 0
74 #define GPT_PR_VALUE_MASK 0x00000fff
76 #define GPT_PR_VALUE_MASK_24M 0x0000f000
79 #define IMX_GPT_SR 0x0008 /* Status Register R/W */
80 #define IMX_GPT_IR 0x000c /* Interrupt Register R/W */
86 #define GPT_IR_OF1 (1 << 0)
95 #define IMX_GPT_OCR1 0x0010 /* Output Compare Register 1 R/W */
96 #define IMX_GPT_OCR2 0x0014 /* Output Compare Register 2 R/W */
97 #define IMX_GPT_OCR3 0x0018 /* Output Compare Register 3 R/W */
98 #define IMX_GPT_ICR1 0x001c /* Input capture Register 1 RO */
99 #define IMX_GPT_ICR2 0x0020 /* Input capture Register 2 RO */
100 #define IMX_GPT_CNT 0x0024 /* Counter Register RO */