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/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dqoriq-thermal.txt6 Register (IPBRR0) at offset 0x0BF8.
10 0x01900102 T1040
32 reg = <0xf0000 0x1000>;
33 interrupts = <18 2 0 0>;
34 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
35 fsl,tmu-calibration = <0x00000000 0x00000025
36 0x00000001 0x00000028
37 0x00000002 0x0000002d
38 0x00000003 0x00000031
39 0x00000004 0x00000036
[all …]
H A Dqoriq-thermal.yaml20 Register (IPBRR0) at offset 0x0BF8.
24 0x01900102 T1040
82 reg = <0xf0000 0x1000>;
83 interrupts = <18 2 0 0>;
84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
85 fsl,tmu-calibration = <0x00000000 0x00000025>,
86 <0x00000001 0x00000028>,
87 <0x00000002 0x0000002d>,
88 <0x00000003 0x00000031>,
89 <0x00000004 0x00000036>,
[all …]
/freebsd/crypto/krb5/src/lib/crypto/builtin/des/
H A Df_sched.c44 0x00000000, 0x00000010, 0x00001000, 0x00001010,
45 0x00100000, 0x00100010, 0x00101000, 0x00101010
49 0x00000000, 0x00100000, 0x00001000, 0x00101000,
50 0x00000010, 0x00100010, 0x00001010, 0x00101010,
51 0x00000001, 0x00100001, 0x00001001, 0x00101001,
52 0x00000011, 0x00100011, 0x00001011, 0x00101011
56 0x00000000, 0x00000001, 0x00000100, 0x00000101,
57 0x00010000, 0x00010001, 0x00010100, 0x00010101,
58 0x01000000, 0x01000001, 0x01000100, 0x01000101,
59 0x01010000, 0x01010001, 0x01010100, 0x01010101
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dt1023si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dt1040si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1012a.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
38 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
54 arm,psci-suspend-param = <0x0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
92 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
93 <0x0 0x1402000 0 0x2000>, /* GICC */
94 <0x0 0x1404000 0 0x2000>, /* GICH */
[all …]
H A Dfsl-ls1088a.dtsi27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
42 reg = <0x1>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
51 reg = <0x2>;
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 reg = <0x3>;
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls1043a.dtsi37 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0>;
49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
58 reg = <0x1>;
59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
68 reg = <0x2>;
69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
78 reg = <0x3>;
79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls1046a.dtsi38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
44 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
53 reg = <0x1>;
54 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
63 reg = <0x2>;
64 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
73 reg = <0x3>;
74 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls208xa.dtsi33 #size-cells = <0>;
38 reg = <0x00000000 0x80000000 0 0x80000000>;
44 #clock-cells = <0>;
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
67 reg = <0x0 0x6020000 0 0x20000>;
73 reg = <0x0 0x1e60000 0x0 0x4>;
[all …]
H A Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
34 d-cache-size = <0x8000>;
45 reg = <0x1>;
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
51 d-cache-size = <0x8000>;
[all …]
H A Dimx8mq.dtsi47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #size-cells = <0>;
105 A53_0: cpu@0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
H A Dtegra30-pegatron-chagall.dts49 reg = <0x80000000 0x40000000>;
59 alloc-ranges = <0x80000000 0x30000000>;
60 size = <0x10000000>; /* 256MiB */
67 reg = <0xbeb00000 0x10000>; /* 64kB */
68 console-size = <0x8000>; /* 32kB */
69 record-size = <0x400>; /* 1kB */
74 reg = <0xbfe0000
[all...]
/freebsd/usr.sbin/bhyve/
H A Dhda_codec.c41 #define INTEL_VENDORID 0x8086
43 #define HDA_CODEC_SUBSYSTEM_ID ((INTEL_VENDORID << 16) | 0x01)
44 #define HDA_CODEC_ROOT_NID 0x00
45 #define HDA_CODEC_FG_NID 0x01
46 #define HDA_CODEC_AUDIO_OUTPUT_NID 0x02
47 #define HDA_CODEC_PIN_OUTPUT_NID 0x03
48 #define HDA_CODEC_AUDIO_INPUT_NID 0x04
49 #define HDA_CODEC_PIN_INPUT_NID 0x05
51 #define HDA_CODEC_STREAMS_COUNT 0x02
52 #define HDA_CODEC_STREAM_OUTPUT 0x00
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/ls/
H A Dls1021a.dtsi31 #size-cells = <0>;
36 reg = <0xf00>;
37 clocks = <&clockgen 1 0>;
44 reg = <0xf01>;
45 clocks = <&clockgen 1 0>;
50 memory@0 {
52 reg = <0x0 0x0 0x0 0x0>;
57 #clock-cells = <0>;
80 offset = <0xb0>;
81 mask = <0x02>;
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_main.c74 #define AL_ETH_TX_L4_PROTO_IDX_MASK 0x1F
86 #define AL_ETH_TX_META_L3_LEN_MASK 0xff
87 #define AL_ETH_TX_META_L3_OFF_MASK 0xff
91 #define AL_ETH_TX_META_OUTER_L3_LEN_MASK 0x1f
93 #define AL_ETH_TX_META_OUTER_L3_OFF_HIGH_MASK 0x18
95 #define AL_ETH_TX_META_OUTER_L3_OFF_LOW_MASK 0x07
99 #define AL_ETH_TX_MACSEC_SIGN_SHIFT 0 /* Sign TX pkt */
105 #define AL_ETH_TX_MACSEC_SECURED_PYLD_LEN_LSB_SHIFT 10 /* Secure Payload Length (0x3FFF for non-S…
109 #define AL_ETH_RX_L3_PROTO_IDX_MASK 0x1F
112 #define AL_ETH_RX_L4_PROTO_IDX_MASK 0x1F
[all …]
/freebsd/sys/dev/ispfw/
H A Dasm_2700.h38 0x0501f06c, 0x00122000, 0x00100000, 0x00014f80,
39 0x00000009, 0x0000000c, 0x00000000, 0x785ad0d5,
40 0x00000040, 0x0000f206, 0x20434f50, 0x59524947,
41 0x48542032, 0x30323220, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x32377878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020392e, 0x31322e30,
45 0x30202024, 0x00000000, 0x0000002f, 0x00000000,
46 0x00000000, 0x00000000, 0x00000000, 0x00100000,
47 0x00100000, 0x00014f80, 0xffffffff, 0x00122004,
[all …]
H A Dasm_2800.h38 0x0501f078, 0x00124000, 0x00100000, 0x00017380,
39 0x00000009, 0x0000000c, 0x00000001, 0x785ad0d5,
40 0x00000080, 0x0001f626, 0x20434f50, 0x59524947,
41 0x48542032, 0x30323320, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x32387878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020392e, 0x31322e30,
45 0x31202024, 0x00000000, 0x00000092, 0x00000000,
46 0x00000000, 0x00000000, 0x00000000, 0x00100000,
47 0x00100000, 0x00017380, 0xffffffff, 0x00124004,
[all …]
H A Dasm_2400.h33 0x0401f1be, 0x00112000, 0x00100000, 0x0000c79b,
34 0x00000008, 0x00000007, 0x00000000, 0x00009496,
35 0x00000003, 0x00000000, 0x20434f50, 0x59524947,
36 0x48542032, 0x30313720, 0x514c4f47, 0x49432043,
37 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
38 0x32347878, 0x20466972, 0x6d776172, 0x65202020,
39 0x56657273, 0x696f6e20, 0x2020382e, 0x30372e30,
40 0x30202024, 0x00000000, 0x00000000, 0x00000000,
41 0x00000000, 0x00000000, 0x00000000, 0x00000000,
42 0x00000000, 0x00000000, 0x00000000, 0x00000000,
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]