Lines Matching +full:0 +full:x00020004
74 #define AL_ETH_TX_L4_PROTO_IDX_MASK 0x1F
86 #define AL_ETH_TX_META_L3_LEN_MASK 0xff
87 #define AL_ETH_TX_META_L3_OFF_MASK 0xff
91 #define AL_ETH_TX_META_OUTER_L3_LEN_MASK 0x1f
93 #define AL_ETH_TX_META_OUTER_L3_OFF_HIGH_MASK 0x18
95 #define AL_ETH_TX_META_OUTER_L3_OFF_LOW_MASK 0x07
99 #define AL_ETH_TX_MACSEC_SIGN_SHIFT 0 /* Sign TX pkt */
105 #define AL_ETH_TX_MACSEC_SECURED_PYLD_LEN_LSB_SHIFT 10 /* Secure Payload Length (0x3FFF for non-S…
109 #define AL_ETH_RX_L3_PROTO_IDX_MASK 0x1F
112 #define AL_ETH_RX_L4_PROTO_IDX_MASK 0x1F
116 #define AL_ETH_RX_L3_OFFSET_MASK (0x7f << AL_ETH_RX_L3_OFFSET_SHIFT)
118 #define AL_ETH_RX_HASH_MASK (0xffff << AL_ETH_RX_HASH_SHIFT)
124 #define AL_ETH_TX_VLAN_TABLE_UDMA_MASK 0xF
128 #define AL_ETH_TX_GPD_L3_PROTO_MASK 0x1f
129 #define AL_ETH_TX_GPD_L3_PROTO_SHIFT 0
130 #define AL_ETH_TX_GPD_L4_PROTO_MASK 0x1f
132 #define AL_ETH_TX_GPD_TUNNEL_CTRL_MASK 0x7
134 #define AL_ETH_TX_GPD_SRC_VLAN_CNT_MASK 0x3
141 #define AL_ETH_TX_GCP_POLY_SEL_MASK 0x1
142 #define AL_ETH_TX_GCP_POLY_SEL_SHIFT 0
143 #define AL_ETH_TX_GCP_CRC32_BIT_COMP_MASK 0x1
145 #define AL_ETH_TX_GCP_CRC32_BIT_SWAP_MASK 0x1
147 #define AL_ETH_TX_GCP_CRC32_BYTE_SWAP_MASK 0x1
149 #define AL_ETH_TX_GCP_DATA_BIT_SWAP_MASK 0x1
151 #define AL_ETH_TX_GCP_DATA_BYTE_SWAP_MASK 0x1
153 #define AL_ETH_TX_GCP_TRAIL_SIZE_MASK 0xF
155 #define AL_ETH_TX_GCP_HEAD_SIZE_MASK 0xFF
157 #define AL_ETH_TX_GCP_HEAD_CALC_MASK 0x1
159 #define AL_ETH_TX_GCP_MASK_POLARITY_MASK 0x1
162 #define AL_ETH_TX_GCP_OPCODE_1_MASK 0x3F
163 #define AL_ETH_TX_GCP_OPCODE_1_SHIFT 0
164 #define AL_ETH_TX_GCP_OPCODE_2_MASK 0x3F
166 #define AL_ETH_TX_GCP_OPCODE_3_MASK 0x3F
168 #define AL_ETH_TX_GCP_OPSEL_1_MASK 0xF
169 #define AL_ETH_TX_GCP_OPSEL_1_SHIFT 0
170 #define AL_ETH_TX_GCP_OPSEL_2_MASK 0xF
172 #define AL_ETH_TX_GCP_OPSEL_3_MASK 0xF
174 #define AL_ETH_TX_GCP_OPSEL_4_MASK 0xF
178 #define L4_CHECKSUM_DIS_AND_L3_CHECKSUM_DIS 0x00
179 #define L4_CHECKSUM_DIS_AND_L3_CHECKSUM_EN 0x20
180 #define L4_CHECKSUM_EN_AND_L3_CHECKSUM_DIS 0x40
181 #define L4_CHECKSUM_EN_AND_L3_CHECKSUM_EN 0x60
184 #define AL_ETH_RX_GPD_OUTER_L3_PROTO_MASK 0x1f
185 #define AL_ETH_RX_GPD_OUTER_L3_PROTO_SHIFT (3 + 0)
186 #define AL_ETH_RX_GPD_OUTER_L4_PROTO_MASK 0x1f
188 #define AL_ETH_RX_GPD_INNER_L3_PROTO_MASK 0x1f
190 #define AL_ETH_RX_GPD_INNER_L4_PROTO_MASK 0x1f
192 #define AL_ETH_RX_GPD_OUTER_PARSE_CTRL_MASK 0xFF
194 #define AL_ETH_RX_GPD_INNER_PARSE_CTRL_MASK 0xFF
196 #define AL_ETH_RX_GPD_L3_PRIORITY_MASK 0xFF
198 #define AL_ETH_RX_GPD_L4_DST_PORT_LSB_MASK 0xFF
206 #define AL_ETH_RX_GPD_PARSE_RESULT_INNER_L3_PROTO_IDX_OFFSET (0 + 5)
207 #define AL_ETH_RX_GPD_PARSE_RESULT_INNER_L4_PROTO_IDX_OFFSET (0 + 10)
214 #define AL_ETH_RX_GCP_POLY_SEL_MASK 0x1
215 #define AL_ETH_RX_GCP_POLY_SEL_SHIFT 0
216 #define AL_ETH_RX_GCP_CRC32_BIT_COMP_MASK 0x1
218 #define AL_ETH_RX_GCP_CRC32_BIT_SWAP_MASK 0x1
220 #define AL_ETH_RX_GCP_CRC32_BYTE_SWAP_MASK 0x1
222 #define AL_ETH_RX_GCP_DATA_BIT_SWAP_MASK 0x1
224 #define AL_ETH_RX_GCP_DATA_BYTE_SWAP_MASK 0x1
226 #define AL_ETH_RX_GCP_TRAIL_SIZE_MASK 0xF
228 #define AL_ETH_RX_GCP_HEAD_SIZE_MASK 0xFF
230 #define AL_ETH_RX_GCP_HEAD_CALC_MASK 0x1
232 #define AL_ETH_RX_GCP_MASK_POLARITY_MASK 0x1
235 #define AL_ETH_RX_GCP_OPCODE_1_MASK 0x3F
236 #define AL_ETH_RX_GCP_OPCODE_1_SHIFT 0
237 #define AL_ETH_RX_GCP_OPCODE_2_MASK 0x3F
239 #define AL_ETH_RX_GCP_OPCODE_3_MASK 0x3F
241 #define AL_ETH_RX_GCP_OPSEL_1_MASK 0xF
242 #define AL_ETH_RX_GCP_OPSEL_1_SHIFT 0
243 #define AL_ETH_RX_GCP_OPSEL_2_MASK 0xF
245 #define AL_ETH_RX_GCP_OPSEL_3_MASK 0xF
247 #define AL_ETH_RX_GCP_OPSEL_4_MASK 0xF
256 { 0x0, 0x0, 0x0 },
257 { 0x0, 0x0, 0x1 },
258 { 0x0, 0x0, 0x2 },
259 { 0x0, 0x0, 0x3 },
260 { 0x18100, 0xFFFFF, 0x80000004 },
261 { 0x188A8, 0xFFFFF, 0x80000005 },
262 { 0x99100, 0xFFFFF, 0x80000006 },
263 { 0x98100, 0xFFFFF, 0x80000007 },
264 { 0x10800, 0x7FFFF, 0x80000008 },
265 { 0x20000, 0x73FFF, 0x80000009 },
266 { 0x20000, 0x70000, 0x8000000A },
267 { 0x186DD, 0x7FFFF, 0x8000000B },
268 { 0x30600, 0x7FF00, 0x8000000C },
269 { 0x31100, 0x7FF00, 0x8000000D },
270 { 0x32F00, 0x7FF00, 0x8000000E },
271 { 0x32900, 0x7FF00, 0x8000000F },
272 { 0x105DC, 0x7FFFF, 0x80010010 },
273 { 0x188E5, 0x7FFFF, 0x80000011 },
274 { 0x72000, 0x72000, 0x80000012 },
275 { 0x70000, 0x72000, 0x80000013 },
276 { 0x46558, 0x7FFFF, 0x80000001 },
277 { 0x18906, 0x7FFFF, 0x80000015 },
278 { 0x18915, 0x7FFFF, 0x80000016 },
279 { 0x31B00, 0x7FF00, 0x80000017 },
280 { 0x30400, 0x7FF00, 0x80000018 },
281 { 0x0, 0x0, 0x8000001F }
286 {{ 0x2800000, 0x0, 0x0, 0x0, 0x1, 0x400000 }},
287 {{ 0x280004C, 0x746000, 0xA46030, 0xE00000, 0x2, 0x400000 }},
288 {{ 0x2800054, 0x746000, 0xA46030, 0x1600000, 0x2, 0x400000 }},
289 {{ 0x280005C, 0x746000, 0xA46030, 0x1E00000, 0x2, 0x400000 }},
290 {{ 0x2800042, 0xD42000, 0x0, 0x400000, 0x1010412, 0x400000 }},
291 {{ 0x2800042, 0xD42000, 0x0, 0x400000, 0x1010412, 0x400000 }},
292 {{ 0x2800042, 0xE42000, 0x0, 0x400000, 0x2020002, 0x400000 }},
293 {{ 0x2800042, 0xE42000, 0x0, 0x400000, 0x2020002, 0x400000 }},
294 {{ 0x280B046, 0x0, 0x6C1008, 0x0, 0x4, 0x406800 }},
295 {{ 0x2800049, 0xF44060, 0x1744080, 0x14404, 0x6, 0x400011 }},
296 {{ 0x2015049, 0xF44060, 0x1744080, 0x14404, 0x8080007, 0x400011 }},
297 {{ 0x280B046, 0xF60040, 0x6C1004, 0x2800000, 0x6, 0x406811 }},
298 {{ 0x2815042, 0x1F42000, 0x2042010, 0x1414460, 0x10100009, 0x40B800 }},
299 {{ 0x2815042, 0x1F42000, 0x2042010, 0x800000, 0x10100009, 0x40B800 }},
300 {{ 0x280B042, 0x0, 0x0, 0x430400, 0x4040009, 0x0 }},
301 {{ 0x2815580, 0x0, 0x0, 0x0, 0x4040005, 0x0 }},
302 {{ 0x280B000, 0x0, 0x0, 0x0, 0x1, 0x400000 }},
303 {{ 0x2800040, 0x174E000, 0x0, 0x0, 0xE, 0x406800 }},
304 {{ 0x280B000, 0x0, 0x0, 0x600000, 0x1, 0x406800 }},
305 {{ 0x280B000, 0x0, 0x0, 0xE00000, 0x1, 0x406800 }},
306 {{ 0x2800000, 0x0, 0x0, 0x0, 0x1, 0x400000 }},
307 {{ 0x280B046, 0x0, 0x0, 0x2800000, 0x7, 0x400000 }},
308 {{ 0x280B046, 0xF60040, 0x6C1004, 0x2800000, 0x6, 0x406811 }},
309 {{ 0x2815042, 0x1F43028, 0x2000000, 0xC00000, 0x10100009, 0x40B800 }},
310 {{ 0x2815400, 0x0, 0x0, 0x0, 0x4040005, 0x0 }},
311 {{ 0x2800000, 0x0, 0x0, 0x0, 0x1, 0x400000 }}
353 * @return 0 on success. otherwise on failure.
363 if (rc != 0) { in al_udma_state_set_wait()
376 if (count-- == 0) { in al_udma_state_set_wait()
382 return 0; in al_udma_state_set_wait()
397 /*control table 0*/ in al_eth_epe_entry_set()
398 al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_addr, idx); in al_eth_epe_entry_set()
399 al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_6, in al_eth_epe_entry_set()
401 al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_2, in al_eth_epe_entry_set()
403 al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_3, in al_eth_epe_entry_set()
405 al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_4, in al_eth_epe_entry_set()
407 al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_5, in al_eth_epe_entry_set()
409 al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_1, in al_eth_epe_entry_set()
410 control_entry->data[0]); in al_eth_epe_entry_set()
425 control_entry->data[0]); in al_eth_epe_entry_set()
432 if (adapter->enable_rx_parser == 0) { in al_eth_epe_init()
435 al_reg_write32(&adapter->ec_regs_base->epe[0].res_def, 0x08000000); in al_eth_epe_init()
436 al_reg_write32(&adapter->ec_regs_base->epe[0].res_in, 0x7); in al_eth_epe_init()
438 al_reg_write32(&adapter->ec_regs_base->epe[1].res_def, 0x08000000); in al_eth_epe_init()
439 al_reg_write32(&adapter->ec_regs_base->epe[1].res_in, 0x7); in al_eth_epe_init()
444 for (idx = 0; idx < AL_ETH_EPE_ENTRIES_NUM; idx++) in al_eth_epe_init()
447 al_reg_write32(&adapter->ec_regs_base->epe[0].res_def, 0x08000080); in al_eth_epe_init()
448 al_reg_write32(&adapter->ec_regs_base->epe[0].res_in, 0x7); in al_eth_epe_init()
450 al_reg_write32(&adapter->ec_regs_base->epe[1].res_def, 0x08000080); in al_eth_epe_init()
451 al_reg_write32(&adapter->ec_regs_base->epe[1].res_in, 0); in al_eth_epe_init()
480 al_dbg("[%s]: %s - reg %d. val 0x%x", in al_eth_40g_mac_reg_read()
503 al_dbg("[%s]: %s - reg %d. val 0x%x", in al_eth_40g_mac_reg_write()
525 al_dbg("[%s]: %s - reg %d. val 0x%x", in al_eth_40g_pcs_reg_read()
548 al_dbg("[%s]: %s - reg %d. val 0x%x", in al_eth_40g_pcs_reg_write()
580 adapter->ec_ints_base = (uint8_t __iomem *)adapter->ec_regs_base + 0x1c00; in al_eth_adapter_init()
582 ((uint8_t __iomem *)adapter->mac_regs_base + 0x800); in al_eth_adapter_init()
591 if (rc != 0) { in al_eth_adapter_init()
597 if (rc != 0) { in al_eth_adapter_init()
609 if (rc != 0) { in al_eth_adapter_init()
616 if (rc != 0) { in al_eth_adapter_init()
626 conf.max_pkt_size = 0xfffff; in al_eth_adapter_init()
644 for (i = 0; i < 4; i++) { in al_eth_adapter_init()
646 al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_1, 0x00000000); in al_eth_adapter_init()
647 al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_2, 0x00000000); in al_eth_adapter_init()
648 al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_3, 0x00000000); in al_eth_adapter_init()
649 al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_4, 0x00000000); in al_eth_adapter_init()
652 // only udma 0 allowed to init ec in al_eth_adapter_init()
653 if (adapter->udma_id != 0) { in al_eth_adapter_init()
654 return 0; in al_eth_adapter_init()
658 al_reg_write32(&adapter->ec_regs_base->gen.en, 0xffffffff); in al_eth_adapter_init()
659 al_reg_write32(&adapter->ec_regs_base->gen.fifo_en, 0xffffffff); in al_eth_adapter_init()
683 al_reg_write32(&adapter->ec_regs_base->mac.gen, 0x00000001); in al_eth_adapter_init()
688 al_reg_write32(&adapter->ec_regs_base->tfw_udma[0].fwd_dec, 0x000003fb); in al_eth_adapter_init()
690 /* RFW configuration: default 0 */ in al_eth_adapter_init()
691 al_reg_write32(&adapter->ec_regs_base->rfw_default[0].opt_1, 0x00000001); in al_eth_adapter_init()
694 al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_addr, 0x00000000); in al_eth_adapter_init()
696 al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_data, 0x00000000); in al_eth_adapter_init()
697 /* HASH config (select toeplitz and bits 7:0 of the thash result, enable in al_eth_adapter_init()
707 reg &= ~0x7F00; /*clear bits 14:8 */ in al_eth_adapter_init()
710 return 0; in al_eth_adapter_init()
723 // only udma 0 allowed to init ec in al_eth_ec_mac_ints_config()
724 if (adapter->udma_id != 0) in al_eth_ec_mac_ints_config()
754 return 0; in al_eth_ec_mac_ints_config()
763 * @return 0 on success. otherwise on failure.
770 // only udma 0 allowed to init ec in al_eth_ec_mac_isr()
771 if (adapter->udma_id != 0) in al_eth_ec_mac_isr()
776 al_dbg("[%s]: ethernet group A cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
780 al_dbg("[%s]: mac group A cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
783 al_dbg("[%s]: mac group B cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
786 al_dbg("[%s]: mac group C cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
789 al_dbg("[%s]: mac group D cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
792 al_dbg("[%s]: ethernet group B cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
794 al_dbg("[%s]: ethernet group C cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
796 al_dbg("[%s]: ethernet group D cause 0x%08x\n", adapter->name, cause); in al_eth_ec_mac_isr()
798 return 0; in al_eth_ec_mac_isr()
812 if (rc != 0) { in al_eth_adapter_stop()
822 if (rc != 0) { in al_eth_adapter_stop()
830 return 0; in al_eth_adapter_stop()
918 return 0; in al_eth_rx_pkt_limit_config()
926 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40003210); in al_eth_mac_config()
929 /* bit[0] - TX_ENA - zeroed by default. Should be asserted by al_eth_mac_start in al_eth_mac_config()
936 al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, 0x01800010); in al_eth_mac_config()
939 al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_empty, 0x00000000); in al_eth_mac_config()
941 …al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_full, 0x0000000c); /* must be larger tha… in al_eth_mac_config()
943 al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_empty, 0x00000008); in al_eth_mac_config()
945 al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_full, 0x00000008); in al_eth_mac_config()
949 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_empty, 0x00000008); /* 8 ? */ in al_eth_mac_config()
950 /* TX_SECTION_FULL, 0 - store and forward, */ in al_eth_mac_config()
951 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_full, 0x0000000c); in al_eth_mac_config()
953 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_empty, 0x00000008); in al_eth_mac_config()
955 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_full, 0x00000008); in al_eth_mac_config()
958 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000000); in al_eth_mac_config()
963 al_reg_write32(&adapter->mac_regs_base->gen.mac_1g_cfg, 0x00000002); in al_eth_mac_config()
965 …al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x000… in al_eth_mac_config()
966 al_reg_write32(&adapter->mac_regs_base->gen.rgmii_sel, 0xF); in al_eth_mac_config()
972 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010); in al_eth_mac_config()
974 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800); in al_eth_mac_config()
976 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080); in al_eth_mac_config()
978 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020); in al_eth_mac_config()
980 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000121); in al_eth_mac_config()
982 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */ in al_eth_mac_config()
984 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */ in al_eth_mac_config()
986 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020); in al_eth_mac_config()
988 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080); in al_eth_mac_config()
990 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000212); in al_eth_mac_config()
992 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000); in al_eth_mac_config()
993 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000001); in al_eth_mac_config()
994 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000); in al_eth_mac_config()
995 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
997 al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333); in al_eth_mac_config()
1003 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40053210); in al_eth_mac_config()
1006 /* bit[0] - TX_ENA - zeroed by default. Should be asserted by al_eth_mac_start in al_eth_mac_config()
1013 al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, 0x01800010); in al_eth_mac_config()
1016 al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_empty, 0x00000000); in al_eth_mac_config()
1018 …al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_full, 0x0000000c); /* must be larger tha… in al_eth_mac_config()
1020 al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_empty, 0x00000008); in al_eth_mac_config()
1022 al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_full, 0x00000008); in al_eth_mac_config()
1026 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_empty, 0x00000008); /* 8 ? */ in al_eth_mac_config()
1027 /* TX_SECTION_FULL, 0 - store and forward, */ in al_eth_mac_config()
1028 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_full, 0x0000000c); in al_eth_mac_config()
1030 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_empty, 0x00000008); in al_eth_mac_config()
1032 al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_full, 0x00000008); in al_eth_mac_config()
1035 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x000000c0); in al_eth_mac_config()
1040 al_reg_write32(&adapter->mac_regs_base->gen.mac_1g_cfg, 0x00000002); in al_eth_mac_config()
1042 …al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x000… in al_eth_mac_config()
1043 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); in al_eth_mac_config()
1044 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); in al_eth_mac_config()
1048 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000012); in al_eth_mac_config()
1049 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x00000040); in al_eth_mac_config()
1050 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000013); in al_eth_mac_config()
1051 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x00000000); in al_eth_mac_config()
1055 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000014); in al_eth_mac_config()
1056 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x0000000b); in al_eth_mac_config()
1058 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000004); in al_eth_mac_config()
1059 al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x000009A0); in al_eth_mac_config()
1069 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010); in al_eth_mac_config()
1071 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800); in al_eth_mac_config()
1073 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080); in al_eth_mac_config()
1075 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020); in al_eth_mac_config()
1077 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023); in al_eth_mac_config()
1079 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020); in al_eth_mac_config()
1081 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080); in al_eth_mac_config()
1083 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000012); in al_eth_mac_config()
1085 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000); in al_eth_mac_config()
1086 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1087 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000); in al_eth_mac_config()
1088 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000050); in al_eth_mac_config()
1090 al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333); in al_eth_mac_config()
1094 al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022830); in al_eth_mac_config()
1096 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000001); in al_eth_mac_config()
1097 al_reg_write32(&adapter->mac_regs_base->mac_10g.if_mode, 0x00000028); in al_eth_mac_config()
1098 al_reg_write32(&adapter->mac_regs_base->mac_10g.control, 0x00001140); in al_eth_mac_config()
1100 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401); in al_eth_mac_config()
1101 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */ in al_eth_mac_config()
1102 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401); in al_eth_mac_config()
1103 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */ in al_eth_mac_config()
1105 ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00063910); in al_eth_mac_config()
1106 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40003210); in al_eth_mac_config()
1107 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); in al_eth_mac_config()
1108 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); in al_eth_mac_config()
1119 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010); in al_eth_mac_config()
1121 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800); in al_eth_mac_config()
1123 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080); in al_eth_mac_config()
1125 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020); in al_eth_mac_config()
1127 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023); in al_eth_mac_config()
1129 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */ in al_eth_mac_config()
1131 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */ in al_eth_mac_config()
1133 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020); in al_eth_mac_config()
1135 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080); in al_eth_mac_config()
1137 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000012); in al_eth_mac_config()
1139 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000); in al_eth_mac_config()
1140 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1141 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000); in al_eth_mac_config()
1142 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000050); in al_eth_mac_config()
1144 al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333); in al_eth_mac_config()
1148 al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810); in al_eth_mac_config()
1150 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005); in al_eth_mac_config()
1152 al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007); in al_eth_mac_config()
1153 al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1); in al_eth_mac_config()
1154 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401); in al_eth_mac_config()
1155 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */ in al_eth_mac_config()
1156 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401); in al_eth_mac_config()
1157 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */ in al_eth_mac_config()
1159 ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00073910); in al_eth_mac_config()
1160 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210); in al_eth_mac_config()
1161 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); in al_eth_mac_config()
1162 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); in al_eth_mac_config()
1170 /* select 25G SERDES lane 0 and lane 1 */ in al_eth_mac_config()
1171 al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, 0x0002110f); in al_eth_mac_config()
1176 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010); in al_eth_mac_config()
1178 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800); in al_eth_mac_config()
1180 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080); in al_eth_mac_config()
1182 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020); in al_eth_mac_config()
1184 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023); in al_eth_mac_config()
1186 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */ in al_eth_mac_config()
1188 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */ in al_eth_mac_config()
1190 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020); in al_eth_mac_config()
1192 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080); in al_eth_mac_config()
1194 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000012); in al_eth_mac_config()
1196 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000); in al_eth_mac_config()
1197 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1198 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000); in al_eth_mac_config()
1199 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x000000a0); in al_eth_mac_config()
1201 al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333); in al_eth_mac_config()
1205 al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810); in al_eth_mac_config()
1207 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005); in al_eth_mac_config()
1209 al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007); in al_eth_mac_config()
1210 al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1); in al_eth_mac_config()
1211 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401); in al_eth_mac_config()
1212 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */ in al_eth_mac_config()
1213 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401); in al_eth_mac_config()
1214 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */ in al_eth_mac_config()
1216 if (adapter->serdes_lane == 0) in al_eth_mac_config()
1218 ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00073910); in al_eth_mac_config()
1220 al_reg_write32(&adapter->mac_regs_base->gen.mux_sel, 0x00077910); in al_eth_mac_config()
1222 if (adapter->serdes_lane == 0) in al_eth_mac_config()
1223 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210); in al_eth_mac_config()
1225 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10000101); in al_eth_mac_config()
1227 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); in al_eth_mac_config()
1228 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); in al_eth_mac_config()
1235 al_reg_write32(&adapter->mac_regs_base->gen.los_sel, 0x101); in al_eth_mac_config()
1242 al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810); in al_eth_mac_config()
1245 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000001); in al_eth_mac_config()
1247 al_reg_write32(&adapter->mac_regs_base->mac_10g.if_mode, 0x0000002b); in al_eth_mac_config()
1248 al_reg_write32(&adapter->mac_regs_base->mac_10g.control, 0x00009140); in al_eth_mac_config()
1251 al_reg_write32(&adapter->mac_regs_base->mac_10g.link_timer_lo, 0x00000040); in al_eth_mac_config()
1252 al_reg_write32(&adapter->mac_regs_base->mac_10g.link_timer_hi, 0x00000000); in al_eth_mac_config()
1256 al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007); in al_eth_mac_config()
1257 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401); in al_eth_mac_config()
1258 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */ in al_eth_mac_config()
1259 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401); in al_eth_mac_config()
1260 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */ in al_eth_mac_config()
1262 ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00063910); in al_eth_mac_config()
1263 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40003210); in al_eth_mac_config()
1264 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); in al_eth_mac_config()
1274 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010); in al_eth_mac_config()
1276 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800); in al_eth_mac_config()
1278 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080); in al_eth_mac_config()
1280 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00010040); in al_eth_mac_config()
1282 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023); in al_eth_mac_config()
1284 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */ in al_eth_mac_config()
1286 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */ in al_eth_mac_config()
1288 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00010040); in al_eth_mac_config()
1290 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080); in al_eth_mac_config()
1292 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000112); in al_eth_mac_config()
1294 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000010); in al_eth_mac_config()
1295 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1296 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000); in al_eth_mac_config()
1297 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1299 al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333); in al_eth_mac_config()
1302 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, 0x00000008); in al_eth_mac_config()
1303 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, 0x01022810); in al_eth_mac_config()
1305 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, 0x00000008); */ in al_eth_mac_config()
1307 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, 0x00000002); */ in al_eth_mac_config()
1310 al_eth_40g_pcs_reg_write(adapter, 0x00010004, 1023); in al_eth_mac_config()
1311 al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0xA04c); in al_eth_mac_config()
1312 al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0x204c); in al_eth_mac_config()
1318 ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x06883910); in al_eth_mac_config()
1319 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x0000040f); in al_eth_mac_config()
1322 /* al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810); */ in al_eth_mac_config()
1324 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005); in al_eth_mac_config()
1326 al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007); in al_eth_mac_config()
1327 al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1); in al_eth_mac_config()
1328 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401); in al_eth_mac_config()
1329 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */ in al_eth_mac_config()
1330 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401); in al_eth_mac_config()
1331 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */ in al_eth_mac_config()
1332 /* al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x… in al_eth_mac_config()
1333 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210); in al_eth_mac_config()
1334 /* al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); *//* XLG_LL_40G change */ in al_eth_mac_config()
1335 /* al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); *//* XLG_LL_40G change */ in al_eth_mac_config()
1343 /* xgmii_mode: 0=xlgmii, 1=xgmii */ in al_eth_mac_config()
1344 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, 0x0080); in al_eth_mac_config()
1345 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, 0x00000001); in al_eth_mac_config()
1349 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010); in al_eth_mac_config()
1351 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800); in al_eth_mac_config()
1353 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080); in al_eth_mac_config()
1355 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00010040); in al_eth_mac_config()
1357 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023); in al_eth_mac_config()
1359 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */ in al_eth_mac_config()
1361 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */ in al_eth_mac_config()
1363 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00010040); in al_eth_mac_config()
1365 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080); in al_eth_mac_config()
1367 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000112); in al_eth_mac_config()
1369 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000010); in al_eth_mac_config()
1370 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1371 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000); in al_eth_mac_config()
1372 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1374 al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333); in al_eth_mac_config()
1377 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, 0x00000008); in al_eth_mac_config()
1378 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, 0x01022810); in al_eth_mac_config()
1380 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, 0x00000008); */ in al_eth_mac_config()
1382 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, 0x00000002); */ in al_eth_mac_config()
1384 /* select the 25G serdes for lanes 0/1 */ in al_eth_mac_config()
1385 al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, 0x0002110f); in al_eth_mac_config()
1388 /* use VL 0-2 for RXLAUI lane 0, use VL 1-3 for RXLAUI lane 1 */ in al_eth_mac_config()
1389 al_eth_40g_pcs_reg_write(adapter, 0x00010008, 0x0d80); in al_eth_mac_config()
1391 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_cfg, 0x00440000); in al_eth_mac_config()
1394 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, 0xE); in al_eth_mac_config()
1395 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, 0); in al_eth_mac_config()
1398 al_eth_40g_pcs_reg_write(adapter, 0x00010004, 1023); in al_eth_mac_config()
1399 al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0xA04c); in al_eth_mac_config()
1400 al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0x204c); in al_eth_mac_config()
1404 if (adapter->serdes_lane == 0) in al_eth_mac_config()
1406 ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x06883910); in al_eth_mac_config()
1408 al_reg_write32(&adapter->mac_regs_base->gen.mux_sel, 0x06803950); in al_eth_mac_config()
1410 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x0000040f); in al_eth_mac_config()
1413 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005); in al_eth_mac_config()
1415 al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007); in al_eth_mac_config()
1416 al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1); in al_eth_mac_config()
1417 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401); in al_eth_mac_config()
1418 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401); in al_eth_mac_config()
1419 if (adapter->serdes_lane == 0) in al_eth_mac_config()
1420 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210); in al_eth_mac_config()
1422 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10000101); in al_eth_mac_config()
1429 al_reg_write32(&adapter->mac_regs_base->gen.los_sel, 0x101); in al_eth_mac_config()
1437 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010); in al_eth_mac_config()
1439 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800); in al_eth_mac_config()
1441 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080); in al_eth_mac_config()
1443 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00010040); in al_eth_mac_config()
1445 al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023); in al_eth_mac_config()
1447 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */ in al_eth_mac_config()
1449 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */ in al_eth_mac_config()
1451 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00010040); in al_eth_mac_config()
1453 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080); in al_eth_mac_config()
1455 al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000112); in al_eth_mac_config()
1457 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000010); in al_eth_mac_config()
1458 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1459 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000); in al_eth_mac_config()
1460 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000); in al_eth_mac_config()
1462 al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333); in al_eth_mac_config()
1465 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, 0x00000008); in al_eth_mac_config()
1466 al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, 0x01022810); in al_eth_mac_config()
1468 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, 0x00000008); */ in al_eth_mac_config()
1470 /* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, 0x00000002); */ in al_eth_mac_config()
1472 /* select the 25G serdes for lanes 0/1 */ in al_eth_mac_config()
1473 al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, 0x0382110F); in al_eth_mac_config()
1476 /* use VL 0-2 for RXLAUI lane 0, use VL 1-3 for RXLAUI lane 1 */ in al_eth_mac_config()
1477 al_eth_40g_pcs_reg_write(adapter, 0x00010008, 0x0d81); in al_eth_mac_config()
1479 al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_cfg, 0x00440000); in al_eth_mac_config()
1483 al_eth_40g_pcs_reg_write(adapter, 0x00010004, 1023); in al_eth_mac_config()
1484 al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0xA04c); in al_eth_mac_config()
1485 al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0x204c); in al_eth_mac_config()
1489 …al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x068… in al_eth_mac_config()
1490 al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x0000040f); in al_eth_mac_config()
1493 /* al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810); */ in al_eth_mac_config()
1495 al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005); in al_eth_mac_config()
1497 al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007); in al_eth_mac_config()
1498 al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1); in al_eth_mac_config()
1499 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401); in al_eth_mac_config()
1500 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */ in al_eth_mac_config()
1501 al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401); in al_eth_mac_config()
1502 /* al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */ in al_eth_mac_config()
1503 /* al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x… in al_eth_mac_config()
1504 al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210); in al_eth_mac_config()
1505 /* al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); *//* XLG_LL_40G change */ in al_eth_mac_config()
1506 /* al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); *//* XLG_LL_40G change */ in al_eth_mac_config()
1521 return 0; in al_eth_mac_config()
1551 return 0; in al_eth_mac_start()
1561 0); in al_eth_mac_stop()
1566 0); in al_eth_mac_stop()
1581 return 0; in al_eth_mac_stop()
1627 0); in al_eth_fec_enable()
1628 return 0; in al_eth_fec_enable()
1640 return 0; in al_eth_fec_stats_get()
1677 return 0; in al_eth_capabilities_get()
1688 uint32_t sgmii_ctrl = 0; in al_eth_mac_link_config_1g_mac()
1689 uint32_t sgmii_if_mode = 0; in al_eth_mac_link_config_1g_mac()
1690 uint32_t rgmii_ctrl = 0; in al_eth_mac_link_config_1g_mac()
1699 * in case bit 0 is off in sgmii_if_mode register all the other in al_eth_mac_link_config_1g_mac()
1867 return 0; in al_eth_mac_link_config()
1911 return 0; in al_eth_mac_loopback_config()
1985 val &= ~(0x1FF << 7); in al_eth_mdio_config()
2000 return 0; in al_eth_mdio_config()
2009 return 0; in al_eth_mdio_1g_mac_read()
2018 return 0; in al_eth_mdio_1g_mac_write()
2023 int count = 0; in al_eth_mdio_10g_mac_wait_busy()
2030 al_err(" %s mdio read failed on error. phy_addr 0x%x reg 0x%x\n", in al_eth_mdio_10g_mac_wait_busy()
2034 if (mdio_cfg_status & AL_BIT(0)){ in al_eth_mdio_10g_mac_wait_busy()
2035 if (count > 0) in al_eth_mdio_10g_mac_wait_busy()
2038 return 0; in al_eth_mdio_10g_mac_wait_busy()
2062 mdio_cmd = (uint16_t)(0x1F & reg); in al_eth_mdio_10g_mac_type22()
2063 mdio_cmd |= (0x1F & phy_addr) << 5; in al_eth_mdio_10g_mac_type22()
2076 if (rc != 0) { in al_eth_mdio_10g_mac_type22()
2084 al_err(" %s mdio %s failed on error. phy_addr 0x%x reg 0x%x\n", in al_eth_mdio_10g_mac_type22()
2091 return 0; in al_eth_mdio_10g_mac_type22()
2110 mdio_cmd = (uint16_t)(0x1F & device); in al_eth_mdio_10g_mac_type45()
2111 mdio_cmd |= (0x1F & port_addr) << 5; in al_eth_mdio_10g_mac_type45()
2145 al_err(" %s mdio %s failed on error. port 0x%x, device 0x%x reg 0x%x\n", in al_eth_mdio_10g_mac_type45()
2152 return 0; in al_eth_mdio_10g_mac_type45()
2161 * @return 0 on success, -ETIMEDOUT on timeout.
2165 int count = 0; in al_eth_mdio_lock()
2169 return 0; /* nothing to do when interface is not shared */ in al_eth_mdio_lock()
2175 al_err(" %s mdio read failed on error. phy_addr 0x%x reg 0x%x\n", in al_eth_mdio_lock()
2179 if (mdio_ctrl_1 & AL_BIT(0)){ in al_eth_mdio_lock()
2180 if (count > 0) in al_eth_mdio_lock()
2183 return 0; in al_eth_mdio_lock()
2187 al_err(" %s mdio failed to take ownership. MDIO info reg: 0x%08x\n", in al_eth_mdio_lock()
2199 * @return 0.
2204 return 0; /* nothing to do when interface is not shared */ in al_eth_mdio_free()
2206 al_reg_write32(&adapter->mac_regs_base->gen.mdio_ctrl_1, 0); in al_eth_mdio_free()
2222 return 0; in al_eth_mdio_free()
2260 rc = al_eth_mdio_10g_mac_type22(adapter, 0, phy_addr, reg, &val); in al_eth_mdio_write()
2262 rc = al_eth_mdio_10g_mac_type45(adapter, 0, phy_addr, device, reg, &val); in al_eth_mdio_write()
2272 al_dbg("0x%08x\n", *(ptr++)); in al_dump_tx_desc()
2273 al_dbg("0x%08x\n", *(ptr++)); in al_dump_tx_desc()
2274 al_dbg("0x%08x\n", *(ptr++)); in al_dump_tx_desc()
2275 al_dbg("0x%08x\n", *(ptr++)); in al_dump_tx_desc()
2296 uint32_t total_len = 0; in al_dump_tx_pkt()
2364 for (i = 0; i < pkt->num_of_bufs; i++) { in al_dump_tx_pkt()
2365 …al_dbg("eth [%s %d]: buf[%d]: len 0x%08x. address 0x%016llx\n", tx_dma_q->udma->name, tx_dma_q->qi… in al_dump_tx_pkt()
2369 al_dbg("[%s %d]: total len: 0x%08x\n", tx_dma_q->udma->name, tx_dma_q->qid, total_len); in al_dump_tx_pkt()
2410 return 0; in al_eth_tx_pkt_prepare()
2421 uint32_t meta_word_0 = 0; in al_eth_tx_pkt_prepare()
2422 uint32_t meta_word_1 = 0; in al_eth_tx_pkt_prepare()
2423 uint32_t meta_word_2 = 0; in al_eth_tx_pkt_prepare()
2424 uint32_t meta_word_3 = 0; in al_eth_tx_pkt_prepare()
2464 meta_word_2 |= (pkt->meta->l4_header_len & 0x3f) << 16; in al_eth_tx_pkt_prepare()
2470 meta_word_0 |= (((pkt->meta->mss_val & 0x3c00) >> 10) in al_eth_tx_pkt_prepare()
2472 meta_word_2 |= ((pkt->meta->mss_val & 0x03ff) in al_eth_tx_pkt_prepare()
2537 for(buf_idx = 0; buf_idx < pkt->num_of_bufs; buf_idx++ ) { in al_eth_tx_pkt_prepare()
2556 if (buf_idx == 0) in al_eth_tx_pkt_prepare()
2584 if (rc != 0) { in al_eth_comp_tx_get()
2604 return 0; in al_eth_tso_mss_config()
2623 uint32_t reg_val = 0; in al_eth_rx_desc_config()
2626 EC_RFW_CFG_A_0_LRO_CONTEXT_SEL : 0; in al_eth_rx_desc_config()
2629 EC_RFW_CFG_A_0_META_L4_CHK_RES_SEL : 0; in al_eth_rx_desc_config()
2680 return 0; in al_eth_rx_header_split_config()
2696 return 0; in al_eth_rx_header_split_force_len_config()
2738 return 0; in al_eth_rx_buffer_add()
2765 if (rc == 0) in al_eth_pkt_rx()
2766 return 0; in al_eth_pkt_rx()
2773 pkt->rx_header_len = 0; in al_eth_pkt_rx()
2774 for (i = 0; i < rc; i++) { in al_eth_pkt_rx()
2782 if ((i == 0) && (swap32_from_le(rx_desc->word2) & in al_eth_pkt_rx()
2789 ((swap32_from_le(rx_desc->ctrl_meta) & AL_UDMA_CDESC_DDP) == 0)) in al_eth_pkt_rx()
2792 pkt->bufs[i].len = 0; in al_eth_pkt_rx()
2797 pkt->rx_desc_raw[0] = pkt->flags; in al_eth_pkt_rx()
2820 return 0; in al_eth_rx_parser_entry_update()
2823 #define AL_ETH_THASH_UDMA_SHIFT 0
2824 #define AL_ETH_THASH_UDMA_MASK (0xF << AL_ETH_THASH_UDMA_SHIFT)
2827 #define AL_ETH_THASH_Q_MASK (0x3 << AL_ETH_THASH_Q_SHIFT)
2839 return 0; in al_eth_thash_table_set()
2850 return 0; in al_eth_fsm_table_set()
2855 uint32_t val = 0; in al_eth_fwd_ctrl_entry_to_val()
2856 AL_REG_FIELD_SET(val, AL_FIELD_MASK(3,0), 0, entry->prio_sel); in al_eth_fwd_ctrl_entry_to_val()
2870 && (index->vlan_table_out != AL_REG_BIT_GET(i, 0))) in al_eth_ctrl_index_match()
2871 return 0; in al_eth_ctrl_index_match()
2874 return 0; in al_eth_ctrl_index_match()
2877 return 0; in al_eth_ctrl_index_match()
2880 return 0; in al_eth_ctrl_index_match()
2883 return 0; in al_eth_ctrl_index_match()
2886 return 0; in al_eth_ctrl_index_match()
2897 for (i = 0; i < AL_ETH_RX_CTRL_TABLE_SIZE; i++) { in al_eth_ctrl_table_set()
2903 return 0; in al_eth_ctrl_table_set()
2917 return 0; in al_eth_ctrl_table_def_set()
2928 return 0; in al_eth_ctrl_table_raw_set()
2935 return 0; in al_eth_ctrl_table_def_raw_set()
2945 return 0; in al_eth_hash_key_set()
2950 uint32_t val = 0; in al_eth_fwd_mac_table_entry_to_val()
2952 val |= (entry->filter == AL_TRUE) ? EC_FWD_MAC_CTRL_RX_VAL_DROP : 0; in al_eth_fwd_mac_table_entry_to_val()
2959 val |= (entry->rx_valid == AL_TRUE) ? EC_FWD_MAC_CTRL_RX_VALID : 0; in al_eth_fwd_mac_table_entry_to_val()
2964 val |= (entry->tx_valid == AL_TRUE) ? EC_FWD_MAC_CTRL_TX_VALID : 0; in al_eth_fwd_mac_table_entry_to_val()
2979 val = (entry->addr[0] << 8) | entry->addr[1]; in al_eth_fwd_mac_table_set()
2984 val = (entry->mask[0] << 8) | entry->mask[1]; in al_eth_fwd_mac_table_set()
2989 return 0; in al_eth_fwd_mac_table_set()
3003 return 0; in al_eth_fwd_mac_addr_raw_set()
3012 return 0; in al_eth_fwd_mac_ctrl_raw_set()
3024 val = (addr[0] << 8) | addr[1]; in al_eth_mac_addr_store()
3026 return 0; in al_eth_mac_addr_store()
3035 addr[5] = addr_lo & 0xff; in al_eth_mac_addr_read()
3036 addr[4] = (addr_lo >> 8) & 0xff; in al_eth_mac_addr_read()
3037 addr[3] = (addr_lo >> 16) & 0xff; in al_eth_mac_addr_read()
3038 addr[2] = (addr_lo >> 24) & 0xff; in al_eth_mac_addr_read()
3039 addr[1] = addr_hi & 0xff; in al_eth_mac_addr_read()
3040 addr[0] = (addr_hi >> 8) & 0xff; in al_eth_mac_addr_read()
3041 return 0; in al_eth_mac_addr_read()
3046 uint32_t val = 0; in al_eth_fwd_mhash_table_set()
3049 AL_REG_FIELD_SET(val, AL_FIELD_MASK(3,0), 0, udma_mask); in al_eth_fwd_mhash_table_set()
3054 return 0; in al_eth_fwd_mhash_table_set()
3058 uint32_t val = 0; in al_eth_fwd_vid_entry_to_val()
3059 AL_REG_BIT_VAL_SET(val, 0, entry->control); in al_eth_fwd_vid_entry_to_val()
3080 return 0; in al_eth_fwd_vid_config_set()
3092 return 0; in al_eth_fwd_vid_table_set()
3102 return 0; in al_eth_fwd_pbits_table_set()
3110 return 0; in al_eth_fwd_priority_table_set()
3122 return 0; in al_eth_fwd_dscp_table_set()
3133 return 0; in al_eth_fwd_tc_table_set()
3143 return 0; in al_eth_fwd_default_udma_config()
3153 return 0; in al_eth_fwd_default_queue_config()
3163 return 0; in al_eth_fwd_default_priority_config()
3174 if (udma_id == 0) { in al_eth_switching_config_set()
3190 return 0; in al_eth_switching_config_set()
3214 al_err("[%s]: unsupported filter options (0x%08x)\n", adapter->name, params->filters); in al_eth_filter_config()
3231 for (i = 0; i < AL_ETH_PROTOCOLS_NUM; i++) { in al_eth_filter_config()
3240 return 0; in al_eth_filter_config()
3252 al_err("[%s]: unsupported override filter options (0x%08x)\n", adapter->name, params->filters); in al_eth_filter_override_config()
3265 return 0; in al_eth_filter_override_config()
3277 return 0; in al_eth_switching_default_bitmap_set()
3324 al_reg_write32(&adapter->ec_regs_base->efc.ec_pause, 0); in al_eth_flow_control_config()
3332 al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 0); in al_eth_flow_control_config()
3341 for (i = 0; i < 4; i++) { in al_eth_flow_control_config()
3345 params->prio_q_map[i][0]); in al_eth_flow_control_config()
3347 al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_pause_0, 0); in al_eth_flow_control_config()
3351 al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_xoff_0, params->prio_q_map[i][0]); in al_eth_flow_control_config()
3353 al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_xoff_0, 0); in al_eth_flow_control_config()
3360 for (i = 0; i < 4; i++) { in al_eth_flow_control_config()
3362 for (prio = 0; prio < 8; prio++) { in al_eth_flow_control_config()
3369 0); in al_eth_flow_control_config()
3376 0); in al_eth_flow_control_config()
3383 al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 0xFF << EC_EFC_EC_XOFF_MASK_2_SHIFT); in al_eth_flow_control_config()
3385 al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 0); in al_eth_flow_control_config()
3457 return 0; in al_eth_flow_control_config()
3467 return 0; in al_eth_vlan_mod_config()
3483 return 0; in al_eth_eee_get()
3492 if (params->enable == 0) { in al_eth_eee_config()
3494 al_reg_write32(&adapter->ec_regs_base->eee.cfg_e, 0); in al_eth_eee_config()
3495 return 0; in al_eth_eee_config()
3517 params->fast_wake ? 1 : 0); in al_eth_eee_config()
3546 return 0; in al_eth_eee_config()
3574 0 (default) – use the timestamp from the SOP info (10G MAC) in al_eth_ts_init()
3577 return 0; in al_eth_ts_init()
3594 return 0; in al_eth_tx_ts_val_get()
3611 return 0; in al_eth_pth_systime_read()
3620 /* bits 31:14 of the clock period lsb register contains bits 17:0 of the in al_eth_pth_clk_period_write()
3628 return 0; in al_eth_pth_clk_period_write()
3651 return 0; in al_eth_pth_int_update_config()
3669 return 0; in al_eth_pth_int_update_time_set()
3687 return 0; in al_eth_pth_ext_update_config()
3706 return 0; in al_eth_pth_ext_update_time_set()
3721 return 0; in al_eth_pth_read_compensation_set()
3736 return 0; in al_eth_pth_int_write_compensation_set()
3751 return 0; in al_eth_pth_ext_write_compensation_set()
3766 return 0; in al_eth_pth_sync_compensation_set()
3818 return 0; in al_eth_pth_pulse_out_config()
3863 if ((reg & AL_BIT(3)) == 0) in al_eth_link_status_get()
3883 if ((reg & 0xF) == 0xF) { in al_eth_link_status_get()
3901 if ((reg & 0x1F) == 0x1F) { in al_eth_link_status_get()
3904 ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_LOC_FAULT)) == 0) in al_eth_link_status_get()
3917 return 0; in al_eth_link_status_get()
3922 int status = 0; in al_eth_link_status_clear()
3939 uint32_t reg = 0; in al_eth_led_set()
3958 return 0; in al_eth_led_set()
3966 al_memset(stats, 0, sizeof(struct al_eth_mac_stats)); in al_eth_mac_stats_get()
3997 stats->aFrameTooLongErrors = 0; /* N/A */ in al_eth_mac_stats_get()
3998 stats->aInRangeLengthErrors = 0; /* N/A */ in al_eth_mac_stats_get()
3999 stats->VLANTransmittedOK = 0; /* N/A */ in al_eth_mac_stats_get()
4000 stats->VLANReceivedOK = 0; /* N/A */ in al_eth_mac_stats_get()
4186 return 0; in al_eth_mac_stats_get()
4233 return 0; in al_eth_ec_stats_get()
4268 return 0; in al_eth_ec_stat_udma_get()
4284 int i = 0; in al_eth_flr_rmn()
4303 (*pci_read_config_u32)(handle, 0xC, &cfg_reg_store[i++]); in al_eth_flr_rmn()
4304 (*pci_read_config_u32)(handle, 0x10, &cfg_reg_store[i++]); in al_eth_flr_rmn()
4305 (*pci_read_config_u32)(handle, 0x18, &cfg_reg_store[i++]); in al_eth_flr_rmn()
4306 (*pci_read_config_u32)(handle, 0x20, &cfg_reg_store[i++]); in al_eth_flr_rmn()
4307 (*pci_read_config_u32)(handle, 0x110, &cfg_reg_store[i++]); in al_eth_flr_rmn()
4313 i = 0; in al_eth_flr_rmn()
4315 (*pci_write_config_u32)(handle, 0xC, cfg_reg_store[i++]); in al_eth_flr_rmn()
4316 (*pci_write_config_u32)(handle, 0x10, cfg_reg_store[i++]); in al_eth_flr_rmn()
4317 (*pci_write_config_u32)(handle, 0x18, cfg_reg_store[i++]); in al_eth_flr_rmn()
4318 (*pci_write_config_u32)(handle, 0x20, cfg_reg_store[i++]); in al_eth_flr_rmn()
4319 (*pci_write_config_u32)(handle, 0x110, cfg_reg_store[i++]); in al_eth_flr_rmn()
4324 al_reg_write32(&mac_regs_base->sgmii.clk_div, 0x03320501); in al_eth_flr_rmn()
4337 al_reg_write32(&mac_regs_base->sgmii.clk_div, 0x00320501); in al_eth_flr_rmn()
4341 AL_REG_MASK_SET(reg, 0xF0); in al_eth_flr_rmn()
4344 AL_REG_MASK_CLEAR(reg, 0xF0); in al_eth_flr_rmn()
4347 return 0; in al_eth_flr_rmn()
4358 struct al_eth_board_params params = { .media_type = 0 }; in al_eth_flr_rmn_restore_params()
4368 al_eth_mac_addr_read(ec_base, 0, mac_addr); in al_eth_flr_rmn_restore_params()
4372 al_eth_mac_addr_store(ec_base, 0, mac_addr); in al_eth_flr_rmn_restore_params()
4378 #define AL_HAL_ETH_MEDIA_TYPE_MASK (AL_FIELD_MASK(3, 0))
4379 #define AL_HAL_ETH_MEDIA_TYPE_SHIFT 0
4403 #define AL_HAL_ETH_DONT_OVERRIDE_SERDES_SHIFT 0
4427 #define AL_HAL_ETH_GPIO_SFP_PRESENT_MASK (AL_FIELD_MASK(5, 0))
4428 #define AL_HAL_ETH_GPIO_SFP_PRESENT_SHIFT 0
4434 uint32_t reg = 0; in al_eth_board_params_set()
4462 (params->serdes_grp & AL_BIT(2)) ? 1 : 0); in al_eth_board_params_set()
4470 al_assert(reg != 0); in al_eth_board_params_set()
4475 reg = 0; in al_eth_board_params_set()
4501 (params->retimer_channel & AL_BIT(0))); in al_eth_board_params_set()
4505 (AL_REG_FIELD_GET(params->retimer_channel, 0x6, 1))); in al_eth_board_params_set()
4521 reg = 0; in al_eth_board_params_set()
4529 return 0; in al_eth_board_params_set()
4538 /* check if the register was initialized, 0 is not a valid value */ in al_eth_board_params_get()
4539 if (reg == 0) in al_eth_board_params_get()
4594 params->serdes_grp |= (AL_REG_BIT_GET(reg, AL_HAL_ETH_SERDES_GRP_2_SHIFT) ? AL_BIT(2) : 0); in al_eth_board_params_get()
4676 return 0; in al_eth_board_params_get()
4683 uint32_t mask = 0xff; in al_eth_byte_arr_to_reg()
4688 *reg = 0; in al_eth_byte_arr_to_reg()
4690 for (i = 0 ; i < num_bytes ; i++) { in al_eth_byte_arr_to_reg()
4700 uint32_t reg = 0; in al_eth_wol_enable()
4705 al_eth_byte_arr_to_reg(®, &wol->pswd[0], 4); in al_eth_wol_enable()
4715 al_eth_byte_arr_to_reg(®, &wol->ipv4[0], 4); in al_eth_wol_enable()
4722 al_eth_byte_arr_to_reg(®, &wol->ipv6[0], 4); in al_eth_wol_enable()
4751 return 0; in al_eth_wol_enable()
4757 al_reg_write32(&adapter->ec_regs_base->wol.wol_en, 0); in al_eth_wol_disable()
4759 return 0; in al_eth_wol_disable()
4765 uint32_t val = 0; in al_eth_tx_fwd_vid_table_set()
4767 AL_REG_FIELD_SET(val, AL_ETH_TX_VLAN_TABLE_UDMA_MASK, 0, udma_mask); in al_eth_tx_fwd_vid_table_set()
4772 return 0; in al_eth_tx_fwd_vid_table_set()
4815 return 0; in al_eth_tx_protocol_detect_table_entry_set()
4867 tx_gcp_entry->gcp_mask[0]); in al_eth_tx_generic_crc_table_entry_set()
4888 return 0; in al_eth_tx_generic_crc_table_entry_set()
4899 tx_replace_cmd = (uint32_t)(tx_replace_entry->l3_csum_en_00) << 0; in al_eth_tx_crc_chksum_replace_cmd_entry_set()
4906 tx_replace_cmd = (uint32_t)(tx_replace_entry->l3_csum_en_01) << 0; in al_eth_tx_crc_chksum_replace_cmd_entry_set()
4913 tx_replace_cmd = (uint32_t)(tx_replace_entry->l3_csum_en_10) << 0; in al_eth_tx_crc_chksum_replace_cmd_entry_set()
4920 tx_replace_cmd = (uint32_t)(tx_replace_entry->l3_csum_en_11) << 0; in al_eth_tx_crc_chksum_replace_cmd_entry_set()
4927 return 0; in al_eth_tx_crc_chksum_replace_cmd_entry_set()
4982 return 0; in al_eth_rx_protocol_detect_table_entry_set()
5033 rx_gcp_entry->gcp_mask[0]); in al_eth_rx_generic_crc_table_entry_set()
5054 return 0; in al_eth_rx_generic_crc_table_entry_set()
5064 /* [0] roce (with grh, bth) */
5065 {22, 0, 0, 0, 1,
5066 0x1f, 0x0, 0x0, 0x0, },
5068 {21, 0, 0, 0, 1,
5069 0x1f, 0x0, 0x0, 0x0, },
5071 {8, 23, 0, 0, 1,
5072 0x1f, 0x1f, 0x0, 0x0, },
5074 {11, 23, 0, 0, 1,
5075 0x1f, 0x1f, 0x0, 0x0, },
5077 {23, 0, 5, 0, 1,
5078 0x1f, 0x0, 0x5, 0x0, },
5080 {23, 0, 3, 0, 1,
5081 0x1f, 0x0, 0x5, 0x0 },
5083 {8, 2, 0, 0, 1,
5084 0x1f, 0x1f, 0x0, 0x0, },
5086 {11, 2, 0, 0, 1,
5087 0x1f, 0x1f, 0x0, 0x0, },
5089 {0, 0, 0, 0, 1,
5090 0x0, 0x0, 0x0, 0x0 }
5096 /* [0] roce (with grh, bth) */
5097 {0, 1, 1, 0, 1,
5098 0, 4, 8, 0, 1,
5099 0, 0, 0, 0, 0,
5100 0, 0, {0xffff7f03, 0x00000000, 0x00000000,
5101 0x00c00000, 0x00000000, 0x00000000}, 0xffffffff, 0x0,
5102 0},
5104 {0, 1, 0, 0, 1,
5105 0, 8, 14, 1, 1,
5106 0, 0, 0, 0, 0,
5107 0, 0, {0x00000000, 0x00000000, 0x00000000,
5108 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x0,
5109 0},
5111 {0, 1, 1, 0, 1,
5112 0, 4, 0, 0, 1,
5113 0, 0, 0, 0, 0,
5114 0, 0, {0x3000cf00, 0x00000f00, 0xc0000000,
5115 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x0,
5116 0},
5118 {0, 1, 1, 0, 1,
5119 0, 4, 0, 0, 1,
5120 0, 0, 0, 0, 0,
5121 0, 0, {0x7f030000, 0x00000000, 0x00000003,
5122 0x00c00000, 0x00000000, 0x00000000}, 0xffffffff, 0x0,
5123 0},
5125 {0, 1, 1, 0, 1,
5126 0, 4, 0, 0, 1,
5127 2, 0, 0, 0, 10,
5128 0, 0, {0x3000cf00, 0x00000f00, 0xc0000000,
5129 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x0,
5132 {0, 1, 1, 0, 1,
5133 0, 4, 0, 0, 1,
5134 2, 0, 0, 0, 10,
5135 0, 0, {0x7f030000, 0x00000000, 0x00000003,
5136 0x00c00000, 0x00000000, 0x00000000}, 0xffffffff, 0x0,
5139 {1, 1, 1, 0, 1,
5140 0, 4, 0, 0, 1,
5141 1, 0, 1, 0, 2,
5142 10, 0, {0x00000000, 0x00000000, 0x00000000,
5143 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x0,
5146 {1, 1, 1, 0, 1,
5147 0, 4, 0, 0, 1,
5148 1, 0, 1, 0, 2,
5149 10, 0, {0x00000000, 0x00000000, 0x00000000,
5150 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x0,
5153 {0, 0, 0, 0, 0,
5154 0, 0, 0, 0, 0,
5155 0, 0, 0, 0, 0,
5156 0, 0, {0x00000000, 0x00000000, 0x00000000,
5157 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x0,
5158 0}
5164 /* [0] roce (with grh, bth) */
5165 {0,1,0,1, 0,0,0,0, 0,0,0,0},
5167 {0,1,0,1, 0,0,0,0, 0,0,0,0},
5169 {0,0,1,1, 0,0,0,0, 0,1,0,1},
5171 {0,0,1,1, 0,0,0,0, 0,0,0,0},
5173 {0,1,0,1, 0,0,0,0, 0,0,0,0},
5175 {0,1,0,1, 0,0,0,0, 0,0,0,0},
5177 {0,0,1,1, 0,0,0,0, 0,1,0,1},
5179 {0,0,1,1, 0,0,0,0, 0,0,0,0},
5181 {0,0,0,0, 0,0,1,1, 0,1,0,1}
5187 /* [0] roce (with grh, bth) */
5188 {22, 0, 0, 0,
5189 0, 0, 0, 0, 1,
5190 0x1f, 0x0, 0x0, 0x0,
5191 0x4, 0x0, 0x0, 0x0},
5193 {21, 0, 0, 0,
5194 0, 0, 0, 0, 1,
5195 0x1f, 0x0, 0x0, 0x0,
5196 0x4, 0x0, 0x0, 0x0},
5198 {8, 23, 0, 0,
5199 0, 0, 0, 0, 1,
5200 0x1f, 0x1f, 0x0, 0x0,
5201 0x4, 0x0, 0x0, 0x0},
5203 {11, 23, 0, 0,
5204 0, 0, 0, 0, 1,
5205 0x1f, 0x1f, 0x0, 0x0,
5206 0x4, 0x0, 0x0, 0x0},
5208 {8, 13, 23, 0,
5209 0, 0, 0, 0, 1,
5210 0x1f, 0x1f, 0x1f, 0x0,
5211 0x4, 0x0, 0x0, 0x0},
5213 {11, 13, 23, 0,
5214 0, 0, 0, 0, 1,
5215 0x1f, 0x1f, 0x1f, 0x0,
5216 0x4, 0x0, 0x0, 0x0},
5218 {8, 0, 22, 0,
5219 4, 0, 0, 0, 1,
5220 0x1f, 0x0, 0x1f, 0x0,
5221 0x4, 0x0, 0x0, 0x0},
5223 {11, 0, 22, 0,
5224 4, 0, 0, 0, 1,
5225 0x1f, 0x0, 0x1f, 0x0,
5226 0x4, 0x0, 0x0, 0x0},
5228 {8, 0, 21, 0,
5229 4, 0, 0, 0, 1,
5230 0x1f, 0x0, 0x1f, 0x0,
5231 0x4, 0x0, 0x0, 0x0},
5233 {11, 0, 21, 0,
5234 4, 0, 0, 0, 1,
5235 0x1f, 0x0, 0x1f, 0x0,
5236 0x4, 0x0, 0x0, 0x0},
5238 {8, 0, 8, 23,
5239 4, 0, 0, 0, 1,
5240 0x1f, 0x0, 0x1f, 0x1f,
5241 0x4, 0x0, 0x0, 0x0},
5243 {11, 0, 8, 23,
5244 4, 0, 0, 0, 1,
5245 0x1f, 0x0, 0x1f, 0x1f,
5246 0x4, 0x0, 0x0, 0x0},
5248 {8, 0, 11, 23,
5249 4, 0, 0, 0, 1,
5250 0x1f, 0x0, 0x1f, 0x1f,
5251 0x4, 0x0, 0x0, 0x0},
5253 {11, 0, 11, 23,
5254 4, 0, 0, 0, 1,
5255 0x1f, 0x0, 0x1f, 0x1f,
5256 0x4, 0x0, 0x0, 0x0},
5258 {8, 0, 0, 0,
5259 0, 0, 0, 0, 1,
5260 0x1f, 0x1f, 0x0, 0x0,
5261 0x4, 0x0, 0x0, 0x0},
5263 {8, 12, 0, 0,
5264 0, 0, 0, 0, 1,
5265 0x1f, 0x1e, 0x0, 0x0,
5266 0x4, 0x0, 0x0, 0x0},
5268 {11, 0, 0, 0,
5269 0, 0, 0, 0, 1,
5270 0x1f, 0x1f, 0x0, 0x0,
5271 0x4, 0x0, 0x0, 0x0},
5273 {11, 12, 0, 0,
5274 0, 0, 0, 0, 1,
5275 0x1f, 0x1e, 0x0, 0x0,
5276 0x4, 0x0, 0x0, 0x0},
5278 {8, 0, 8, 0,
5279 4, 0, 0, 0, 1,
5280 0x1f, 0x0, 0x1f, 0x1f,
5281 0x4, 0x0, 0x0, 0x0},
5283 {8, 0, 8, 12,
5284 4, 0, 0, 0, 1,
5285 0x1f, 0x0, 0x1f, 0x1e,
5286 0x4, 0x0, 0x0, 0x0},
5288 {11, 0, 8, 0,
5289 4, 0, 0, 0, 1,
5290 0x1f, 0x0, 0x1f, 0x1f,
5291 0x4, 0x0, 0x0, 0x0},
5293 {11, 0, 8, 12,
5294 4, 0, 0, 0, 1,
5295 0x1f, 0x0, 0x1f, 0x1e,
5296 0x4, 0x0, 0x0, 0x0},
5298 {8, 0, 11, 0,
5299 4, 0, 0, 0, 1,
5300 0x1f, 0x0, 0x1f, 0x1f,
5301 0x4, 0x0, 0x0, 0x0},
5303 {8, 0, 11, 12,
5304 4, 0, 0, 0, 1,
5305 0x1f, 0x0, 0x1f, 0x1e,
5306 0x4, 0x0, 0x0, 0x0},
5308 {11, 0, 11, 0,
5309 4, 0, 0, 0, 1,
5310 0x1f, 0x0, 0x1f, 0x1f,
5311 0x4, 0x0, 0x0, 0x0},
5313 {11, 0, 11, 12,
5314 4, 0, 0, 0, 1,
5315 0x1f, 0x0, 0x1f, 0x1e,
5316 0x4, 0x0, 0x0, 0x0},
5318 {8, 2, 0, 0,
5319 0, 0, 0, 0, 1,
5320 0x1f, 0x1f, 0x0, 0x0,
5321 0x4, 0x0, 0x0, 0x0},
5323 {11, 2, 0, 0,
5324 0, 0, 0, 0, 1,
5325 0x1f, 0x1f, 0x0, 0x0,
5326 0x4, 0x0, 0x0, 0x0},
5328 {8, 0, 8, 2,
5329 4, 0, 0, 0, 1,
5330 0x18, 0x0, 0x1f, 0x1f,
5331 0x4, 0x0, 0x0, 0x0},
5333 {8, 0, 11, 2,
5334 4, 0, 0, 0, 1,
5335 0x18, 0x0, 0x1f, 0x1f,
5336 0x4, 0x0, 0x0, 0x0},
5338 {8, 0, 0, 0,
5339 4, 0, 0, 0, 1,
5340 0x1f, 0x0, 0x1f, 0x0,
5341 0x4, 0x0, 0x0, 0x0},
5343 {0, 0, 0, 0,
5344 0, 0, 0, 0, 1,
5345 0x0, 0x0, 0x0, 0x0,
5346 0x0, 0x0, 0x0, 0x0}
5352 /* [0] roce (with grh, bth) */
5353 {0, 1, 1, 0, 1,
5354 0, 4, 8, 0, 1,
5355 0, 0, 0, 0, 0,
5356 0, 0, {0xffff7f03, 0x00000000, 0x00000000,
5357 0x00c00000, 0x00000000, 0x00000000}, 0xffffffff, 0x03000010,
5358 0},
5360 {0, 1, 0, 0, 1,
5361 0, 8, 14, 1, 1,
5362 0, 0, 0, 0, 0,
5363 0, 0, {0x00000000, 0x00000000, 0x00000000,
5364 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x03000010,
5365 0},
5367 {0, 1, 1, 0, 1,
5368 0, 4, 0, 0, 1,
5369 0, 0, 0, 0, 0,
5370 0, 0, {0x3000cf00, 0x00000f00, 0xc0000000,
5371 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x03000011,
5372 0},
5374 {0, 1, 1, 0, 1,
5375 0, 4, 0, 0, 1,
5376 0, 0, 0, 0, 0,
5377 0, 0, {0x7f030000, 0x00000000, 0x00000003,
5378 0x00c00000, 0x00000000, 0x00000000}, 0xffffffff, 0x03000010,
5379 0},
5381 {0, 1, 1, 0, 1,
5382 0, 4, 0, 0, 1,
5383 2, 0, 0, 0, 10,
5384 0, 0, {0x3000cf00, 0x00000f00, 0xc0000000,
5385 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x0302201c,
5388 {0, 1, 1, 0, 1,
5389 0, 4, 0, 0, 1,
5390 2, 0, 0, 0, 10,
5391 0, 0, {0x7f030000, 0x00000000, 0x00000003,
5392 0x00c00000, 0x00000000, 0x00000000}, 0xffffffff, 0x03002018,
5395 {0, 1, 1, 0, 1,
5396 0, 4, 8, 0, 1,
5397 0, 0, 0, 1, 0,
5398 0, 0, {0xffff7f03, 0x00000000, 0x00000000,
5399 0x00c00000, 0x00000000, 0x00000000}, 0xffffffff, 0x03020014,
5400 0},
5402 {0, 1, 1, 0, 1,
5403 0, 4, 8, 0, 1,
5404 0, 0, 0, 1, 0,
5405 0, 0, {0xffff7f03, 0x00000000, 0x00000000,
5406 0x00c00000, 0x00000000, 0x00000000}, 0xffffffff, 0x03000010,
5407 0},
5409 {0, 1, 0, 0, 1,
5410 0, 8, 14, 1, 1,
5411 0, 0, 0, 1, 0,
5412 0, 0, {0x00000000, 0x00000000, 0x00000000,
5413 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x03020014,
5414 0},
5416 {0, 1, 0, 0, 1,
5417 0, 8, 14, 1, 1,
5418 0, 0, 0, 1, 0,
5419 0, 0, {0x00000000, 0x00000000, 0x00000000,
5420 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x03000010,
5421 0},
5423 {0, 1, 1, 0, 1,
5424 0, 4, 0, 0, 1,
5425 0, 0, 0, 1, 0,
5426 0, 0, {0x3000cf00, 0x00000f00, 0xc0000000,
5427 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x03020015,
5428 0},
5430 {0, 1, 1, 0, 1,
5431 0, 4, 0, 0, 1,
5432 0, 0, 0, 1, 0,
5433 0, 0, {0x3000cf00, 0x00000f00, 0xc0000000,
5434 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x03000011,
5435 0},
5437 {0, 1, 1, 0, 1,
5438 0, 4, 0, 0, 1,
5439 0, 0, 0, 1, 0,
5440 0, 0, {0x7f030000, 0x00000000, 0x00000003,
5441 0x00c00000, 0x00000000, 0x00000000}, 0xffffffff, 0x03020014,
5442 0},
5444 {0, 1, 1, 0, 1,
5445 0, 4, 0, 0, 1,
5446 0, 0, 0, 1, 0,
5447 0, 0, {0x7f030000, 0x00000000, 0x00000003,
5448 0x00c00000, 0x00000000, 0x00000000}, 0xffffffff, 0x03000010,
5449 0},
5451 {0, 0, 0, 0, 0,
5452 0, 0, 0, 0, 0,
5453 0, 0, 0, 0, 0,
5454 0, 0, {0x00000000, 0x00000000, 0x00000000,
5455 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x00000001,
5456 0},
5458 {0, 0, 0, 0, 0,
5459 0, 0, 0, 0, 0,
5460 0, 0, 0, 0, 0,
5461 0, 0, {0x00000000, 0x00000000, 0x00000000,
5462 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x00000003,
5463 0},
5465 {0, 0, 0, 0, 0,
5466 0, 0, 0, 0, 0,
5467 0, 0, 0, 0, 0,
5468 0, 0, {0x00000000, 0x00000000, 0x00000000,
5469 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x00000000,
5470 0},
5472 {0, 0, 0, 0, 0,
5473 0, 0, 0, 0, 0,
5474 0, 0, 0, 0, 0,
5475 0, 0, {0x00000000, 0x00000000, 0x00000000,
5476 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x00000002,
5477 0},
5479 {0, 0, 0, 0, 0,
5480 0, 0, 0, 0, 0,
5481 0, 0, 0, 0, 0,
5482 0, 0, {0x00000000, 0x00000000, 0x00000000,
5483 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x00020005,
5484 0},
5486 {0, 0, 0, 0, 0,
5487 0, 0, 0, 0, 0,
5488 0, 0, 0, 0, 0,
5489 0, 0, {0x00000000, 0x00000000, 0x00000000,
5490 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x00020007,
5491 0},
5493 {0, 0, 0, 0, 0,
5494 0, 0, 0, 0, 0,
5495 0, 0, 0, 0, 0,
5496 0, 0, {0x00000000, 0x00000000, 0x00000000,
5497 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x00000001,
5498 0},
5500 {0, 0, 0, 0, 0,
5501 0, 0, 0, 0, 0,
5502 0, 0, 0, 0, 0,
5503 0, 0, {0x00000000, 0x00000000, 0x00000000,
5504 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x00000003,
5505 0},
5507 {0, 0, 0, 0, 0,
5508 0, 0, 0, 0, 0,
5509 0, 0, 0, 0, 0,
5510 0, 0, {0x00000000, 0x00000000, 0x00000000,
5511 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x00020004,
5512 0},
5514 {0, 0, 0, 0, 0,
5515 0, 0, 0, 0, 0,
5516 0, 0, 0, 0, 0,
5517 0, 0, {0x00000000, 0x00000000, 0x00000000,
5518 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x00020006,
5519 0},
5521 {0, 0, 0, 0, 0,
5522 0, 0, 0, 0, 0,
5523 0, 0, 0, 0, 0,
5524 0, 0, {0x00000000, 0x00000000, 0x00000000,
5525 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x00000000,
5526 0},
5528 {0, 0, 0, 0, 0,
5529 0, 0, 0, 0, 0,
5530 0, 0, 0, 0, 0,
5531 0, 0, {0x00000000, 0x00000000, 0x00000000,
5532 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x00000002,
5533 0},
5535 {1, 1, 1, 0, 1,
5536 0, 4, 0, 0, 1,
5537 0, 0, 0, 2, 0,
5538 0, 0, {0x00000000, 0x00000000, 0x00000000,
5539 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x03000011,
5540 0},
5542 {1, 1, 1, 0, 1,
5543 0, 4, 0, 0, 1,
5544 0, 0, 0, 2, 0,
5545 0, 0, {0x00000000, 0x00000000, 0x00000000,
5546 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x03000010,
5547 0},
5549 {1, 1, 1, 0, 1,
5550 0, 4, 0, 0, 1,
5551 0, 0, 0, 3, 0,
5552 0, 0, {0x00000000, 0x00000000, 0x00000000,
5553 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x03000011,
5554 0},
5556 {1, 1, 1, 0, 1,
5557 0, 4, 0, 0, 1,
5558 0, 0, 0, 3, 0,
5559 0, 0, {0x00000000, 0x00000000, 0x00000000,
5560 0x00000000, 0x00000000, 0x00000000}, 0xffffffff, 0x03000010,
5561 0},
5563 {0, 0, 0, 0, 0,
5564 0, 0, 0, 0, 0,
5565 0, 0, 0, 0, 0,
5566 0, 0, {0x00000000, 0x00000000, 0x00000000,
5567 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x00020004,
5568 0},
5570 {0, 0, 0, 0, 0,
5571 0, 0, 0, 0, 0,
5572 0, 0, 0, 0, 0,
5573 0, 0, {0x00000000, 0x00000000, 0x00000000,
5574 0x00000000, 0x00000000, 0x00000000}, 0x00000000, 0x0,
5575 0}
5583 for (idx = 0; idx < AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM; idx++) in al_eth_tx_protocol_detect_table_init()
5587 return 0; in al_eth_tx_protocol_detect_table_init()
5596 al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_legacy, 0x0); in al_eth_tx_generic_crc_table_init()
5597 al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace, 0x0); in al_eth_tx_generic_crc_table_init()
5598 for (idx = 0; idx < AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM; idx++) in al_eth_tx_generic_crc_table_init()
5602 return 0; in al_eth_tx_generic_crc_table_init()
5610 for (idx = 0; idx < AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM; idx++) in al_eth_tx_crc_chksum_replace_cmd_init()
5614 return 0; in al_eth_tx_crc_chksum_replace_cmd_init()
5638 for (idx = 0; idx < AL_ETH_RX_PROTOCOL_DETECT_ENTRIES_NUM; idx++) in al_eth_rx_protocol_detect_table_init()
5641 return 0; in al_eth_rx_protocol_detect_table_init()
5652 al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_legacy, 0x0); in al_eth_rx_generic_crc_table_init()
5654 for (idx = 0; idx < AL_ETH_RX_PROTOCOL_DETECT_ENTRIES_NUM; idx++) in al_eth_rx_generic_crc_table_init()
5664 return 0; in al_eth_rx_generic_crc_table_init()