Lines Matching +full:0 +full:x00020004
33 #size-cells = <0>;
38 reg = <0x00000000 0x80000000 0 0x80000000>;
44 #clock-cells = <0>;
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
61 interrupts = <1 9 0x4>;
66 reg = <0x0 0x6020000 0 0x20000>;
72 reg = <0x0 0x1e60000 0x0 0x4>;
78 offset = <0x0>;
79 mask = <0x2>;
252 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
265 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
269 reg = <0 0x1300000 0 0xa0000>;
276 reg = <0x0 0x1e00000 0x0 0x10000>;
282 reg = <0x0 0x1e80000 0x0 0x10000>;
290 reg = <0x0 0x1f70000 0x0 0x10000>;
294 ranges = <0x0 0x0 0x1f70000 0x10000>;
299 #address-cells = <0>;
301 reg = <0x14 4>;
303 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
304 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
305 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
306 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
307 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
308 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
309 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
310 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
311 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
312 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
313 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
314 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
315 interrupt-map-mask = <0xf 0x0>;
321 reg = <0x0 0x1f80000 0x0 0x10000>;
322 interrupts = <0 23 0x4>;
323 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
325 <0x00000000 0x00000026>,
326 <0x00000001 0x0000002d>,
327 <0x00000002 0x00000032>,
328 <0x00000003 0x00000039>,
329 <0x00000004 0x0000003f>,
330 <0x00000005 0x00000046>,
331 <0x00000006 0x0000004d>,
332 <0x00000007 0x00000054>,
333 <0x00000008 0x0000005a>,
334 <0x00000009 0x00000061>,
335 <0x0000000a 0x0000006a>,
336 <0x0000000b 0x00000071>,
338 <0x00010000 0x00000025>,
339 <0x00010001 0x0000002c>,
340 <0x00010002 0x00000035>,
341 <0x00010003 0x0000003d>,
342 <0x00010004 0x00000045>,
343 <0x00010005 0x0000004e>,
344 <0x00010006 0x00000057>,
345 <0x00010007 0x00000061>,
346 <0x00010008 0x0000006b>,
347 <0x00010009 0x00000076>,
349 <0x00020000 0x00000029>,
350 <0x00020001 0x00000033>,
351 <0x00020002 0x0000003d>,
352 <0x00020003 0x00000049>,
353 <0x00020004 0x00000056>,
354 <0x00020005 0x00000061>,
355 <0x00020006 0x0000006d>,
357 <0x00030000 0x00000021>,
358 <0x00030001 0x0000002a>,
359 <0x00030002 0x0000003c>,
360 <0x00030003 0x0000004e>;
367 reg = <0x0 0x21c0500 0x0 0x100>;
370 interrupts = <0 32 0x4>; /* Level high type */
375 reg = <0x0 0x21c0600 0x0 0x100>;
378 interrupts = <0 32 0x4>; /* Level high type */
383 reg = <0x0 0x21d0500 0x0 0x100>;
386 interrupts = <0 33 0x4>; /* Level high type */
391 reg = <0x0 0x21d0600 0x0 0x100>;
394 interrupts = <0 33 0x4>; /* Level high type */
399 reg = <0x0 0xc000000 0x0 0x1000>;
409 reg = <0x0 0xc010000 0x0 0x1000>;
419 reg = <0x0 0xc100000 0x0 0x1000>;
429 reg = <0x0 0xc110000 0x0 0x1000>;
439 reg = <0x0 0xc200000 0x0 0x1000>;
449 reg = <0x0 0xc210000 0x0 0x1000>;
459 reg = <0x0 0xc300000 0x0 0x1000>;
469 reg = <0x0 0xc310000 0x0 0x1000>;
478 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
482 ranges = <0x0 0x00 0x8000000 0x100000>;
483 reg = <0x00 0x8000000 0x0 0x100000>;
488 compatible = "fsl,sec-v5.0-job-ring",
489 "fsl,sec-v4.0-job-ring";
490 reg = <0x10000 0x10000>;
495 compatible = "fsl,sec-v5.0-job-ring",
496 "fsl,sec-v4.0-job-ring";
497 reg = <0x20000 0x10000>;
502 compatible = "fsl,sec-v5.0-job-ring",
503 "fsl,sec-v4.0-job-ring";
504 reg = <0x30000 0x10000>;
509 compatible = "fsl,sec-v5.0-job-ring",
510 "fsl,sec-v4.0-job-ring";
511 reg = <0x40000 0x10000>;
518 reg = <0x00000000 0x08340020 0 0x2>;
523 reg = <0x0 0x8b95000 0x0 0x100>;
532 reg = <0x0 0x8b96000 0x0 0x1000>;
535 #size-cells = <0>;
544 reg = <0x0 0x8b97000 0x0 0x1000>;
547 #size-cells = <0>;
556 reg = <0x0 0x8c07000 0x0 0x1000>;
559 #size-cells = <0>;
562 pcs1: ethernet-phy@0 {
563 reg = <0>;
569 reg = <0x0 0x8c0b000 0x0 0x1000>;
572 #size-cells = <0>;
575 pcs2: ethernet-phy@0 {
576 reg = <0>;
582 reg = <0x0 0x8c0f000 0x0 0x1000>;
585 #size-cells = <0>;
588 pcs3: ethernet-phy@0 {
589 reg = <0>;
595 reg = <0x0 0x8c13000 0x0 0x1000>;
598 #size-cells = <0>;
601 pcs4: ethernet-phy@0 {
602 reg = <0>;
608 reg = <0x0 0x8c17000 0x0 0x1000>;
611 #size-cells = <0>;
614 pcs5: ethernet-phy@0 {
615 reg = <0>;
621 reg = <0x0 0x8c1b000 0x0 0x1000>;
624 #size-cells = <0>;
627 pcs6: ethernet-phy@0 {
628 reg = <0>;
634 reg = <0x0 0x8c1f000 0x0 0x1000>;
637 #size-cells = <0>;
640 pcs7: ethernet-phy@0 {
641 reg = <0>;
647 reg = <0x0 0x8c23000 0x0 0x1000>;
650 #size-cells = <0>;
653 pcs8: ethernet-phy@0 {
654 reg = <0>;
660 reg = <0x0 0x8c27000 0x0 0x1000>;
663 #size-cells = <0>;
666 pcs9: ethernet-phy@0 {
667 reg = <0>;
673 reg = <0x0 0x8c2b000 0x0 0x1000>;
676 #size-cells = <0>;
679 pcs10: ethernet-phy@0 {
680 reg = <0>;
686 reg = <0x0 0x8c2f000 0x0 0x1000>;
689 #size-cells = <0>;
692 pcs11: ethernet-phy@0 {
693 reg = <0>;
699 reg = <0x0 0x8c33000 0x0 0x1000>;
702 #size-cells = <0>;
705 pcs12: ethernet-phy@0 {
706 reg = <0>;
712 reg = <0x0 0x8c37000 0x0 0x1000>;
715 #size-cells = <0>;
718 pcs13: ethernet-phy@0 {
719 reg = <0>;
725 reg = <0x0 0x8c3b000 0x0 0x1000>;
728 #size-cells = <0>;
731 pcs14: ethernet-phy@0 {
732 reg = <0>;
738 reg = <0x0 0x8c3f000 0x0 0x1000>;
741 #size-cells = <0>;
744 pcs15: ethernet-phy@0 {
745 reg = <0>;
751 reg = <0x0 0x8c43000 0x0 0x1000>;
754 #size-cells = <0>;
757 pcs16: ethernet-phy@0 {
758 reg = <0>;
764 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
765 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
767 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
773 * Region type 0x0 - MC portals
774 * Region type 0x1 - QBMAN portals
776 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
777 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
784 #size-cells = <0>;
788 reg = <0x1>;
794 reg = <0x2>;
800 reg = <0x3>;
806 reg = <0x4>;
812 reg = <0x5>;
818 reg = <0x6>;
824 reg = <0x7>;
830 reg = <0x8>;
836 reg = <0x9>;
842 reg = <0xa>;
848 reg = <0xb>;
854 reg = <0xc>;
860 reg = <0xd>;
866 reg = <0xe>;
872 reg = <0xf>;
878 reg = <0x10>;
886 reg = <0 0x5000000 0 0x800000>;
889 stream-match-mask = <0x7C00>;
891 interrupts = <0 13 4>, /* global secure fault */
892 <0 14 4>, /* combined secure interrupt */
893 <0 15 4>, /* global non-secure fault */
894 <0 16 4>, /* combined non-secure interrupt */
895 /* performance counter interrupts 0-7 */
896 <0 211 4>, <0 212 4>,
897 <0 213 4>, <0 214 4>,
898 <0 215 4>, <0 216 4>,
899 <0 217 4>, <0 218 4>,
901 <0 146 4>, <0 147 4>,
902 <0 148 4>, <0 149 4>,
903 <0 150 4>, <0 151 4>,
904 <0 152 4>, <0 153 4>,
905 <0 154 4>, <0 155 4>,
906 <0 156 4>, <0 157 4>,
907 <0 158 4>, <0 159 4>,
908 <0 160 4>, <0 161 4>,
909 <0 162 4>, <0 163 4>,
910 <0 164 4>, <0 165 4>,
911 <0 166 4>, <0 167 4>,
912 <0 168 4>, <0 169 4>,
913 <0 170 4>, <0 171 4>,
914 <0 172 4>, <0 173 4>,
915 <0 174 4>, <0 175 4>,
916 <0 176 4>, <0 177 4>,
917 <0 178 4>, <0 179 4>,
918 <0 180 4>, <0 181 4>,
919 <0 182 4>, <0 183 4>,
920 <0 184 4>, <0 185 4>,
921 <0 186 4>, <0 187 4>,
922 <0 188 4>, <0 189 4>,
923 <0 190 4>, <0 191 4>,
924 <0 192 4>, <0 193 4>,
925 <0 194 4>, <0 195 4>,
926 <0 196 4>, <0 197 4>,
927 <0 198 4>, <0 199 4>,
928 <0 200 4>, <0 201 4>,
929 <0 202 4>, <0 203 4>,
930 <0 204 4>, <0 205 4>,
931 <0 206 4>, <0 207 4>,
932 <0 208 4>, <0 209 4>;
939 #size-cells = <0>;
940 reg = <0x0 0x2100000 0x0 0x10000>;
941 interrupts = <0 26 0x4>; /* Level high type */
951 reg = <0x0 0x2140000 0x0 0x10000>;
952 interrupts = <0 28 0x4>; /* Level high type */
963 reg = <0x0 0x2300000 0x0 0x10000>;
964 interrupts = <0 36 0x4>; /* Level high type */
974 reg = <0x0 0x2310000 0x0 0x10000>;
975 interrupts = <0 36 0x4>; /* Level high type */
985 reg = <0x0 0x2320000 0x0 0x10000>;
986 interrupts = <0 37 0x4>; /* Level high type */
996 reg = <0x0 0x2330000 0x0 0x10000>;
997 interrupts = <0 37 0x4>; /* Level high type */
1009 #size-cells = <0>;
1010 reg = <0x0 0x2000000 0x0 0x10000>;
1011 interrupts = <0 34 0x4>; /* Level high type */
1021 #size-cells = <0>;
1022 reg = <0x0 0x2010000 0x0 0x10000>;
1023 interrupts = <0 34 0x4>; /* Level high type */
1033 #size-cells = <0>;
1034 reg = <0x0 0x2020000 0x0 0x10000>;
1035 interrupts = <0 35 0x4>; /* Level high type */
1045 #size-cells = <0>;
1046 reg = <0x0 0x2030000 0x0 0x10000>;
1047 interrupts = <0 35 0x4>; /* Level high type */
1055 reg = <0x0 0x2240000 0x0 0x20000>;
1056 interrupts = <0 21 0x4>; /* Level high type */
1061 ranges = <0 0 0x5 0x80000000 0x08000000
1062 2 0 0x5 0x30000000 0x00010000
1063 3 0 0x5 0x20000000 0x00010000>;
1069 #size-cells = <0>;
1070 reg = <0x0 0x20c0000 0x0 0x10000>,
1071 <0x0 0x20000000 0x0 0x10000000>;
1085 interrupts = <0 108 0x4>; /* Level high type */
1092 bus-range = <0x0 0xff>;
1095 interrupt-map-mask = <0 0 0 7>;
1096 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1097 <0000 0 0 2 &gic 0 0 0 110 4>,
1098 <0000 0 0 3 &gic 0 0 0 111 4>,
1099 <0000 0 0 4 &gic 0 0 0 112 4>;
1100 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1107 interrupts = <0 113 0x4>; /* Level high type */
1114 bus-range = <0x0 0xff>;
1117 interrupt-map-mask = <0 0 0 7>;
1118 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1119 <0000 0 0 2 &gic 0 0 0 115 4>,
1120 <0000 0 0 3 &gic 0 0 0 116 4>,
1121 <0000 0 0 4 &gic 0 0 0 117 4>;
1122 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1129 interrupts = <0 118 0x4>; /* Level high type */
1136 bus-range = <0x0 0xff>;
1139 interrupt-map-mask = <0 0 0 7>;
1140 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1141 <0000 0 0 2 &gic 0 0 0 120 4>,
1142 <0000 0 0 3 &gic 0 0 0 121 4>,
1143 <0000 0 0 4 &gic 0 0 0 122 4>;
1144 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1151 interrupts = <0 123 0x4>; /* Level high type */
1158 bus-range = <0x0 0xff>;
1161 interrupt-map-mask = <0 0 0 7>;
1162 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1163 <0000 0 0 2 &gic 0 0 0 125 4>,
1164 <0000 0 0 3 &gic 0 0 0 126 4>,
1165 <0000 0 0 4 &gic 0 0 0 127 4>;
1166 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1173 reg = <0x0 0x3200000 0x0 0x10000>;
1174 interrupts = <0 133 0x4>; /* Level high type */
1183 reg = <0x0 0x3210000 0x0 0x10000>;
1184 interrupts = <0 136 0x4>; /* Level high type */
1195 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
1199 reg = <0x0 0x3100000 0x0 0x10000>;
1200 interrupts = <0 80 0x4>; /* Level high type */
1202 snps,quirk-frame-length-adjustment = <0x20>;
1210 reg = <0x0 0x3110000 0x0 0x10000>;
1211 interrupts = <0 81 0x4>; /* Level high type */
1213 snps,quirk-frame-length-adjustment = <0x20>;
1222 reg = <0x0 0x04000000 0x0 0x01000000>;
1223 interrupts = <0 12 4>;
1228 reg = <0x0 0x1e34040 0x0 0x18>;
1235 reg = <0x0 0x2800000 0x0 0x10000>;
1236 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1243 reg = <0x0 0x1080000 0x0 0x1000>;
1244 interrupts = <0 17 0x4>;
1250 reg = <0x0 0x1090000 0x0 0x1000>;
1251 interrupts = <0 18 0x4>;