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Searched +full:0 +full:x00010006 (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dbtc_dpm.c38 #define MC_CG_ARB_FREQ_F0 0x0a
39 #define MC_CG_ARB_FREQ_F1 0x0b
40 #define MC_CG_ARB_FREQ_F2 0x0c
41 #define MC_CG_ARB_FREQ_F3 0x0d
43 #define MC_CG_SEQ_DRAMCONF_S0 0x05
44 #define MC_CG_SEQ_DRAMCONF_S1 0x06
45 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
46 #define MC_CG_SEQ_YCLK_RESUME 0x0a
48 #define SMC_RAM_END 0x8000
58 0x000008f8, 0x00000010, 0xffffffff,
[all …]
H A Devergreen.c50 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
51 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
52 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
63 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_rreg()
74 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_wreg()
85 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_rreg()
96 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_wreg()
107 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_rreg()
118 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_wreg()
137 0x98fc,
[all …]
H A Dni_dpm.c37 #define MC_CG_ARB_FREQ_F0 0x0a
38 #define MC_CG_ARB_FREQ_F1 0x0b
39 #define MC_CG_ARB_FREQ_F2 0x0c
40 #define MC_CG_ARB_FREQ_F3 0x0d
42 #define SMC_RAM_END 0xC000
46 0x15,
47 0x2,
48 0x19,
49 0x2,
50 0x8,
[all …]
H A Dtrinity_dpm.c44 0x0000802c, 0xc0000000, 0xffffffff,
45 0x00003fc4, 0xc0000000, 0xffffffff,
46 0x00005448, 0x00000100, 0xffffffff,
47 0x000055e4, 0x00000100, 0xffffffff,
48 0x0000160c, 0x00000100, 0xffffffff,
49 0x00008984, 0x06000100, 0xffffffff,
50 0x0000c164, 0x00000100, 0xffffffff,
51 0x00008a18, 0x00000100, 0xffffffff,
52 0x0000897c, 0x06000100, 0xffffffff,
53 0x00008b28, 0x00000100, 0xffffffff,
[all …]
H A Dni.c70 0x98fc,
71 0x98f0,
72 0x9834,
73 0x9838,
74 0x9870,
75 0x9874,
76 0x8a14,
77 0x8b24,
78 0x8bcc,
79 0x8b10,
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml20 Register (IPBRR0) at offset 0x0BF8.
24 0x01900102 T1040
82 reg = <0xf0000 0x1000>;
83 interrupts = <18 2 0 0>;
84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
85 fsl,tmu-calibration = <0x00000000 0x00000025>,
86 <0x00000001 0x00000028>,
87 <0x00000002 0x0000002d>,
88 <0x00000003 0x00000031>,
89 <0x00000004 0x00000036>,
[all …]
/linux/include/soc/bcm2835/
H A Draspberrypi-firmware.h15 RPI_FIRMWARE_STATUS_REQUEST = 0,
16 RPI_FIRMWARE_STATUS_SUCCESS = 0x80000000,
17 RPI_FIRMWARE_STATUS_ERROR = 0x80000001,
37 RPI_FIRMWARE_PROPERTY_END = 0,
38 RPI_FIRMWARE_GET_FIRMWARE_REVISION = 0x00000001,
40 RPI_FIRMWARE_SET_CURSOR_INFO = 0x00008010,
41 RPI_FIRMWARE_SET_CURSOR_STATE = 0x00008011,
43 RPI_FIRMWARE_GET_BOARD_MODEL = 0x00010001,
44 RPI_FIRMWARE_GET_BOARD_REVISION = 0x00010002,
45 RPI_FIRMWARE_GET_BOARD_MAC_ADDRESS = 0x00010003,
[all …]
/linux/include/scsi/
H A Dsrp.h48 SRP_LOGIN_REQ = 0x00,
49 SRP_TSK_MGMT = 0x01,
50 SRP_CMD = 0x02,
51 SRP_I_LOGOUT = 0x03,
52 SRP_LOGIN_RSP = 0xc0,
53 SRP_RSP = 0xc1,
54 SRP_LOGIN_REJ = 0xc2,
55 SRP_T_LOGOUT = 0x80,
56 SRP_CRED_REQ = 0x81,
57 SRP_AER_REQ = 0x82,
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dt1023si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dt1040si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
38 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
54 arm,psci-suspend-param = <0x0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
92 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
93 <0x0 0x1402000 0 0x2000>, /* GICC */
94 <0x0 0x1404000 0 0x2000>, /* GICH */
[all …]
H A Dfsl-ls1088a.dtsi27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
42 reg = <0x1>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
51 reg = <0x2>;
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 reg = <0x3>;
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls1043a.dtsi37 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0>;
49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
58 reg = <0x1>;
59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
68 reg = <0x2>;
69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
78 reg = <0x3>;
79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls1046a.dtsi38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
44 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
53 reg = <0x1>;
54 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
63 reg = <0x2>;
64 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
73 reg = <0x3>;
74 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls208xa.dtsi33 #size-cells = <0>;
38 reg = <0x00000000 0x80000000 0 0x80000000>;
44 #clock-cells = <0>;
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
67 reg = <0x0 0x6020000 0 0x20000>;
73 reg = <0x0 0x1e60000 0x0 0x4>;
[all …]
H A Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
34 d-cache-size = <0x8000>;
45 reg = <0x1>;
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
51 d-cache-size = <0x8000>;
[all …]
/linux/drivers/message/fusion/lsi/
H A Dmpi_log_sas.h16 #define SAS_LOGINFO_NEXUS_LOSS 0x31170000
17 #define SAS_LOGINFO_MASK 0xFFFF0000
20 /* IOC LOGINFO defines, 0x00000000 - 0x0FFFFFFF */
23 /* Bits 27-24: IOC_LOGINFO_ORIGINATOR: 0=IOP, 1=PL, 2=IR */
25 /* Bits 15-0: LOGINFO_CODE Specific */
31 #define IOC_LOGINFO_ORIGINATOR_IOP (0x00000000)
32 #define IOC_LOGINFO_ORIGINATOR_PL (0x01000000)
33 #define IOC_LOGINFO_ORIGINATOR_IR (0x02000000)
35 #define IOC_LOGINFO_ORIGINATOR_MASK (0x0F000000)
40 #define IOC_LOGINFO_CODE_MASK (0x00FF0000)
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
H A Dgf119.fuc4.h3 /* 0x0000: proc_kern */
4 0x52544e49,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
[all …]
H A Dgk208.fuc5.h3 /* 0x0000: proc_kern */
4 0x52544e49,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
[all …]
H A Dgt215.fuc3.h3 /* 0x0000: proc_kern */
4 0x52544e49,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
[all …]
H A Dgf100.fuc3.h3 /* 0x0000: proc_kern */
4 0x52544e49,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
[all …]
/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a.dtsi31 #size-cells = <0>;
36 reg = <0xf00>;
37 clocks = <&clockgen 1 0>;
44 reg = <0xf01>;
45 clocks = <&clockgen 1 0>;
50 memory@0 {
52 reg = <0x0 0x0 0x0 0x0>;
57 #clock-cells = <0>;
80 offset = <0xb0>;
81 mask = <0x02>;
[all …]
/linux/include/linux/
H A Dhid.h57 #define HID_ITEM_FORMAT_SHORT 0
70 #define HID_ITEM_TYPE_MAIN 0
89 #define HID_MAIN_ITEM_CONSTANT 0x001
90 #define HID_MAIN_ITEM_VARIABLE 0x002
91 #define HID_MAIN_ITEM_RELATIVE 0x004
92 #define HID_MAIN_ITEM_WRAP 0x008
93 #define HID_MAIN_ITEM_NONLINEAR 0x010
94 #define HID_MAIN_ITEM_NO_PREFERRED 0x020
95 #define HID_MAIN_ITEM_NULL_STATE 0x040
96 #define HID_MAIN_ITEM_VOLATILE 0x080
[all …]
/linux/drivers/media/pci/cx23885/
H A Dcx23885-cards.c39 "\t\t Default: 0 [Disabled]");
48 .clk_freq = 0,
51 .vmux = 0,
68 .vmux = 0,
69 .gpio0 = 0xff00,
72 .vmux = 0,
73 .gpio0 = 0xff01,
77 .gpio0 = 0xff02,
81 .gpio0 = 0xff02,
90 .tuner_addr = 0x42, /* 0x84 >> 1 */
[all …]
/linux/drivers/scsi/lpfc/
H A Dlpfc_hw.h23 #define FDMI_DID 0xfffffaU
24 #define NameServer_DID 0xfffffcU
25 #define Fabric_Cntl_DID 0xfffffdU
26 #define Fabric_DID 0xfffffeU
27 #define Bcast_DID 0xffffffU
28 #define Mask_DID 0xffffffU
29 #define CT_DID_MASK 0xffff00U
30 #define Fabric_DID_MASK 0xfff000U
31 #define WELL_KNOWN_DID_MASK 0xfffff0U
42 0 */
[all …]