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/freebsd/sys/contrib/device-tree/src/riscv/sophgo/
H A Dsg2042.dtsi28 #clock-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
52 reg = <0x70 0x30005000 0x0 0x1000>;
54 #size-cells = <0>;
65 reg = <0x70 0x30006000 0x0 0x1000>;
67 #size-cells = <0>;
78 reg = <0x70 0x30007000 0x0 0x1000>;
80 #size-cells = <0>;
91 reg = <0x70 0x30008000 0x0 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124-nyan-blaze-emc.dtsi92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x00000008
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonBaseInfo.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
31 NoAddrMode = 0, // No addressing mode
41 NoMemAccess = 0,
53 TypePos = 0,
54 TypeMask = 0x7f,
58 SoloMask = 0x1,
61 SoloAXMask = 0x1,
64 RestrictSlot1AOKMask = 0x1,
68 PredicatedMask = 0x1,
70 PredicatedFalseMask = 0x1,
[all …]
/freebsd/sys/contrib/device-tree/src/mips/loongson/
H A Drs780e-pch.dtsi8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000
9 0 0x40000000 0 0x40000000 0 0x40000000
10 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
18 reg = <0 0x1a000000 0 0x02000000>;
20 ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x0000c000>,
21 <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
28 ranges = <1 0 0 0x18000000 0x4000>;
32 reg = <1 0x70 0x8>;
39 reg = <1 0x800 0x100>;
H A Dloongson64v_4core_virtio.dts12 #address-cells = <0>;
22 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
23 0 0x3ff00000 0 0x3ff00000 0x100000
24 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
28 reg = <0 0x3ff01400 0x64>;
37 loongson,parent_int_map = <0x00000001>, /* int0 */
38 <0xfffffffe>, /* int1 */
39 <0x00000000>, /* int2 */
40 <0x00000000>; /* int3 */
46 reg = <0 0x1fe001e0 0x8>;
[all …]
/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9287an.h22 #define AR9287_AN_RF2G3_CH0 0x7808
23 #define AR9287_AN_RF2G3_CH1 0x785c
24 #define AR9287_AN_RF2G3_DB1 0xE0000000
26 #define AR9287_AN_RF2G3_DB2 0x1C000000
28 #define AR9287_AN_RF2G3_OB_CCK 0x03800000
30 #define AR9287_AN_RF2G3_OB_PSK 0x00700000
32 #define AR9287_AN_RF2G3_OB_QAM 0x000E0000
34 #define AR9287_AN_RF2G3_OB_PAL_OFF 0x0001C000
37 #define AR9287_AN_TXPC0 0x7898
38 #define AR9287_AN_TXPC0_TXPCMODE 0x0000C000
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A Dfsl,qe-muram.yaml62 ranges = <0 0x00010000 0x0000c000>;
66 data-only@0{
69 reg = <0 0xc000>;
H A Dfsl,qe.yaml106 reg = <0xe0100000 0x480>;
107 ranges = <0 0xe0100000 0x00100000>;
110 brg-frequency = <0>;
111 bus-frequency = <0x179a7b00>;
113 0x04 0x05 0x0c 0x0d 0x14 0x15 0x1c 0x1d
114 0x24 0x25 0x2c 0x2d 0x34 0x35 0x88 0x89
115 0x98 0x99 0xa8 0xa9 0xb8 0xb9 0xc8 0xc9
116 0xd8 0xd9 0xe8 0xe9>;
120 reg = <0x80 0x80>;
123 interrupts = <95 2 0 0 94 2 0 0>;
[all …]
/freebsd/sys/dev/dc/
H A Dif_dcreg.h39 #define DC_BUSCTL 0x00 /* bus control */
40 #define DC_TXSTART 0x08 /* tx start demand */
41 #define DC_RXSTART 0x10 /* rx start demand */
42 #define DC_RXADDR 0x18 /* rx descriptor list start addr */
43 #define DC_TXADDR 0x20 /* tx descriptor list start addr */
44 #define DC_ISR 0x28 /* interrupt status register */
45 #define DC_NETCFG 0x30 /* network config register */
46 #define DC_IMR 0x38 /* interrupt mask */
47 #define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */
48 #define DC_SIO 0x48 /* MII and ROM/EEPROM access */
[all …]
/freebsd/sys/dev/rtwn/rtl8188e/
H A Dr88e_rx_desc.h27 #define R88E_RXDW3_RPT_M 0x0000c000
29 #define R88E_RXDW3_RPT_RX 0
58 #define R88E_RPTB6_PKT_NUM_M 0x0e
60 #define R88E_RPTB0_INT_CCX 0x80
63 #define R88E_RPTB1_MACID_M 0x3f
64 #define R88E_RPTB1_MACID_S 0
65 #define R88E_RPTB1_PKT_OK 0x40
66 #define R88E_RPTB1_BMC 0x80
69 #define R88E_RPTB2_RETRY_CNT_M 0x3f
70 #define R88E_RPTB2_RETRY_CNT_S 0
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Da3m071.dts26 ranges = <0 0xf0000000 0x0000c000>;
27 reg = <0xf0000000 0x00000100>;
28 bus-frequency = <0>; /* From boot loader */
29 system-frequency = <0>; /* From boot loader */
41 reg = <0x2000 0x100>;
42 interrupts = <2 1 0>;
63 reg = <0x2c00 0x100>;
64 interrupts = <2 4 0>;
73 reg = <0x03>;
94 ranges = <0 0 0xfc000000 0x02000000
[all …]
H A Da4m072.dts27 ranges = <0 0xf0000000 0x0000c000>;
28 reg = <0xf0000000 0x00000100>;
29 bus-frequency = <0>; /* From boot loader */
30 system-frequency = <0>; /* From boot loader */
33 fsl,init-ext-48mhz-en = <0x0>;
34 fsl,init-fd-enable = <0x01>;
35 fsl,init-fd-counters = <0x3333>;
44 reg = <0x2000 0x100>;
45 interrupts = <2 1 0>;
50 reg = <0x2200 0x100>;
[all …]
H A Dtqm5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
H A Dcharon.dts23 #size-cells = <0>;
25 PowerPC,5200@0 {
27 reg = <0>;
30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
32 timebase-frequency = <0>; // from bootloader
33 bus-frequency = <0>; // from bootloader
34 clock-frequency = <0>; // from bootloader
38 memory@0 {
40 reg = <0x00000000 0x08000000>; // 128MB
[all …]
H A Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_dcb_82598.h41 #define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin,
43 #define IXGBE_DPMCS_TRM 0x00000010 /* Transmit Recycle Mode */
44 #define IXGBE_DPMCS_ARBDIS 0x00000040 /* DCB arbiter disable */
45 #define IXGBE_DPMCS_TSOEF 0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
47 #define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */
50 #define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */
52 #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet
54 #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores
59 #define IXGBE_TDTQ2TCCR_GSP 0x40000000
60 #define IXGBE_TDTQ2TCCR_LSP 0x80000000
[all …]
/freebsd/sys/dev/irdma/
H A Dicrdma_hw.h40 #define VFPE_CQPTAIL1 0x0000a000
41 #define VFPE_CQPDB1 0x0000bc00
42 #define VFPE_CCQPSTATUS1 0x0000b800
43 #define VFPE_CCQPHIGH1 0x00009800
44 #define VFPE_CCQPLOW1 0x0000ac00
45 #define VFPE_CQARM1 0x0000b400
46 #define VFPE_CQARM1 0x0000b400
47 #define VFPE_CQACK1 0x0000b000
48 #define VFPE_AEQALLOC1 0x0000a400
49 #define VFPE_CQPERRCODES1 0x00009c00
[all …]
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dimx-weim.txt25 <cs-number> 0 <physical address of mapping> <size>
32 register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
36 IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
38 05 128M 0M 0M 0M
39 033 64M 64M 0M 0M
40 0113 64M 32M 32M 0M
44 what bootloader sets up in IOMUXC_GPR1[11:0] will be
75 reg = <0x021b8000 0x4000>;
79 ranges = <0 0 0x08000000 0x08000000>;
82 nor@0,0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/cirrus/
H A Dep7209.dtsi28 #address-cells = <0>;
29 #size-cells = <0>;
47 reg = <0x80000000 0xc000>;
53 reg = <0x80000000 0x4000>;
60 reg = <0x80000000 0x1 0x80000040 0x1>;
67 reg = <0x80000001 0x1 0x80000041 0x1>;
74 reg = <0x80000003 0x1 0x80000043 0x1>;
81 reg = <0x80000083 0x1 0x800000c3 0x1>;
88 reg = <0x80000100 0x80>;
96 reg = <0x80000180 0x80>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/fsl/
H A Dfsl,imx-weim.yaml21 pattern: "^memory-controller@[0-9a-f]+$"
63 WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
67 IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
69 05 128M 0M 0M 0M
70 033 64M 64M 0M 0M
71 0113 64M 32M 32M 0M
75 sets up in IOMUXC_GPR1[11:0] will be used.
90 "^.*@[0-7],[0-9a-f]+$":
133 "^.*@[0-7],[0-9a-f]+$":
149 "^.*@[0-7],[0-9a-f]+$":
[all …]
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dti,k3-dsp-rproc.yaml161 mailbox0_cluster3: mailbox-0 {
173 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
174 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */
175 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
176 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */
181 reg = <0x4d 0x80800000 0x00 0x00048000>,
182 <0x4d 0x80e00000 0x00 0x00008000>,
183 <0x4d 0x80f00000 0x00 0x00008000>;
187 ti,sci-proc-ids = <0x03 0xFF>;
198 reg = <0x00 0x64800000 0x00 0x00080000>,
[all …]
/freebsd/sys/contrib/ncsw/Peripherals/FM/Pcd/
H A Dfm_plcr.h49 #define FM_PCD_PLCR_PAR_GO 0x80000000
50 #define FM_PCD_PLCR_PAR_PWSEL_MASK 0x0000FFFF
51 #define FM_PCD_PLCR_PAR_R 0x40000000
57 #define FM_PCD_PLCR_PEMODE_PI 0x80000000
58 #define FM_PCD_PLCR_PEMODE_CBLND 0x40000000
59 #define FM_PCD_PLCR_PEMODE_ALG_MASK 0x30000000
60 #define FM_PCD_PLCR_PEMODE_ALG_RFC2698 0x10000000
61 #define FM_PCD_PLCR_PEMODE_ALG_RFC4115 0x20000000
62 #define FM_PCD_PLCR_PEMODE_DEFC_MASK 0x0C000000
63 #define FM_PCD_PLCR_PEMODE_DEFC_Y 0x04000000
[all …]
/freebsd/contrib/bearssl/src/symcipher/
H A Daes_ct_dec.c33 * S(x) = A(I(x)) ^ 0x63 in br_aes_ct_bitslice_invSbox()
35 * transform (0 is formally defined to be its own inverse). in br_aes_ct_bitslice_invSbox()
38 * iS(x) = B(S(B(x ^ 0x63)) ^ 0x63) in br_aes_ct_bitslice_invSbox()
40 * iS(S(y)) = B(A(I(B(A(I(y)) ^ 0x63 ^ 0x63))) ^ 0x63 ^ 0x63) = y in br_aes_ct_bitslice_invSbox()
51 q0 = ~q[0]; in br_aes_ct_bitslice_invSbox()
66 q[0] = q2 ^ q5 ^ q7; in br_aes_ct_bitslice_invSbox()
70 q0 = ~q[0]; in br_aes_ct_bitslice_invSbox()
85 q[0] = q2 ^ q5 ^ q7; in br_aes_ct_bitslice_invSbox()
93 for (i = 0; i < 8; i ++) { in add_round_key()
103 for (i = 0; i < 8; i ++) { in inv_shift_rows()
[all …]
/freebsd/sys/dev/usb/controller/
H A Dehcireg.h36 #define PCI_CBMEM 0x10 /* configuration base MEM */
37 #define PCI_INTERFACE_EHCI 0x20
38 #define PCI_USBREV 0x60 /* RO USB protocol revision */
39 #define PCI_USB_REV_MASK 0xff
40 #define PCI_USB_REV_PRE_1_0 0x00
41 #define PCI_USB_REV_1_0 0x10
42 #define PCI_USB_REV_1_1 0x11
43 #define PCI_USB_REV_2_0 0x20
44 #define PCI_EHCI_FLADJ 0x61 /* RW Frame len adj, SOF=59488+6*fladj */
45 #define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212phy.h23 #define AR_PHY_BASE 0x9800 /* base address of phy regs */
26 #define AR_PHY_TEST 0x9800 /* PHY test control */
27 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */
29 #define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */
30 #define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */
31 #define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */
33 #define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */
36 #define AR_PHY_TURBO 0x9804 /* frame control register */
37 #define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */
38 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
[all …]

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