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/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2hk.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
62 reg = <0x0c000000 0x600000>;
63 ranges = <0x0 0x0c000000 0x600000>;
68 reg = <0x5f0000 0x8000>;
78 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
79 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
80 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
81 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
[all …]
H A Dkeystone-k2l.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
49 reg = <0x02348400 0x100>;
59 reg = <0x02348800 0x100>;
66 reg = <0x02348000 0x100>;
110 reg = <0x02620690 0xc>;
112 #size-cells = <0>;
116 pinctrl-single,function-mask = <0x1>;
122 0x0 0x0 0xc0
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am62p.dtsi53 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
57 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
58 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
62 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62a.dtsi54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-j722s.dtsi24 #size-cells = <0>;
46 cpu0: cpu@0 {
48 reg = <0x000>;
51 i-cache-size = <0x8000>;
54 d-cache-size = <0x8000>;
58 clocks = <&k3_clks 135 0>;
63 reg = <0x001>;
66 i-cache-size = <0x8000>;
69 d-cache-size = <0x8000>;
73 clocks = <&k3_clks 136 0>;
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
H A Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
H A Dtegra30-asus-tf700t.dts92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "
[all...]
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
H A Dtegra124-apalis-emc.dtsi108 0x40040001 0x8000000a
109 0x00000001 0x00000001
110 0x00000002 0x00000000
111 0x00000002 0x00000001
112 0x00000003 0x00000008
113 0x00000003 0x00000002
114 0x00000003 0x00000006
115 0x06030203 0x000a0502
116 0x77e30303 0x70000f03
117 0x001f0000
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi104 0x40040001
105 0x8000000a
106 0x00000001
107 0x00000001
108 0x00000002
109 0x00000000
110 0x00000002
111 0x00000001
112 0x00000003
113 0x00000008
[all …]
H A Dtegra30-lg-p880.dts17 pinctrl-0 = <&state_default>;
120 emc-timings-0 {
122 nvidia,ram-code = <0>;
127 nvidia,emem-configuration = < 0x00050001 0xc0000010
128 0x00000001 0x00000001 0x00000002 0x00000000
129 0x00000003 0x00000001 0x00000002 0x00000004
130 0x00000001 0x00000000 0x00000002 0x00000002
131 0x02020001 0x00060402 0x77230303 0x001f0000 >;
137 nvidia,emem-configuration = < 0x00020001 0xc0000010
138 0x00000001 0x00000001 0x00000002 0x00000000
[all …]
H A Dtegra30-lg-p895.dts12 pinctrl-0 = <&state_default>;
123 nvidia,emem-configuration = < 0x00020001 0xc0000010
124 0x00000001 0x00000001 0x00000002 0x00000000
125 0x00000003 0x00000001 0x00000002 0x00000004
126 0x00000001 0x00000000 0x00000002 0x00000002
127 0x02020001 0x00060402 0x77230303 0x001f0000 >;
133 nvidia,emem-configuration = < 0x00030003 0xc0000010
134 0x00000001 0x00000001 0x00000002 0x00000000
135 0x00000003 0x00000001 0x00000002 0x00000004
136 0x00000001 0x00000000 0x00000002 0x00000002
[all …]
H A Dtegra124-nyan-blaze-emc.dtsi92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x00000008
[all …]
/freebsd/sys/dev/sound/pci/
H A Demuxkireg.h50 #define EMU_PTR 0x00
51 #define EMU_PTR_CHNO_MASK 0x0000003f
52 #define EMU_PTR_ADDR_MASK 0x07ff0000
53 #define EMU_A_PTR_ADDR_MASK 0x0fff0000
55 #define EMU_DATA 0x04
57 #define EMU_IPR 0x08
58 #define EMU_IPR_RATETRCHANGE 0x01000000
59 #define EMU_IPR_FXDSP 0x00800000
60 #define EMU_IPR_FORCEINT 0x00400000
61 #define EMU_PCIERROR 0x00200000
[all …]
/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9280v2.ini19 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
20 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
21 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
22 { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
23 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
24 { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
25 { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
26 { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
27 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
28 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dti,keystone-rproc.txt121 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
130 reg = <0x10800000 0x00100000>,
131 <0x10e00000 0x00008000>,
132 <0x10f00000 0x00008000>;
135 ti,syscon-dev = <&devctrl 0x40>;
136 resets = <&pscrst 0>;
138 interrupts = <0 8>;
140 kick-gpios = <&dspgpio0 27 0>;
160 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
169 reg = <0x10800000 0x00100000>,
[all …]
/freebsd/sys/dev/nge/
H A Dif_ngereg.h36 #define NGE_CSR 0x00
37 #define NGE_CFG 0x04
38 #define NGE_MEAR 0x08
39 #define NGE_PCITST 0x0C
40 #define NGE_ISR 0x10
41 #define NGE_IMR 0x14
42 #define NGE_IER 0x18
43 #define NGE_IHR 0x1C
44 #define NGE_TX_LISTPTR_LO 0x20
45 #define NGE_TX_LISTPTR_HI 0x24
[all …]
/freebsd/sys/dev/rtwn/rtl8821a/usb/
H A Dr21au_dfs.c66 rtwn_bb_setbits(sc, 0x924, 0x00008000, 0); in r21au_dfs_radar_disable()
72 return !!(rtwn_bb_read(sc, 0x924) & 0x00008000); in r21au_dfs_radar_is_enabled()
80 error = rtwn_bb_setbits(sc, 0x924, 0x00008000, 0); in r21au_dfs_radar_reset()
81 if (error != 0) in r21au_dfs_radar_reset()
84 return (rtwn_bb_setbits(sc, 0x924, 0, 0x00008000)); in r21au_dfs_radar_reset()
91 if (res != 0) \ in r21au_dfs_radar_enable()
93 } while(0) in r21au_dfs_radar_enable()
97 RTWN_CHK(rtwn_bb_setbits(sc, 0x814, 0x3fffffff, 0x04cc4d10)); in r21au_dfs_radar_enable()
98 RTWN_CHK(rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0xff, 0x06)); in r21au_dfs_radar_enable()
99 RTWN_CHK(rtwn_bb_write(sc, 0x918, 0x1c16ecdf)); in r21au_dfs_radar_enable()
[all …]
/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_kg.h81 uint32_t kgse_dv0; /**< KeyGen Scheme Entry Default Value 0 */
99 #define FM_KG_KGAR_GO 0x80000000
100 #define FM_KG_KGAR_READ 0x40000000
101 #define FM_KG_KGAR_WRITE 0x00000000
102 #define FM_KG_KGAR_SEL_SCHEME_ENTRY 0x00000000
103 #define FM_KG_KGAR_SCM_WSEL_UPDATE_CNT 0x00008000
105 #define KG_SCH_PP_SHIFT_HIGH 0x80000000
106 #define KG_SCH_PP_NO_GEN 0x10000000
107 #define KG_SCH_PP_SHIFT_LOW 0x0000F000
108 #define KG_SCH_MODE_NIA_PLCR 0x40000000
[all …]
/freebsd/sys/dev/lge/
H A Dif_lgereg.h37 #define LGE_MODE1 0x00 /* CSR00 */
38 #define LGE_MODE2 0x04 /* CSR01 */
39 #define LGE_PPTXBUF_IDX 0x08 /* CSR02 */
40 #define LGE_PRODID 0x0C /* CSR03 */
41 #define LGE_PPTXBUF_ADDR_LO 0x10 /* CSR04 */
42 #define LGE_PPTXBUF_ADDR_HI 0x14 /* CSR05 */
43 #define LGE_RSVD0 0x18 /* CSR06 */
44 #define LGE_PPRXBUF_IDX 0x1C /* CSR07 */
45 #define LGE_PPRXBUF_ADDR_LO 0x20 /* CSR08 */
46 #define LGE_PPRXBUF_ADDR_HI 0x24 /* CSR09 */
[all …]
/freebsd/sys/dev/age/
H A Dif_agereg.h36 #define VENDORID_ATTANSIC 0x1969
41 #define DEVICEID_ATTANSIC_L1 0x1048
43 #define AGE_VPD_REG_CONF_START 0x0100
44 #define AGE_VPD_REG_CONF_END 0x01FF
45 #define AGE_VPD_REG_CONF_SIG 0x5A
47 #define AGE_SPI_CTRL 0x200
48 #define SPI_STAT_NOT_READY 0x00000001
49 #define SPI_STAT_WR_ENB 0x00000002
50 #define SPI_STAT_WRP_ENB 0x00000080
51 #define SPI_INST_MASK 0x000000FF
[all …]
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dcpuid.h3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
17 /* Responses identification request with %eax 0 */
19 #define signature_AMD_ebx 0x68747541
20 #define signature_AMD_edx 0x69746e65
21 #define signature_AMD_ecx 0x444d4163
23 #define signature_CENTAUR_ebx 0x746e6543
24 #define signature_CENTAUR_edx 0x48727561
25 #define signature_CENTAUR_ecx 0x736c7561
27 #define signature_CYRIX_ebx 0x69727943
28 #define signature_CYRIX_edx 0x736e4978
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212phy.h23 #define AR_PHY_BASE 0x9800 /* base address of phy regs */
26 #define AR_PHY_TEST 0x9800 /* PHY test control */
27 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */
29 #define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */
30 #define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */
31 #define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */
33 #define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */
36 #define AR_PHY_TURBO 0x9804 /* frame control register */
37 #define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */
38 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
[all …]

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