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/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl507d.h27 #define NV_DISP_CORE_NOTIFIER_1 0x00000000
28 #define NV_DISP_CORE_NOTIFIER_1_SIZEOF 0x00000054
29 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0 0x00000000
30 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE 0:0
31 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE 0x00000000
32 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001
35 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1 0x00000001
36 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE 0:0
37 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE 0x00000000
38 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE 0x00000001
[all …]
H A Dcl827d.h28 …827D_HEAD_SET_BASE_LUT_LO(a) (0x00000840 + (a)*0x00000400)
30 #define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000)
31 #define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001)
33 #define NV827D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000)
34 #define NV827D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001)
36 …827D_HEAD_SET_BASE_LUT_HI(a) (0x00000844 + (a)*0x00000400)
37 #define NV827D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0
38 …827D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000085C + (a)*0x00000400)
39 #define NV827D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0
40 …T_OFFSET(a,b) (0x00000860 + (a)*0x00000400 + (b)*0x000…
[all …]
H A Dclc57d.h27 #define NVC57D_SET_CONTEXT_DMA_NOTIFIER (0x00000208)
28 #define NVC57D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
30 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0…
31 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0
32 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
33 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
35 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
36 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
38 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
39 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
[all …]
H A Dclc37d.h27 #define NV_DISP_NOTIFIER 0x00000000
28 #define NV_DISP_NOTIFIER_SIZEOF 0x00000010
29 #define NV_DISP_NOTIFIER__0 0x00000000
30 #define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0
33 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000
34 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001
39 #define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000
40 #define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001
41 #define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002
42 #define NV_DISP_NOTIFIER__1 0x00000001
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/linux/drivers/media/dvb-frontends/
H A Dstb0899_reg.h14 #define STB0899_DEV_ID 0xf000
15 #define STB0899_CHIP_ID (0x0f << 4)
18 #define STB0899_CHIP_REL (0x0f << 0)
19 #define STB0899_OFFST_CHIP_REL 0
22 #define STB0899_DEMOD 0xf40e
23 #define STB0899_MODECOEFF (0x01 << 0)
24 #define STB0899_OFFST_MODECOEFF 0
27 #define STB0899_RCOMPC 0xf410
28 #define STB0899_AGC1CN 0xf412
29 #define STB0899_AGC1REF 0xf413
[all …]
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler.h24 0xbf820001, 0xbf820121,
25 0xb8f4f802, 0x89748674,
26 0xb8f5f803, 0x8675ff75,
27 0x00000400, 0xbf850017,
28 0xc00a1e37, 0x00000000,
29 0xbf8c007f, 0x87777978,
30 0xbf840005, 0x8f728374,
31 0xb972e0c2, 0xbf800002,
32 0xb9740002, 0xbe801d78,
33 0xb8f5f803, 0x8675ff75,
[all …]
/linux/drivers/net/ethernet/smsc/
H A Dsmsc911x.h12 #define LAN9115 0x01150000
13 #define LAN9116 0x01160000
14 #define LAN9117 0x01170000
15 #define LAN9118 0x01180000
16 #define LAN9215 0x115A0000
17 #define LAN9216 0x116A0000
18 #define LAN9217 0x117A0000
19 #define LAN9218 0x118A0000
20 #define LAN9210 0x92100000
21 #define LAN9211 0x92110000
[all …]
/linux/arch/openrisc/include/asm/
H A Dspr_defs.h24 #define MAX_SPRS (0x10000)
27 #define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
41 #define SPR_VR (SPRGROUP_SYS + 0)
70 #define SPR_DMMUCR (SPRGROUP_DMMU + 0)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
78 #define SPR_IMMUCR (SPRGROUP_IMMU + 0)
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
[all …]
/linux/drivers/net/usb/
H A Dlan78xx.h9 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
10 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
11 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
32 #define TX_CMD_A_IGE_ (0x20000000)
33 #define TX_CMD_A_ICE_ (0x10000000)
34 #define TX_CMD_A_LSO_ (0x08000000)
35 #define TX_CMD_A_IPE_ (0x04000000)
36 #define TX_CMD_A_TPE_ (0x02000000)
37 #define TX_CMD_A_IVTG_ (0x01000000)
38 #define TX_CMD_A_RVTG_ (0x00800000)
[all …]
H A Dsmsc75xx.h12 #define TX_CMD_A_LSO (0x08000000)
13 #define TX_CMD_A_IPE (0x04000000)
14 #define TX_CMD_A_TPE (0x02000000)
15 #define TX_CMD_A_IVTG (0x01000000)
16 #define TX_CMD_A_RVTG (0x00800000)
17 #define TX_CMD_A_FCS (0x00400000)
18 #define TX_CMD_A_LEN (0x000FFFFF)
20 #define TX_CMD_B_MSS (0x3FFF0000)
23 #define TX_CMD_B_VTAG (0x0000FFFF)
26 #define RX_CMD_A_ICE (0x80000000)
[all …]
/linux/arch/powerpc/include/asm/
H A Dkeylargo.h10 /* "Pangea" chipset has keylargo device-id 0x25 while core99
11 * has device-id 0x22. The rev. of the pangea one is 0, so we
12 * fake an artificial rev. in keylargo_rev by oring 0x100
14 #define KL_PANGEA_REV 0x100
17 #define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
18 #define KEYLARGO_FCR0 0x38
19 #define KEYLARGO_FCR1 0x3c
20 #define KEYLARGO_FCR2 0x40
21 #define KEYLARGO_FCR3 0x44
22 #define KEYLARGO_FCR4 0x48
[all …]
/linux/arch/mips/include/asm/txx9/
H A Dtx4927pcic.h87 #define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
88 #define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
89 #define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
92 #define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
95 #define TX4927_PCIC_PBACFG_FIXPA 0x00000008
96 #define TX4927_PCIC_PBACFG_RPBA 0x00000004
97 #define TX4927_PCIC_PBACFG_PBAEN 0x00000002
98 #define TX4927_PCIC_PBACFG_BMCEN 0x00000001
101 #define TX4927_PCIC_PBASTATUS_ALL 0x00000001
102 #define TX4927_PCIC_PBASTATUS_BM 0x00000001
[all …]
/linux/drivers/net/ethernet/renesas/
H A Dravb.h39 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
40 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
42 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
43 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
44 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
45 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
46 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
50 CCC = 0x0000,
51 DBAT = 0x0004,
52 DLR = 0x0008,
[all …]
/linux/arch/mips/include/asm/mips-boards/
H A Dmsc01_pci.h19 #define MSC01_PCI_ID_OFS 0x0000
20 #define MSC01_PCI_SC2PMBASL_OFS 0x0208
21 #define MSC01_PCI_SC2PMMSKL_OFS 0x0218
22 #define MSC01_PCI_SC2PMMAPL_OFS 0x0228
23 #define MSC01_PCI_SC2PIOBASL_OFS 0x0248
24 #define MSC01_PCI_SC2PIOMSKL_OFS 0x0258
25 #define MSC01_PCI_SC2PIOMAPL_OFS 0x0268
26 #define MSC01_PCI_P2SCMSKL_OFS 0x0308
27 #define MSC01_PCI_P2SCMAPL_OFS 0x0318
28 #define MSC01_PCI_INTCFG_OFS 0x0600
[all …]
H A Dbonito64.h42 #define BONITO_BOOT_BASE 0x1fc00000
43 #define BONITO_BOOT_SIZE 0x00100000
45 #define BONITO_FLASH_BASE 0x1c000000
46 #define BONITO_FLASH_SIZE 0x03000000
48 #define BONITO_SOCKET_BASE 0x1f800000
49 #define BONITO_SOCKET_SIZE 0x00400000
51 #define BONITO_REG_BASE 0x1fe00000
52 #define BONITO_REG_SIZE 0x00040000
54 #define BONITO_DEV_BASE 0x1ff00000
55 #define BONITO_DEV_SIZE 0x00100000
[all …]
/linux/drivers/net/ethernet/sis/
H A Dsis900.h19 #define SIS900_TOTAL_SIZE 0x100
23 cr=0x0, //Command Register
24 cfg=0x4, //Configuration Register
25 mear=0x8, //EEPROM Access Register
26 ptscr=0xc, //PCI Test Control Register
27 isr=0x10, //Interrupt Status Register
28 imr=0x14, //Interrupt Mask Register
29 ier=0x18, //Interrupt Enable Register
30 epar=0x18, //Enhanced PHY Access Register
31 txdp=0x20, //Transmit Descriptor Pointer Register
[all …]
/linux/drivers/pcmcia/
H A Dyenta_socket.h7 #define CB_SOCKET_EVENT 0x00
8 #define CB_CSTSEVENT 0x00000001 /* Card status event */
9 #define CB_CD1EVENT 0x00000002 /* Card detect 1 change event */
10 #define CB_CD2EVENT 0x00000004 /* Card detect 2 change event */
11 #define CB_PWREVENT 0x00000008 /* PWRCYCLE change event */
13 #define CB_SOCKET_MASK 0x04
14 #define CB_CSTSMASK 0x00000001 /* Card status mask */
15 #define CB_CDMASK 0x00000006 /* Card detect 1&2 mask */
16 #define CB_PWRMASK 0x00000008 /* PWRCYCLE change mask */
18 #define CB_SOCKET_STATE 0x08
[all …]
/linux/arch/powerpc/include/asm/nohash/32/
H A Dmmu-44x.h10 #define PPC44x_MMUCR_TID 0x000000ff
11 #define PPC44x_MMUCR_STS 0x00010000
13 #define PPC44x_TLB_PAGEID 0
18 #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
19 #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
20 #define PPC44x_TLB_TS 0x00000100 /* Translation address space */
21 #define PPC44x_TLB_1K 0x00000000 /* Page sizes */
22 #define PPC44x_TLB_4K 0x00000010
23 #define PPC44x_TLB_16K 0x00000020
24 #define PPC44x_TLB_64K 0x00000030
[all …]
/linux/arch/nios2/boot/dts/
H A D3c120_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0 {
23 reg = <0x00000000>;
38 altr,reset-addr = <0xc2800000>;
39 altr,fast-tlb-miss-addr = <0xc7fff400>;
40 altr,exception-addr = <0xd0000020>;
46 memory@0 {
48 reg = <0x10000000 0x08000000>,
49 <0x07fff400 0x00000400>;
52 sopc@0 {
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am64.dtsi54 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
58 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
63 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
[all …]
/linux/sound/soc/fsl/
H A Dfsl_ssi.h15 /* SSI Transmit Data Register 0 */
16 #define REG_SSI_STX0 0x00
18 #define REG_SSI_STX1 0x04
19 /* SSI Receive Data Register 0 */
20 #define REG_SSI_SRX0 0x08
22 #define REG_SSI_SRX1 0x0c
24 #define REG_SSI_SCR 0x10
26 #define REG_SSI_SISR 0x14
28 #define REG_SSI_SIER 0x18
30 #define REG_SSI_STCR 0x1c
[all …]
/linux/arch/mips/ath25/
H A Dar2315_regs.h20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
29 #define AR2315_MISC_IRQ_UART0 0
43 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
44 #define AR2315_SPI_READ_SIZE 0x01000000
45 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
[all …]
/linux/arch/mips/include/asm/mach-au1x00/
H A Dau1100_mmc.h52 #define SD0_BASE 0xB0600000
53 #define SD1_BASE 0xB0680000
59 #define SD_TXPORT (0x0000)
60 #define SD_RXPORT (0x0004)
61 #define SD_CONFIG (0x0008)
62 #define SD_ENABLE (0x000C)
63 #define SD_CONFIG2 (0x0010)
64 #define SD_BLKSIZE (0x0014)
65 #define SD_STATUS (0x0018)
66 #define SD_DEBUG (0x001C)
[all …]
/linux/arch/mips/include/asm/sgi/
H A Dmc.h18 volatile u32 cpuctrl0; /* CPU control register 0, readwrite */
19 #define SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */
20 #define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */
21 #define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */
22 #define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */
23 #define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */
24 #define SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */
25 #define SGIMC_CCTRL0_SYSINIT 0x00000200 /* System init bit */
26 #define SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */
27 #define SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */
[all …]

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