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/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_default.h26 #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000
29 #define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000
30 #define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000
31 #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000
32 #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000
34 #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx25-karo-tx25.dts17 reg_fec_phy: regulator-0 {
22 gpio = <&gpio4 9 0>;
28 reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
35 MX25_PAD_UART1_TXD__UART1_TXD 0x00000020
36 MX25_PAD_UART1_RXD__UART1_RXD 0x000000a0
37 MX25_PAD_UART1_CTS__UART1_CTS 0x00000060
38 MX25_PAD_UART1_RTS__UART1_RTS 0x000000e0
44 MX25_PAD_D11__GPIO_4_9 0x00000021 /* FEC PHY power on pin */
45 MX25_PAD_D13__GPIO_4_7 0x000000a1 /* FEC reset */
46 MX25_PAD_FEC_MDC__FEC_MDC 0x00000060
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/linux/arch/openrisc/include/asm/
H A Dspr_defs.h24 #define MAX_SPRS (0x10000)
27 #define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
41 #define SPR_VR (SPRGROUP_SYS + 0)
70 #define SPR_DMMUCR (SPRGROUP_DMMU + 0)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
78 #define SPR_IMMUCR (SPRGROUP_IMMU + 0)
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
[all …]
/linux/drivers/net/ethernet/renesas/
H A Dravb.h39 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
40 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
42 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
43 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
44 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
45 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
46 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
50 CCC = 0x0000,
51 DBAT = 0x0004,
52 DLR = 0x0008,
[all …]
/linux/drivers/usb/gadget/udc/
H A Dmv_udc.h16 #define EP_DIR_OUT 0
18 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
22 #define WAIT_FOR_SETUP 0
28 #define CAPLENGTH_MASK (0xff)
29 #define DCCPARAMS_DEN_MASK (0x1f)
31 #define HCSPARAMS_PPC (0x10)
34 #define USB_FRINDEX_MASKS 0x3fff
37 #define USBCMD_RUN_STOP (0x00000001)
38 #define USBCMD_CTRL_RESET (0x00000002)
39 #define USBCMD_SETUP_TRIPWIRE_SET (0x00002000)
[all …]
H A Dfsl_usb2_udc.h17 #define USB_DR_SYS_OFFSET 0x400
105 #define WAIT_FOR_SETUP 0
112 #define DCCPARAMS_DC 0x00000080
113 #define DCCPARAMS_DEN_MASK 0x0000001f
116 #define USB_FRINDEX_MASKS 0x3fff
118 #define USB_CMD_RUN_STOP 0x00000001
119 #define USB_CMD_CTRL_RESET 0x00000002
120 #define USB_CMD_PERIODIC_SCHEDULE_EN 0x00000010
121 #define USB_CMD_ASYNC_SCHEDULE_EN 0x00000020
122 #define USB_CMD_INT_AA_DOORBELL 0x00000040
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/linux/sound/pci/cs46xx/
H A Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/linux/sound/soc/fsl/
H A Dfsl_ssi.h15 /* SSI Transmit Data Register 0 */
16 #define REG_SSI_STX0 0x00
18 #define REG_SSI_STX1 0x04
19 /* SSI Receive Data Register 0 */
20 #define REG_SSI_SRX0 0x08
22 #define REG_SSI_SRX1 0x0c
24 #define REG_SSI_SCR 0x10
26 #define REG_SSI_SISR 0x14
28 #define REG_SSI_SIER 0x18
30 #define REG_SSI_STCR 0x1c
[all …]
/linux/drivers/pcmcia/
H A Dyenta_socket.h7 #define CB_SOCKET_EVENT 0x00
8 #define CB_CSTSEVENT 0x00000001 /* Card status event */
9 #define CB_CD1EVENT 0x00000002 /* Card detect 1 change event */
10 #define CB_CD2EVENT 0x00000004 /* Card detect 2 change event */
11 #define CB_PWREVENT 0x00000008 /* PWRCYCLE change event */
13 #define CB_SOCKET_MASK 0x04
14 #define CB_CSTSMASK 0x00000001 /* Card status mask */
15 #define CB_CDMASK 0x00000006 /* Card detect 1&2 mask */
16 #define CB_PWRMASK 0x00000008 /* PWRCYCLE change mask */
18 #define CB_SOCKET_STATE 0x08
[all …]
/linux/sound/pci/vx222/
H A Dvx222.h32 #define VX2_AKM_LEVEL_MAX 0x93
38 #define VX_RESET_DMA_REGISTER_OFFSET 0x00000008
41 #define VX_INTCSR_VALUE 0x00000001
42 #define VX_PCI_INTERRUPT_MASK 0x00000040
44 /* Constants used to access the CDSP register (0x20). */
45 #define VX_CDSP_TEST1_MASK 0x00000080
46 #define VX_CDSP_TOR1_MASK 0x00000040
47 #define VX_CDSP_TOR2_MASK 0x00000020
48 #define VX_CDSP_RESERVED0_0_MASK 0x00000010
49 #define VX_CDSP_CODEC_RESET_MASK 0x00000008
[all …]
/linux/arch/mips/include/asm/txx9/
H A Dtx4927pcic.h87 #define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
88 #define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
89 #define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
92 #define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
95 #define TX4927_PCIC_PBACFG_FIXPA 0x00000008
96 #define TX4927_PCIC_PBACFG_RPBA 0x00000004
97 #define TX4927_PCIC_PBACFG_PBAEN 0x00000002
98 #define TX4927_PCIC_PBACFG_BMCEN 0x00000001
101 #define TX4927_PCIC_PBASTATUS_ALL 0x00000001
102 #define TX4927_PCIC_PBASTATUS_BM 0x00000001
[all …]
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler.h24 0xbf820001, 0xbf820121,
25 0xb8f4f802, 0x89748674,
26 0xb8f5f803, 0x8675ff75,
27 0x00000400, 0xbf850017,
28 0xc00a1e37, 0x00000000,
29 0xbf8c007f, 0x87777978,
30 0xbf840005, 0x8f728374,
31 0xb972e0c2, 0xbf800002,
32 0xb9740002, 0xbe801d78,
33 0xb8f5f803, 0x8675ff75,
[all …]
/linux/drivers/video/fbdev/geode/
H A Ddisplay_gx1.h21 #define CONFIG_CCR3 0xc3
22 # define CONFIG_CCR3_MAPEN 0x10
23 #define CONFIG_GCR 0xb8
27 #define MC_BANK_CFG 0x08
28 # define MC_BCFG_DIMM0_SZ_MASK 0x00000700
29 # define MC_BCFG_DIMM0_PG_SZ_MASK 0x00000070
30 # define MC_BCFG_DIMM0_PG_SZ_NO_DIMM 0x00000070
32 #define MC_GBASE_ADD 0x14
33 # define MC_GADD_GBADD_MASK 0x000003ff
37 #define DC_PAL_ADDRESS 0x70
[all …]
H A Dvideo_cs5530.h18 #define CS5530_VIDEO_CONFIG 0x0000
19 # define CS5530_VCFG_VID_EN 0x00000001
20 # define CS5530_VCFG_VID_REG_UPDATE 0x00000002
21 # define CS5530_VCFG_VID_INP_FORMAT 0x0000000C
22 # define CS5530_VCFG_8_BIT_4_2_0 0x00000004
23 # define CS5530_VCFG_16_BIT_4_2_0 0x00000008
24 # define CS5530_VCFG_GV_SEL 0x00000010
25 # define CS5530_VCFG_CSC_BYPASS 0x00000020
26 # define CS5530_VCFG_X_FILTER_EN 0x00000040
27 # define CS5530_VCFG_Y_FILTER_EN 0x00000080
[all …]
/linux/drivers/net/usb/
H A Dlan78xx.h9 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
10 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
11 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
32 #define TX_CMD_A_IGE_ (0x20000000)
33 #define TX_CMD_A_ICE_ (0x10000000)
34 #define TX_CMD_A_LSO_ (0x08000000)
35 #define TX_CMD_A_IPE_ (0x04000000)
36 #define TX_CMD_A_TPE_ (0x02000000)
37 #define TX_CMD_A_IVTG_ (0x01000000)
38 #define TX_CMD_A_RVTG_ (0x00800000)
[all …]
H A Dsmsc75xx.h12 #define TX_CMD_A_LSO (0x08000000)
13 #define TX_CMD_A_IPE (0x04000000)
14 #define TX_CMD_A_TPE (0x02000000)
15 #define TX_CMD_A_IVTG (0x01000000)
16 #define TX_CMD_A_RVTG (0x00800000)
17 #define TX_CMD_A_FCS (0x00400000)
18 #define TX_CMD_A_LEN (0x000FFFFF)
20 #define TX_CMD_B_MSS (0x3FFF0000)
23 #define TX_CMD_B_VTAG (0x0000FFFF)
26 #define RX_CMD_A_ICE (0x80000000)
[all …]
/linux/include/linux/mfd/
H A Dcs42l43-regs.h13 #define CS42L43_GEN_INT_STAT_1 0x000000C0
14 #define CS42L43_GEN_INT_MASK_1 0x000000C1
15 #define CS42L43_DEVID 0x00003000
16 #define CS42L43_REVID 0x00003004
17 #define CS42L43_RELID 0x0000300C
18 #define CS42L43_SFT_RESET 0x00003020
19 #define CS42L43_DRV_CTRL1 0x00006004
20 #define CS42L43_DRV_CTRL3 0x0000600C
21 #define CS42L43_DRV_CTRL4 0x00006010
22 #define CS42L43_DRV_CTRL_5 0x00006014
[all …]
/linux/arch/mips/ath25/
H A Dar2315_regs.h20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
29 #define AR2315_MISC_IRQ_UART0 0
43 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
44 #define AR2315_SPI_READ_SIZE 0x01000000
45 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
[all …]
/linux/arch/mips/include/asm/mips-boards/
H A Dmsc01_pci.h19 #define MSC01_PCI_ID_OFS 0x0000
20 #define MSC01_PCI_SC2PMBASL_OFS 0x0208
21 #define MSC01_PCI_SC2PMMSKL_OFS 0x0218
22 #define MSC01_PCI_SC2PMMAPL_OFS 0x0228
23 #define MSC01_PCI_SC2PIOBASL_OFS 0x0248
24 #define MSC01_PCI_SC2PIOMSKL_OFS 0x0258
25 #define MSC01_PCI_SC2PIOMAPL_OFS 0x0268
26 #define MSC01_PCI_P2SCMSKL_OFS 0x0308
27 #define MSC01_PCI_P2SCMAPL_OFS 0x0318
28 #define MSC01_PCI_INTCFG_OFS 0x0600
[all …]
H A Dbonito64.h42 #define BONITO_BOOT_BASE 0x1fc00000
43 #define BONITO_BOOT_SIZE 0x00100000
45 #define BONITO_FLASH_BASE 0x1c000000
46 #define BONITO_FLASH_SIZE 0x03000000
48 #define BONITO_SOCKET_BASE 0x1f800000
49 #define BONITO_SOCKET_SIZE 0x00400000
51 #define BONITO_REG_BASE 0x1fe00000
52 #define BONITO_REG_SIZE 0x00040000
54 #define BONITO_DEV_BASE 0x1ff00000
55 #define BONITO_DEV_SIZE 0x00100000
[all …]
/linux/drivers/media/platform/qcom/venus/
H A Dhfi_helper.h9 #define HFI_DOMAIN_BASE_COMMON 0
11 #define HFI_DOMAIN_BASE_VDEC 0x1000000
12 #define HFI_DOMAIN_BASE_VENC 0x2000000
13 #define HFI_DOMAIN_BASE_VPE 0x3000000
15 #define HFI_VIDEO_ARCH_OX 0x1
17 #define HFI_ARCH_COMMON_OFFSET 0
18 #define HFI_ARCH_OX_OFFSET 0x200000
20 #define HFI_OX_BASE 0x1000000
22 #define HFI_CMD_START_OFFSET 0x10000
23 #define HFI_MSG_START_OFFSET 0x20000
[all …]
/linux/arch/mips/include/asm/
H A Dtxx9tmr.h31 #define TXx9_TMTCR_TCE 0x00000080
32 #define TXx9_TMTCR_CCDE 0x00000040
33 #define TXx9_TMTCR_CRE 0x00000020
34 #define TXx9_TMTCR_ECES 0x00000008
35 #define TXx9_TMTCR_CCS 0x00000004
36 #define TXx9_TMTCR_TMODE_MASK 0x00000003
37 #define TXx9_TMTCR_TMODE_ITVL 0x00000000
38 #define TXx9_TMTCR_TMODE_PGEN 0x00000001
39 #define TXx9_TMTCR_TMODE_WDOG 0x00000002
42 #define TXx9_TMTISR_TPIBS 0x00000004
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/falcon/
H A Dga102.c30 return (nvkm_falcon_rd32(falcon, falcon->addr2 + 0x388) & 0x00000080) != 0; in ga102_flcn_riscv_active()
36 return !!(nvkm_falcon_rd32(falcon, 0x118) & 0x00000002); in ga102_flcn_dma_done()
42 nvkm_falcon_wr32(falcon, 0x114, mem_base); in ga102_flcn_dma_xfer()
43 nvkm_falcon_wr32(falcon, 0x11c, dma_base); in ga102_flcn_dma_xfer()
44 nvkm_falcon_wr32(falcon, 0x118, cmd); in ga102_flcn_dma_xfer()
53 *cmd |= 0x00000010; in ga102_flcn_dma_init()
55 *cmd |= 0x00000004; in ga102_flcn_dma_init()
57 nvkm_falcon_wr32(falcon, 0x110, dma_addr >> 8); in ga102_flcn_dma_init()
58 nvkm_falcon_wr32(falcon, 0x128, 0x00000000); in ga102_flcn_dma_init()
59 return 0; in ga102_flcn_dma_init()
[all …]
/linux/arch/powerpc/include/asm/
H A Ddcr-regs.h29 #define DCRN_CPR0_CONFIG_ADDR 0xc
30 #define DCRN_CPR0_CONFIG_DATA 0xd
33 #define DCRN_SDR0_CONFIG_ADDR 0xe
34 #define DCRN_SDR0_CONFIG_DATA 0xf
36 #define SDR0_PFC0 0x4100
37 #define SDR0_PFC1 0x4101
38 #define SDR0_PFC1_EPS 0x1c00000
40 #define SDR0_PFC1_RMII 0x02000000
41 #define SDR0_MFR 0x4300
42 #define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
[all …]

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