1*384740dcSRalf Baechle /* 2*384740dcSRalf Baechle * include/asm-mips/txx9tmr.h 3*384740dcSRalf Baechle * TX39/TX49 timer controller definitions. 4*384740dcSRalf Baechle * 5*384740dcSRalf Baechle * This file is subject to the terms and conditions of the GNU General Public 6*384740dcSRalf Baechle * License. See the file "COPYING" in the main directory of this archive 7*384740dcSRalf Baechle * for more details. 8*384740dcSRalf Baechle */ 9*384740dcSRalf Baechle #ifndef __ASM_TXX9TMR_H 10*384740dcSRalf Baechle #define __ASM_TXX9TMR_H 11*384740dcSRalf Baechle 12*384740dcSRalf Baechle #include <linux/types.h> 13*384740dcSRalf Baechle 14*384740dcSRalf Baechle struct txx9_tmr_reg { 15*384740dcSRalf Baechle u32 tcr; 16*384740dcSRalf Baechle u32 tisr; 17*384740dcSRalf Baechle u32 cpra; 18*384740dcSRalf Baechle u32 cprb; 19*384740dcSRalf Baechle u32 itmr; 20*384740dcSRalf Baechle u32 unused0[3]; 21*384740dcSRalf Baechle u32 ccdr; 22*384740dcSRalf Baechle u32 unused1[3]; 23*384740dcSRalf Baechle u32 pgmr; 24*384740dcSRalf Baechle u32 unused2[3]; 25*384740dcSRalf Baechle u32 wtmr; 26*384740dcSRalf Baechle u32 unused3[43]; 27*384740dcSRalf Baechle u32 trr; 28*384740dcSRalf Baechle }; 29*384740dcSRalf Baechle 30*384740dcSRalf Baechle /* TMTCR : Timer Control */ 31*384740dcSRalf Baechle #define TXx9_TMTCR_TCE 0x00000080 32*384740dcSRalf Baechle #define TXx9_TMTCR_CCDE 0x00000040 33*384740dcSRalf Baechle #define TXx9_TMTCR_CRE 0x00000020 34*384740dcSRalf Baechle #define TXx9_TMTCR_ECES 0x00000008 35*384740dcSRalf Baechle #define TXx9_TMTCR_CCS 0x00000004 36*384740dcSRalf Baechle #define TXx9_TMTCR_TMODE_MASK 0x00000003 37*384740dcSRalf Baechle #define TXx9_TMTCR_TMODE_ITVL 0x00000000 38*384740dcSRalf Baechle #define TXx9_TMTCR_TMODE_PGEN 0x00000001 39*384740dcSRalf Baechle #define TXx9_TMTCR_TMODE_WDOG 0x00000002 40*384740dcSRalf Baechle 41*384740dcSRalf Baechle /* TMTISR : Timer Int. Status */ 42*384740dcSRalf Baechle #define TXx9_TMTISR_TPIBS 0x00000004 43*384740dcSRalf Baechle #define TXx9_TMTISR_TPIAS 0x00000002 44*384740dcSRalf Baechle #define TXx9_TMTISR_TIIS 0x00000001 45*384740dcSRalf Baechle 46*384740dcSRalf Baechle /* TMITMR : Interval Timer Mode */ 47*384740dcSRalf Baechle #define TXx9_TMITMR_TIIE 0x00008000 48*384740dcSRalf Baechle #define TXx9_TMITMR_TZCE 0x00000001 49*384740dcSRalf Baechle 50*384740dcSRalf Baechle /* TMWTMR : Watchdog Timer Mode */ 51*384740dcSRalf Baechle #define TXx9_TMWTMR_TWIE 0x00008000 52*384740dcSRalf Baechle #define TXx9_TMWTMR_WDIS 0x00000080 53*384740dcSRalf Baechle #define TXx9_TMWTMR_TWC 0x00000001 54*384740dcSRalf Baechle 55*384740dcSRalf Baechle void txx9_clocksource_init(unsigned long baseaddr, 56*384740dcSRalf Baechle unsigned int imbusclk); 57*384740dcSRalf Baechle void txx9_clockevent_init(unsigned long baseaddr, int irq, 58*384740dcSRalf Baechle unsigned int imbusclk); 59*384740dcSRalf Baechle void txx9_tmr_init(unsigned long baseaddr); 60*384740dcSRalf Baechle 61*384740dcSRalf Baechle #define TXX9_TIMER_BITS 32 62*384740dcSRalf Baechle 63*384740dcSRalf Baechle #endif /* __ASM_TXX9TMR_H */ 64