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/linux/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI (1 << 0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/linux/arch/powerpc/platforms/83xx/
H A Dmpc83xx.h8 #define MPC83XX_SCCR_OFFS 0xA08
9 #define MPC83XX_SCCR_USB_MASK 0x00f00000
10 #define MPC83XX_SCCR_USB_MPHCM_11 0x00c00000
11 #define MPC83XX_SCCR_USB_MPHCM_01 0x00400000
12 #define MPC83XX_SCCR_USB_MPHCM_10 0x00800000
13 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000
14 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000
15 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000
16 #define MPC8315_SCCR_USB_MASK 0x00c00000
17 #define MPC8315_SCCR_USB_DRCM_11 0x00c00000
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml20 Register (IPBRR0) at offset 0x0BF8.
24 0x01900102 T1040
82 reg = <0xf0000 0x1000>;
83 interrupts = <18 2 0 0>;
84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
85 fsl,tmu-calibration = <0x00000000 0x00000025>,
86 <0x00000001 0x00000028>,
87 <0x00000002 0x0000002d>,
88 <0x00000003 0x00000031>,
89 <0x00000004 0x00000036>,
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dclc57d.h27 #define NVC57D_SET_CONTEXT_DMA_NOTIFIER (0x00000208)
28 #define NVC57D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
30 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0…
31 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0
32 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
33 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
35 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
36 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
38 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
39 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
[all …]
H A Dclc37d.h27 #define NV_DISP_NOTIFIER 0x00000000
28 #define NV_DISP_NOTIFIER_SIZEOF 0x00000010
29 #define NV_DISP_NOTIFIER__0 0x00000000
30 #define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0
33 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000
34 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001
39 #define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000
40 #define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001
41 #define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002
42 #define NV_DISP_NOTIFIER__1 0x00000001
[all …]
H A Dcl507d.h27 #define NV_DISP_CORE_NOTIFIER_1 0x00000000
28 #define NV_DISP_CORE_NOTIFIER_1_SIZEOF 0x00000054
29 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0 0x00000000
30 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE 0:0
31 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE 0x00000000
32 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001
35 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1 0x00000001
36 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE 0:0
37 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE 0x00000000
38 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE 0x00000001
[all …]
/linux/drivers/crypto/amcc/
H A Dcrypto4xx_reg_def.h15 #define CRYPTO4XX_DESCRIPTOR 0x00000000
16 #define CRYPTO4XX_CTRL_STAT 0x00000000
17 #define CRYPTO4XX_SOURCE 0x00000004
18 #define CRYPTO4XX_DEST 0x00000008
19 #define CRYPTO4XX_SA 0x0000000C
20 #define CRYPTO4XX_SA_LENGTH 0x00000010
21 #define CRYPTO4XX_LENGTH 0x00000014
23 #define CRYPTO4XX_PE_DMA_CFG 0x00000040
24 #define CRYPTO4XX_PE_DMA_STAT 0x00000044
25 #define CRYPTO4XX_PDR_BASE 0x00000048
[all …]
/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A D8192c.c21 .reg_0e00 = 0x07090c0c,
22 .reg_0e04 = 0x01020405,
23 .reg_0e08 = 0x00000000,
24 .reg_086c = 0x00000000,
26 .reg_0e10 = 0x0b0c0c0e,
27 .reg_0e14 = 0x01030506,
28 .reg_0e18 = 0x0b0c0d0e,
29 .reg_0e1c = 0x01030509,
31 .reg_0830 = 0x07090c0c,
32 .reg_0834 = 0x01020405,
[all …]
/linux/drivers/net/ethernet/toshiba/
H A Dspider_net.h56 #define SPIDER_NET_GHIINT0STS 0x00000000
57 #define SPIDER_NET_GHIINT1STS 0x00000004
58 #define SPIDER_NET_GHIINT2STS 0x00000008
59 #define SPIDER_NET_GHIINT0MSK 0x00000010
60 #define SPIDER_NET_GHIINT1MSK 0x00000014
61 #define SPIDER_NET_GHIINT2MSK 0x00000018
63 #define SPIDER_NET_GRESUMINTNUM 0x00000020
64 #define SPIDER_NET_GREINTNUM 0x00000024
66 #define SPIDER_NET_GFFRMNUM 0x00000028
67 #define SPIDER_NET_GFAFRMNUM 0x0000002c
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852a_table.c10 {0xF0FF0001, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03500FF, 0x00000002},
13 {0xF03200FF, 0x00000003},
14 {0xF03400FF, 0x00000004},
15 {0xF03600FF, 0x00000005},
16 {0x704, 0x601E0100},
17 {0x714, 0x00000000},
18 {0x718, 0x13332333},
19 {0x714, 0x00010000},
[all …]
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_reg.h13 #define REG_DP_HW_VERSION (0x00000000)
15 #define REG_DP_SW_RESET (0x00000010)
16 #define DP_SW_RESET (0x00000001)
18 #define REG_DP_PHY_CTRL (0x00000014)
19 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
20 #define DP_PHY_CTRL_SW_RESET (0x00000004)
22 #define REG_DP_CLK_CTRL (0x00000018)
23 #define REG_DP_CLK_ACTIVE (0x0000001C)
24 #define REG_DP_INTR_STATUS (0x00000020)
25 #define REG_DP_INTR_STATUS2 (0x00000024)
[all …]
/linux/drivers/gpu/drm/mcde/
H A Dmcde_dsi_regs.h5 #define DSI_MCTL_INTEGRATION_MODE 0x00000000
7 #define DSI_MCTL_MAIN_DATA_CTL 0x00000004
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
25 #define DSI_MCTL_MAIN_PHY_CTL 0x00000008
26 #define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN BIT(0)
33 #define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_MASK 0x000003C0
36 #define DSI_MCTL_PLL_CTL 0x0000000C
37 #define DSI_MCTL_LANE_STS 0x00000010
39 #define DSI_MCTL_DPHY_TIMEOUT 0x00000014
40 #define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT 0
[all …]
/linux/drivers/net/wireless/ath/ath12k/
H A Dhw.c18 static const guid_t wcn7850_uuid = GUID_INIT(0xf634f534, 0x6147, 0x11ec,
19 0x90, 0xd6, 0x02, 0x42,
20 0xac, 0x12, 0x00, 0x03);
36 return 0; in ath12k_hw_mac_id_to_srng_id_qcn9274()
55 return 0; in ath12k_hw_mac_id_to_pdev_id_wcn7850()
71 if (ring_num == 0 || ring_num == 2 || ring_num == 4) in ath12k_dp_srng_is_comp_ring_wcn7850()
95 #define ATH12K_TX_RING_MASK_0 0x1
96 #define ATH12K_TX_RING_MASK_1 0x2
97 #define ATH12K_TX_RING_MASK_2 0x4
98 #define ATH12K_TX_RING_MASK_3 0x8
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
H A Dgt215.fuc3.h3 /* 0x0000: ctx_object */
4 0x00000000,
5 /* 0x0004: ctx_dma */
6 /* 0x0004: ctx_dma_query */
7 0x00000000,
8 /* 0x0008: ctx_dma_src */
9 0x00000000,
10 /* 0x000c: ctx_dma_dst */
11 0x00000000,
12 /* 0x0010: ctx_query_address_high */
[all …]
H A Dgf100.fuc3.h3 /* 0x0000: ctx_object */
4 0x00000000,
5 /* 0x0004: ctx_query_address_high */
6 0x00000000,
7 /* 0x0008: ctx_query_address_low */
8 0x00000000,
9 /* 0x000c: ctx_query_counter */
10 0x00000000,
11 /* 0x0010: ctx_src_address_high */
12 0x00000000,
[all …]
/linux/drivers/net/wireless/ath/ath6kl/
H A Dtarget.h26 #define AR6004_BOARD_EXT_DATA_SZ 0
28 #define RESET_CONTROL_ADDRESS 0x00004000
29 #define RESET_CONTROL_COLD_RST 0x00000100
30 #define RESET_CONTROL_MBOX_RST 0x00000004
32 #define CPU_CLOCK_STANDARD_S 0
33 #define CPU_CLOCK_STANDARD 0x00000003
34 #define CPU_CLOCK_ADDRESS 0x00000020
36 #define CLOCK_CONTROL_ADDRESS 0x00000028
38 #define CLOCK_CONTROL_LF_CLK32 0x00000004
40 #define SYSTEM_SLEEP_ADDRESS 0x000000c4
[all …]
/linux/arch/m68k/include/asm/
H A Dm528xsim.h24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
33 #define MCFINTC_IRLR 0x18 /* */
34 #define MCFINTC_IACKL 0x19 /* */
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Dac5-98dx25xx.dtsi21 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0 0x0>;
45 reg = <0x0 0x100>;
85 /* 16M internal register @ 0x7f00_0000 */
86 ranges = <0x0 0x0 0x7f000000 0x1000000>;
91 reg = <0x12000 0x100>;
101 reg = <0x12100 0x100>;
111 reg = <0x12200 0x100>;
121 reg = <0x12300 0x100>;
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Dsoc24_enum.h52 CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000,
53 CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001,
54 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002,
55 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003,
63 CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
64 CP_PERFMON_STATE_START_COUNTING = 0x00000001,
65 CP_PERFMON_STATE_STOP_COUNTING = 0x00000002,
66 CP_PERFMON_STATE_RESERVED_3 = 0x00000003,
67 CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
68 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
[all …]
H A Dnavi10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 GATCL1_TYPE_NORMAL = 0x00000000,
185 GATCL1_TYPE_SHOOTDOWN = 0x00000001,
186 GATCL1_TYPE_BYPASS = 0x00000002,
194 UTCL1_TYPE_NORMAL = 0x00000000,
195 UTCL1_TYPE_SHOOTDOWN = 0x00000001,
196 UTCL1_TYPE_BYPASS = 0x00000002,
204 UTCL1_XNACK_SUCCESS = 0x00000000,
205 UTCL1_XNACK_RETRY = 0x00000001,
206 UTCL1_XNACK_PRT = 0x00000002,
[all …]
H A Dsoc21_enum.h55 DSM_DATA_SEL_DISABLE = 0x00000000,
56 DSM_DATA_SEL_0 = 0x00000001,
57 DSM_DATA_SEL_1 = 0x00000002,
58 DSM_DATA_SEL_BOTH = 0x00000003,
66 DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
67 DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
68 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002,
69 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003,
77 DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
78 DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a.dtsi27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
42 reg = <0x1>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
51 reg = <0x2>;
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 reg = <0x3>;
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a.dtsi31 #size-cells = <0>;
36 reg = <0xf00>;
37 clocks = <&clockgen 1 0>;
44 reg = <0xf01>;
45 clocks = <&clockgen 1 0>;
50 memory@0 {
52 reg = <0x0 0x0 0x0 0x0>;
57 #clock-cells = <0>;
80 offset = <0xb0>;
81 mask = <0x02>;
[all …]
/linux/drivers/net/ipa/reg/
H A Dipa_reg-v3.1.c13 [COMP_CFG_ENABLE] = BIT(0),
21 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
24 [CLKON_RX] = BIT(0),
44 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
47 [ROUTE_DIS] = BIT(0),
57 REG_FIELDS(ROUTE, route, 0x00000048);
60 [MEM_SIZE] = GENMASK(15, 0),
64 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
67 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
72 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/
H A Dtable.c7 0x024, 0x0011800f,
8 0x028, 0x00ffdb83,
9 0x800, 0x80040002,
10 0x804, 0x00000003,
11 0x808, 0x0000fc00,
12 0x80c, 0x0000000a,
13 0x810, 0x10000330,
14 0x814, 0x020c3d10,
15 0x818, 0x02200385,
16 0x81c, 0x00000000,
[all …]

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