Lines Matching +full:0 +full:x00000054
15 #define CRYPTO4XX_DESCRIPTOR 0x00000000
16 #define CRYPTO4XX_CTRL_STAT 0x00000000
17 #define CRYPTO4XX_SOURCE 0x00000004
18 #define CRYPTO4XX_DEST 0x00000008
19 #define CRYPTO4XX_SA 0x0000000C
20 #define CRYPTO4XX_SA_LENGTH 0x00000010
21 #define CRYPTO4XX_LENGTH 0x00000014
23 #define CRYPTO4XX_PE_DMA_CFG 0x00000040
24 #define CRYPTO4XX_PE_DMA_STAT 0x00000044
25 #define CRYPTO4XX_PDR_BASE 0x00000048
26 #define CRYPTO4XX_RDR_BASE 0x0000004c
27 #define CRYPTO4XX_RING_SIZE 0x00000050
28 #define CRYPTO4XX_RING_CTRL 0x00000054
29 #define CRYPTO4XX_INT_RING_STAT 0x00000058
30 #define CRYPTO4XX_EXT_RING_STAT 0x0000005c
31 #define CRYPTO4XX_IO_THRESHOLD 0x00000060
32 #define CRYPTO4XX_GATH_RING_BASE 0x00000064
33 #define CRYPTO4XX_SCAT_RING_BASE 0x00000068
34 #define CRYPTO4XX_PART_RING_SIZE 0x0000006c
35 #define CRYPTO4XX_PART_RING_CFG 0x00000070
37 #define CRYPTO4XX_PDR_BASE_UADDR 0x00000080
38 #define CRYPTO4XX_RDR_BASE_UADDR 0x00000084
39 #define CRYPTO4XX_PKT_SRC_UADDR 0x00000088
40 #define CRYPTO4XX_PKT_DEST_UADDR 0x0000008c
41 #define CRYPTO4XX_SA_UADDR 0x00000090
42 #define CRYPTO4XX_GATH_RING_BASE_UADDR 0x000000A0
43 #define CRYPTO4XX_SCAT_RING_BASE_UADDR 0x000000A4
45 #define CRYPTO4XX_SEQ_RD 0x00000408
46 #define CRYPTO4XX_SEQ_MASK_RD 0x0000040C
48 #define CRYPTO4XX_SA_CMD_0 0x00010600
49 #define CRYPTO4XX_SA_CMD_1 0x00010604
51 #define CRYPTO4XX_STATE_PTR 0x000106dc
52 #define CRYPTO4XX_STATE_IV 0x00010700
53 #define CRYPTO4XX_STATE_HASH_BYTE_CNT_0 0x00010710
54 #define CRYPTO4XX_STATE_HASH_BYTE_CNT_1 0x00010714
56 #define CRYPTO4XX_STATE_IDIGEST_0 0x00010718
57 #define CRYPTO4XX_STATE_IDIGEST_1 0x0001071c
59 #define CRYPTO4XX_DATA_IN 0x00018000
60 #define CRYPTO4XX_DATA_OUT 0x0001c000
62 #define CRYPTO4XX_INT_UNMASK_STAT 0x000500a0
63 #define CRYPTO4XX_INT_MASK_STAT 0x000500a4
64 #define CRYPTO4XX_INT_CLR 0x000500a4
65 #define CRYPTO4XX_INT_EN 0x000500a8
67 #define CRYPTO4XX_INT_PKA 0x00000002
68 #define CRYPTO4XX_INT_PDR_DONE 0x00008000
69 #define CRYPTO4XX_INT_MA_WR_ERR 0x00020000
70 #define CRYPTO4XX_INT_MA_RD_ERR 0x00010000
71 #define CRYPTO4XX_INT_PE_ERR 0x00000200
72 #define CRYPTO4XX_INT_USER_DMA_ERR 0x00000040
73 #define CRYPTO4XX_INT_SLAVE_ERR 0x00000010
74 #define CRYPTO4XX_INT_MASTER_ERR 0x00000008
75 #define CRYPTO4XX_INT_ERROR 0x00030258
77 #define CRYPTO4XX_INT_CFG 0x000500ac
78 #define CRYPTO4XX_INT_DESCR_RD 0x000500b0
79 #define CRYPTO4XX_INT_DESCR_CNT 0x000500b4
80 #define CRYPTO4XX_INT_TIMEOUT_CNT 0x000500b8
82 #define CRYPTO4XX_DEVICE_CTRL 0x00060080
83 #define CRYPTO4XX_DEVICE_ID 0x00060084
84 #define CRYPTO4XX_DEVICE_INFO 0x00060088
85 #define CRYPTO4XX_DMA_USER_SRC 0x00060094
86 #define CRYPTO4XX_DMA_USER_DEST 0x00060098
87 #define CRYPTO4XX_DMA_USER_CMD 0x0006009C
89 #define CRYPTO4XX_DMA_CFG 0x000600d4
90 #define CRYPTO4XX_BYTE_ORDER_CFG 0x000600d8
91 #define CRYPTO4XX_ENDIAN_CFG 0x000600d8
93 #define CRYPTO4XX_PRNG_STAT 0x00070000
94 #define CRYPTO4XX_PRNG_STAT_BUSY 0x1
95 #define CRYPTO4XX_PRNG_CTRL 0x00070004
96 #define CRYPTO4XX_PRNG_SEED_L 0x00070008
97 #define CRYPTO4XX_PRNG_SEED_H 0x0007000c
99 #define CRYPTO4XX_PRNG_RES_0 0x00070020
100 #define CRYPTO4XX_PRNG_RES_1 0x00070024
101 #define CRYPTO4XX_PRNG_RES_2 0x00070028
102 #define CRYPTO4XX_PRNG_RES_3 0x0007002C
104 #define CRYPTO4XX_PRNG_LFSR_L 0x00070030
105 #define CRYPTO4XX_PRNG_LFSR_H 0x00070034
110 #define PPC4XX_PDR_POLL 0x3ff
114 #define PPC4XX_CTX_DONE_INT 0x2000
115 #define PPC4XX_PD_DONE_INT 0x8000
116 #define PPC4XX_TMO_ERR_INT 0x40000
117 #define PPC4XX_BYTE_ORDER 0x22222
118 #define PPC4XX_INTERRUPT_CLR 0x3ffff
119 #define PPC4XX_PRNG_CTRL_AUTO_EN 0x3
121 #define PPC4XX_TRNG_EN 0x00020000
123 #define PPC4XX_INT_TIMEOUT_CNT 0
124 #define PPC4XX_INT_TIMEOUT_CNT_REVB 0x3FF
140 #define CRYPTO4XX_DMA_CFG_OFFSET 0x40
164 #define CRYPTO4XX_PDR_BASE_OFFSET 0x48
165 #define CRYPTO4XX_RDR_BASE_OFFSET 0x4c
166 #define CRYPTO4XX_RING_SIZE_OFFSET 0x50
176 #define CRYPTO4XX_RING_CONTROL_OFFSET 0x54
188 #define CRYPTO4XX_IO_THRESHOLD_OFFSET 0x60
199 #define CRYPTO4XX_GATHER_RING_BASE_OFFSET 0x64
200 #define CRYPTO4XX_SCATTER_RING_BASE_OFFSET 0x68
210 #define MAX_BURST_SIZE_32 0
239 #define PD_PAD_CTL_32 0x10
240 #define PD_PAD_CTL_64 0x20
241 #define PD_PAD_CTL_128 0x40
242 #define PD_PAD_CTL_256 0x80
260 #define PD_CTL_HOST_READY BIT(0)