xref: /linux/drivers/net/wireless/realtek/rtl8xxxu/8192c.c (revision 621cde16e49b3ecf7d59a8106a20aaebfb4a59a9)
1028fa281SKalle Valo // SPDX-License-Identifier: GPL-2.0-only
2028fa281SKalle Valo /*
3028fa281SKalle Valo  * RTL8XXXU mac80211 USB driver - 8188c/8188r/8192c specific subdriver
4028fa281SKalle Valo  *
5028fa281SKalle Valo  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
6028fa281SKalle Valo  *
7028fa281SKalle Valo  * Portions, notably calibration code:
8028fa281SKalle Valo  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9028fa281SKalle Valo  *
10028fa281SKalle Valo  * This driver was written as a replacement for the vendor provided
11028fa281SKalle Valo  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
12028fa281SKalle Valo  * their programming interface, I have started adding support for
13028fa281SKalle Valo  * additional 8xxx chips like the 8192cu, 8188cus, etc.
14028fa281SKalle Valo  */
15028fa281SKalle Valo 
16028fa281SKalle Valo #include "regs.h"
17*949f6f3aSPing-Ke Shih #include "rtl8xxxu.h"
18028fa281SKalle Valo 
19028fa281SKalle Valo #ifdef CONFIG_RTL8XXXU_UNTESTED
20028fa281SKalle Valo static struct rtl8xxxu_power_base rtl8192c_power_base = {
21028fa281SKalle Valo 	.reg_0e00 = 0x07090c0c,
22028fa281SKalle Valo 	.reg_0e04 = 0x01020405,
23028fa281SKalle Valo 	.reg_0e08 = 0x00000000,
24028fa281SKalle Valo 	.reg_086c = 0x00000000,
25028fa281SKalle Valo 
26028fa281SKalle Valo 	.reg_0e10 = 0x0b0c0c0e,
27028fa281SKalle Valo 	.reg_0e14 = 0x01030506,
28028fa281SKalle Valo 	.reg_0e18 = 0x0b0c0d0e,
29028fa281SKalle Valo 	.reg_0e1c = 0x01030509,
30028fa281SKalle Valo 
31028fa281SKalle Valo 	.reg_0830 = 0x07090c0c,
32028fa281SKalle Valo 	.reg_0834 = 0x01020405,
33028fa281SKalle Valo 	.reg_0838 = 0x00000000,
34028fa281SKalle Valo 	.reg_086c_2 = 0x00000000,
35028fa281SKalle Valo 
36028fa281SKalle Valo 	.reg_083c = 0x0b0c0d0e,
37028fa281SKalle Valo 	.reg_0848 = 0x01030509,
38028fa281SKalle Valo 	.reg_084c = 0x0b0c0d0e,
39028fa281SKalle Valo 	.reg_0868 = 0x01030509,
40028fa281SKalle Valo };
41028fa281SKalle Valo 
42028fa281SKalle Valo static struct rtl8xxxu_power_base rtl8188r_power_base = {
43028fa281SKalle Valo 	.reg_0e00 = 0x06080808,
44028fa281SKalle Valo 	.reg_0e04 = 0x00040406,
45028fa281SKalle Valo 	.reg_0e08 = 0x00000000,
46028fa281SKalle Valo 	.reg_086c = 0x00000000,
47028fa281SKalle Valo 
48028fa281SKalle Valo 	.reg_0e10 = 0x04060608,
49028fa281SKalle Valo 	.reg_0e14 = 0x00020204,
50028fa281SKalle Valo 	.reg_0e18 = 0x04060608,
51028fa281SKalle Valo 	.reg_0e1c = 0x00020204,
52028fa281SKalle Valo 
53028fa281SKalle Valo 	.reg_0830 = 0x06080808,
54028fa281SKalle Valo 	.reg_0834 = 0x00040406,
55028fa281SKalle Valo 	.reg_0838 = 0x00000000,
56028fa281SKalle Valo 	.reg_086c_2 = 0x00000000,
57028fa281SKalle Valo 
58028fa281SKalle Valo 	.reg_083c = 0x04060608,
59028fa281SKalle Valo 	.reg_0848 = 0x00020204,
60028fa281SKalle Valo 	.reg_084c = 0x04060608,
61028fa281SKalle Valo 	.reg_0868 = 0x00020204,
62028fa281SKalle Valo };
63028fa281SKalle Valo 
64028fa281SKalle Valo static const struct rtl8xxxu_reg8val rtl8192cu_mac_init_table[] = {
65028fa281SKalle Valo 	{0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
66028fa281SKalle Valo 	{0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
67028fa281SKalle Valo 	{0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
68028fa281SKalle Valo 	{0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
69028fa281SKalle Valo 	{0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
70028fa281SKalle Valo 	{0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
71028fa281SKalle Valo 	{0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
72028fa281SKalle Valo 	{0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
73028fa281SKalle Valo 	{0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
74028fa281SKalle Valo 	{0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
75028fa281SKalle Valo 	{0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
76028fa281SKalle Valo 	{0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
77028fa281SKalle Valo 	{0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
78028fa281SKalle Valo 	{0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
79028fa281SKalle Valo 	{0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
80028fa281SKalle Valo 	{0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
81028fa281SKalle Valo 	{0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
82028fa281SKalle Valo 	{0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
83028fa281SKalle Valo 	{0x652, 0x20}, {0x652, 0x20}, {0x63c, 0x08}, {0x63d, 0x08},
84028fa281SKalle Valo 	{0x63e, 0x0c}, {0x63f, 0x0c}, {0x66e, 0x05}, {0x700, 0x21},
85028fa281SKalle Valo 	{0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21},
86028fa281SKalle Valo 	{0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87},
87028fa281SKalle Valo 	{0xffff, 0xff},
88028fa281SKalle Valo };
89028fa281SKalle Valo 
90028fa281SKalle Valo static const struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
91028fa281SKalle Valo 	{0x00, 0x00030159}, {0x01, 0x00031284},
92028fa281SKalle Valo 	{0x02, 0x00098000}, {0x03, 0x00018c63},
93028fa281SKalle Valo 	{0x04, 0x000210e7}, {0x09, 0x0002044f},
94028fa281SKalle Valo 	{0x0a, 0x0001adb1}, {0x0b, 0x00054867},
95028fa281SKalle Valo 	{0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
96028fa281SKalle Valo 	{0x0e, 0x00039ce7}, {0x0f, 0x00000451},
97028fa281SKalle Valo 	{0x19, 0x00000000}, {0x1a, 0x00010255},
98028fa281SKalle Valo 	{0x1b, 0x00060a00}, {0x1c, 0x000fc378},
99028fa281SKalle Valo 	{0x1d, 0x000a1250}, {0x1e, 0x0004445f},
100028fa281SKalle Valo 	{0x1f, 0x00080001}, {0x20, 0x0000b614},
101028fa281SKalle Valo 	{0x21, 0x0006c000}, {0x22, 0x00000000},
102028fa281SKalle Valo 	{0x23, 0x00001558}, {0x24, 0x00000060},
103028fa281SKalle Valo 	{0x25, 0x00000483}, {0x26, 0x0004f000},
104028fa281SKalle Valo 	{0x27, 0x000ec7d9}, {0x28, 0x000577c0},
105028fa281SKalle Valo 	{0x29, 0x00004783}, {0x2a, 0x00000001},
106028fa281SKalle Valo 	{0x2b, 0x00021334}, {0x2a, 0x00000000},
107028fa281SKalle Valo 	{0x2b, 0x00000054}, {0x2a, 0x00000001},
108028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x00053333},
109028fa281SKalle Valo 	{0x2c, 0x0000000c}, {0x2a, 0x00000002},
110028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x0005b333},
111028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000003},
112028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x00063333},
113028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000004},
114028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x0006b333},
115028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000005},
116028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x00073333},
117028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000006},
118028fa281SKalle Valo 	{0x2b, 0x00000709}, {0x2b, 0x0005b333},
119028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000007},
120028fa281SKalle Valo 	{0x2b, 0x00000709}, {0x2b, 0x00063333},
121028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000008},
122028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x0004b333},
123028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000009},
124028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x00053333},
125028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000a},
126028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x0005b333},
127028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000b},
128028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x00063333},
129028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000c},
130028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x0006b333},
131028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000d},
132028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x00073333},
133028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000e},
134028fa281SKalle Valo 	{0x2b, 0x0000050b}, {0x2b, 0x00066666},
135028fa281SKalle Valo 	{0x2c, 0x0000001a}, {0x2a, 0x000e0000},
136028fa281SKalle Valo 	{0x10, 0x0004000f}, {0x11, 0x000e31fc},
137028fa281SKalle Valo 	{0x10, 0x0006000f}, {0x11, 0x000ff9f8},
138028fa281SKalle Valo 	{0x10, 0x0002000f}, {0x11, 0x000203f9},
139028fa281SKalle Valo 	{0x10, 0x0003000f}, {0x11, 0x000ff500},
140028fa281SKalle Valo 	{0x10, 0x00000000}, {0x11, 0x00000000},
141028fa281SKalle Valo 	{0x10, 0x0008000f}, {0x11, 0x0003f100},
142028fa281SKalle Valo 	{0x10, 0x0009000f}, {0x11, 0x00023100},
143028fa281SKalle Valo 	{0x12, 0x00032000}, {0x12, 0x00071000},
144028fa281SKalle Valo 	{0x12, 0x000b0000}, {0x12, 0x000fc000},
145028fa281SKalle Valo 	{0x13, 0x000287b3}, {0x13, 0x000244b7},
146028fa281SKalle Valo 	{0x13, 0x000204ab}, {0x13, 0x0001c49f},
147028fa281SKalle Valo 	{0x13, 0x00018493}, {0x13, 0x0001429b},
148028fa281SKalle Valo 	{0x13, 0x00010299}, {0x13, 0x0000c29c},
149028fa281SKalle Valo 	{0x13, 0x000081a0}, {0x13, 0x000040ac},
150028fa281SKalle Valo 	{0x13, 0x00000020}, {0x14, 0x0001944c},
151028fa281SKalle Valo 	{0x14, 0x00059444}, {0x14, 0x0009944c},
152028fa281SKalle Valo 	{0x14, 0x000d9444}, {0x15, 0x0000f424},
153028fa281SKalle Valo 	{0x15, 0x0004f424}, {0x15, 0x0008f424},
154028fa281SKalle Valo 	{0x15, 0x000cf424}, {0x16, 0x000e0330},
155028fa281SKalle Valo 	{0x16, 0x000a0330}, {0x16, 0x00060330},
156028fa281SKalle Valo 	{0x16, 0x00020330}, {0x00, 0x00010159},
157028fa281SKalle Valo 	{0x18, 0x0000f401}, {0xfe, 0x00000000},
158028fa281SKalle Valo 	{0xfe, 0x00000000}, {0x1f, 0x00080003},
159028fa281SKalle Valo 	{0xfe, 0x00000000}, {0xfe, 0x00000000},
160028fa281SKalle Valo 	{0x1e, 0x00044457}, {0x1f, 0x00080000},
161028fa281SKalle Valo 	{0x00, 0x00030159},
162028fa281SKalle Valo 	{0xff, 0xffffffff}
163028fa281SKalle Valo };
164028fa281SKalle Valo 
165028fa281SKalle Valo static const struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
166028fa281SKalle Valo 	{0x00, 0x00030159}, {0x01, 0x00031284},
167028fa281SKalle Valo 	{0x02, 0x00098000}, {0x03, 0x00018c63},
168028fa281SKalle Valo 	{0x04, 0x000210e7}, {0x09, 0x0002044f},
169028fa281SKalle Valo 	{0x0a, 0x0001adb1}, {0x0b, 0x00054867},
170028fa281SKalle Valo 	{0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
171028fa281SKalle Valo 	{0x0e, 0x00039ce7}, {0x0f, 0x00000451},
172028fa281SKalle Valo 	{0x12, 0x00032000}, {0x12, 0x00071000},
173028fa281SKalle Valo 	{0x12, 0x000b0000}, {0x12, 0x000fc000},
174028fa281SKalle Valo 	{0x13, 0x000287af}, {0x13, 0x000244b7},
175028fa281SKalle Valo 	{0x13, 0x000204ab}, {0x13, 0x0001c49f},
176028fa281SKalle Valo 	{0x13, 0x00018493}, {0x13, 0x00014297},
177028fa281SKalle Valo 	{0x13, 0x00010295}, {0x13, 0x0000c298},
178028fa281SKalle Valo 	{0x13, 0x0000819c}, {0x13, 0x000040a8},
179028fa281SKalle Valo 	{0x13, 0x0000001c}, {0x14, 0x0001944c},
180028fa281SKalle Valo 	{0x14, 0x00059444}, {0x14, 0x0009944c},
181028fa281SKalle Valo 	{0x14, 0x000d9444}, {0x15, 0x0000f424},
182028fa281SKalle Valo 	{0x15, 0x0004f424}, {0x15, 0x0008f424},
183028fa281SKalle Valo 	{0x15, 0x000cf424}, {0x16, 0x000e0330},
184028fa281SKalle Valo 	{0x16, 0x000a0330}, {0x16, 0x00060330},
185028fa281SKalle Valo 	{0x16, 0x00020330},
186028fa281SKalle Valo 	{0xff, 0xffffffff}
187028fa281SKalle Valo };
188028fa281SKalle Valo 
189028fa281SKalle Valo static const struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
190028fa281SKalle Valo 	{0x00, 0x00030159}, {0x01, 0x00031284},
191028fa281SKalle Valo 	{0x02, 0x00098000}, {0x03, 0x00018c63},
192028fa281SKalle Valo 	{0x04, 0x000210e7}, {0x09, 0x0002044f},
193028fa281SKalle Valo 	{0x0a, 0x0001adb1}, {0x0b, 0x00054867},
194028fa281SKalle Valo 	{0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
195028fa281SKalle Valo 	{0x0e, 0x00039ce7}, {0x0f, 0x00000451},
196028fa281SKalle Valo 	{0x19, 0x00000000}, {0x1a, 0x00010255},
197028fa281SKalle Valo 	{0x1b, 0x00060a00}, {0x1c, 0x000fc378},
198028fa281SKalle Valo 	{0x1d, 0x000a1250}, {0x1e, 0x0004445f},
199028fa281SKalle Valo 	{0x1f, 0x00080001}, {0x20, 0x0000b614},
200028fa281SKalle Valo 	{0x21, 0x0006c000}, {0x22, 0x00000000},
201028fa281SKalle Valo 	{0x23, 0x00001558}, {0x24, 0x00000060},
202028fa281SKalle Valo 	{0x25, 0x00000483}, {0x26, 0x0004f000},
203028fa281SKalle Valo 	{0x27, 0x000ec7d9}, {0x28, 0x000577c0},
204028fa281SKalle Valo 	{0x29, 0x00004783}, {0x2a, 0x00000001},
205028fa281SKalle Valo 	{0x2b, 0x00021334}, {0x2a, 0x00000000},
206028fa281SKalle Valo 	{0x2b, 0x00000054}, {0x2a, 0x00000001},
207028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x00053333},
208028fa281SKalle Valo 	{0x2c, 0x0000000c}, {0x2a, 0x00000002},
209028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x0005b333},
210028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000003},
211028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x00063333},
212028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000004},
213028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x0006b333},
214028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000005},
215028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x00073333},
216028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000006},
217028fa281SKalle Valo 	{0x2b, 0x00000709}, {0x2b, 0x0005b333},
218028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000007},
219028fa281SKalle Valo 	{0x2b, 0x00000709}, {0x2b, 0x00063333},
220028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000008},
221028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x0004b333},
222028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000009},
223028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x00053333},
224028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000a},
225028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x0005b333},
226028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000b},
227028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x00063333},
228028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000c},
229028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x0006b333},
230028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000d},
231028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x00073333},
232028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000e},
233028fa281SKalle Valo 	{0x2b, 0x0000050b}, {0x2b, 0x00066666},
234028fa281SKalle Valo 	{0x2c, 0x0000001a}, {0x2a, 0x000e0000},
235028fa281SKalle Valo 	{0x10, 0x0004000f}, {0x11, 0x000e31fc},
236028fa281SKalle Valo 	{0x10, 0x0006000f}, {0x11, 0x000ff9f8},
237028fa281SKalle Valo 	{0x10, 0x0002000f}, {0x11, 0x000203f9},
238028fa281SKalle Valo 	{0x10, 0x0003000f}, {0x11, 0x000ff500},
239028fa281SKalle Valo 	{0x10, 0x00000000}, {0x11, 0x00000000},
240028fa281SKalle Valo 	{0x10, 0x0008000f}, {0x11, 0x0003f100},
241028fa281SKalle Valo 	{0x10, 0x0009000f}, {0x11, 0x00023100},
242028fa281SKalle Valo 	{0x12, 0x00032000}, {0x12, 0x00071000},
243028fa281SKalle Valo 	{0x12, 0x000b0000}, {0x12, 0x000fc000},
244028fa281SKalle Valo 	{0x13, 0x000287b3}, {0x13, 0x000244b7},
245028fa281SKalle Valo 	{0x13, 0x000204ab}, {0x13, 0x0001c49f},
246028fa281SKalle Valo 	{0x13, 0x00018493}, {0x13, 0x0001429b},
247028fa281SKalle Valo 	{0x13, 0x00010299}, {0x13, 0x0000c29c},
248028fa281SKalle Valo 	{0x13, 0x000081a0}, {0x13, 0x000040ac},
249028fa281SKalle Valo 	{0x13, 0x00000020}, {0x14, 0x0001944c},
250028fa281SKalle Valo 	{0x14, 0x00059444}, {0x14, 0x0009944c},
251028fa281SKalle Valo 	{0x14, 0x000d9444}, {0x15, 0x0000f405},
252028fa281SKalle Valo 	{0x15, 0x0004f405}, {0x15, 0x0008f405},
253028fa281SKalle Valo 	{0x15, 0x000cf405}, {0x16, 0x000e0330},
254028fa281SKalle Valo 	{0x16, 0x000a0330}, {0x16, 0x00060330},
255028fa281SKalle Valo 	{0x16, 0x00020330}, {0x00, 0x00010159},
256028fa281SKalle Valo 	{0x18, 0x0000f401}, {0xfe, 0x00000000},
257028fa281SKalle Valo 	{0xfe, 0x00000000}, {0x1f, 0x00080003},
258028fa281SKalle Valo 	{0xfe, 0x00000000}, {0xfe, 0x00000000},
259028fa281SKalle Valo 	{0x1e, 0x00044457}, {0x1f, 0x00080000},
260028fa281SKalle Valo 	{0x00, 0x00030159},
261028fa281SKalle Valo 	{0xff, 0xffffffff}
262028fa281SKalle Valo };
263028fa281SKalle Valo 
264028fa281SKalle Valo static const struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
265028fa281SKalle Valo 	{0x00, 0x00030159}, {0x01, 0x00031284},
266028fa281SKalle Valo 	{0x02, 0x00098000}, {0x03, 0x00018c63},
267028fa281SKalle Valo 	{0x04, 0x000210e7}, {0x09, 0x0002044f},
268028fa281SKalle Valo 	{0x0a, 0x0001adb0}, {0x0b, 0x00054867},
269028fa281SKalle Valo 	{0x0c, 0x0008992e}, {0x0d, 0x0000e529},
270028fa281SKalle Valo 	{0x0e, 0x00039ce7}, {0x0f, 0x00000451},
271028fa281SKalle Valo 	{0x19, 0x00000000}, {0x1a, 0x00000255},
272028fa281SKalle Valo 	{0x1b, 0x00060a00}, {0x1c, 0x000fc378},
273028fa281SKalle Valo 	{0x1d, 0x000a1250}, {0x1e, 0x0004445f},
274028fa281SKalle Valo 	{0x1f, 0x00080001}, {0x20, 0x0000b614},
275028fa281SKalle Valo 	{0x21, 0x0006c000}, {0x22, 0x0000083c},
276028fa281SKalle Valo 	{0x23, 0x00001558}, {0x24, 0x00000060},
277028fa281SKalle Valo 	{0x25, 0x00000483}, {0x26, 0x0004f000},
278028fa281SKalle Valo 	{0x27, 0x000ec7d9}, {0x28, 0x000977c0},
279028fa281SKalle Valo 	{0x29, 0x00004783}, {0x2a, 0x00000001},
280028fa281SKalle Valo 	{0x2b, 0x00021334}, {0x2a, 0x00000000},
281028fa281SKalle Valo 	{0x2b, 0x00000054}, {0x2a, 0x00000001},
282028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x00053333},
283028fa281SKalle Valo 	{0x2c, 0x0000000c}, {0x2a, 0x00000002},
284028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x0005b333},
285028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000003},
286028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x00063333},
287028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000004},
288028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x0006b333},
289028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000005},
290028fa281SKalle Valo 	{0x2b, 0x00000808}, {0x2b, 0x00073333},
291028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000006},
292028fa281SKalle Valo 	{0x2b, 0x00000709}, {0x2b, 0x0005b333},
293028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000007},
294028fa281SKalle Valo 	{0x2b, 0x00000709}, {0x2b, 0x00063333},
295028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000008},
296028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x0004b333},
297028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x00000009},
298028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x00053333},
299028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000a},
300028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x0005b333},
301028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000b},
302028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x00063333},
303028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000c},
304028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x0006b333},
305028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000d},
306028fa281SKalle Valo 	{0x2b, 0x0000060a}, {0x2b, 0x00073333},
307028fa281SKalle Valo 	{0x2c, 0x0000000d}, {0x2a, 0x0000000e},
308028fa281SKalle Valo 	{0x2b, 0x0000050b}, {0x2b, 0x00066666},
309028fa281SKalle Valo 	{0x2c, 0x0000001a}, {0x2a, 0x000e0000},
310028fa281SKalle Valo 	{0x10, 0x0004000f}, {0x11, 0x000e31fc},
311028fa281SKalle Valo 	{0x10, 0x0006000f}, {0x11, 0x000ff9f8},
312028fa281SKalle Valo 	{0x10, 0x0002000f}, {0x11, 0x000203f9},
313028fa281SKalle Valo 	{0x10, 0x0003000f}, {0x11, 0x000ff500},
314028fa281SKalle Valo 	{0x10, 0x00000000}, {0x11, 0x00000000},
315028fa281SKalle Valo 	{0x10, 0x0008000f}, {0x11, 0x0003f100},
316028fa281SKalle Valo 	{0x10, 0x0009000f}, {0x11, 0x00023100},
317028fa281SKalle Valo 	{0x12, 0x000d8000}, {0x12, 0x00090000},
318028fa281SKalle Valo 	{0x12, 0x00051000}, {0x12, 0x00012000},
319028fa281SKalle Valo 	{0x13, 0x00028fb4}, {0x13, 0x00024fa8},
320028fa281SKalle Valo 	{0x13, 0x000207a4}, {0x13, 0x0001c3b0},
321028fa281SKalle Valo 	{0x13, 0x000183a4}, {0x13, 0x00014398},
322028fa281SKalle Valo 	{0x13, 0x000101a4}, {0x13, 0x0000c198},
323028fa281SKalle Valo 	{0x13, 0x000080a4}, {0x13, 0x00004098},
324028fa281SKalle Valo 	{0x13, 0x00000000}, {0x14, 0x0001944c},
325028fa281SKalle Valo 	{0x14, 0x00059444}, {0x14, 0x0009944c},
326028fa281SKalle Valo 	{0x14, 0x000d9444}, {0x15, 0x0000f405},
327028fa281SKalle Valo 	{0x15, 0x0004f405}, {0x15, 0x0008f405},
328028fa281SKalle Valo 	{0x15, 0x000cf405}, {0x16, 0x000e0330},
329028fa281SKalle Valo 	{0x16, 0x000a0330}, {0x16, 0x00060330},
330028fa281SKalle Valo 	{0x16, 0x00020330}, {0x00, 0x00010159},
331028fa281SKalle Valo 	{0x18, 0x0000f401}, {0xfe, 0x00000000},
332028fa281SKalle Valo 	{0xfe, 0x00000000}, {0x1f, 0x00080003},
333028fa281SKalle Valo 	{0xfe, 0x00000000}, {0xfe, 0x00000000},
334028fa281SKalle Valo 	{0x1e, 0x00044457}, {0x1f, 0x00080000},
335028fa281SKalle Valo 	{0x00, 0x00030159},
336028fa281SKalle Valo 	{0xff, 0xffffffff}
337028fa281SKalle Valo };
338028fa281SKalle Valo 
rtl8192cu_identify_chip(struct rtl8xxxu_priv * priv)339028fa281SKalle Valo static int rtl8192cu_identify_chip(struct rtl8xxxu_priv *priv)
340028fa281SKalle Valo {
341028fa281SKalle Valo 	struct device *dev = &priv->udev->dev;
342028fa281SKalle Valo 	u32 val32, bonding, sys_cfg, vendor;
343028fa281SKalle Valo 	int ret = 0;
344028fa281SKalle Valo 
345028fa281SKalle Valo 	sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);
346028fa281SKalle Valo 	priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK);
347028fa281SKalle Valo 	if (sys_cfg & SYS_CFG_TRP_VAUX_EN) {
348028fa281SKalle Valo 		dev_info(dev, "Unsupported test chip\n");
349028fa281SKalle Valo 		ret = -ENOTSUPP;
350028fa281SKalle Valo 		goto out;
351028fa281SKalle Valo 	}
352028fa281SKalle Valo 
353028fa281SKalle Valo 	if (sys_cfg & SYS_CFG_TYPE_ID) {
354028fa281SKalle Valo 		bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
355028fa281SKalle Valo 		bonding &= HPON_FSM_BONDING_MASK;
356028fa281SKalle Valo 		if (bonding == HPON_FSM_BONDING_1T2R) {
357028fa281SKalle Valo 			strscpy(priv->chip_name, "8191CU", sizeof(priv->chip_name));
358028fa281SKalle Valo 			priv->tx_paths = 1;
359028fa281SKalle Valo 			priv->usb_interrupts = 1;
360028fa281SKalle Valo 			priv->rtl_chip = RTL8191C;
361028fa281SKalle Valo 		} else {
362028fa281SKalle Valo 			strscpy(priv->chip_name, "8192CU", sizeof(priv->chip_name));
363028fa281SKalle Valo 			priv->tx_paths = 2;
364028fa281SKalle Valo 			priv->usb_interrupts = 0;
365028fa281SKalle Valo 			priv->rtl_chip = RTL8192C;
366028fa281SKalle Valo 		}
367028fa281SKalle Valo 		priv->rf_paths = 2;
368028fa281SKalle Valo 		priv->rx_paths = 2;
369028fa281SKalle Valo 	} else {
370028fa281SKalle Valo 		strscpy(priv->chip_name, "8188CU", sizeof(priv->chip_name));
371028fa281SKalle Valo 		priv->rf_paths = 1;
372028fa281SKalle Valo 		priv->rx_paths = 1;
373028fa281SKalle Valo 		priv->tx_paths = 1;
374028fa281SKalle Valo 		priv->rtl_chip = RTL8188C;
375028fa281SKalle Valo 		priv->usb_interrupts = 0;
376028fa281SKalle Valo 	}
377028fa281SKalle Valo 	priv->has_wifi = 1;
378028fa281SKalle Valo 
379028fa281SKalle Valo 	vendor = sys_cfg & SYS_CFG_VENDOR_ID;
380028fa281SKalle Valo 	rtl8xxxu_identify_vendor_1bit(priv, vendor);
381028fa281SKalle Valo 
382028fa281SKalle Valo 	val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
383028fa281SKalle Valo 	priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID);
384028fa281SKalle Valo 
385028fa281SKalle Valo 	rtl8xxxu_config_endpoints_sie(priv);
386028fa281SKalle Valo 
387028fa281SKalle Valo 	/*
388028fa281SKalle Valo 	 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
389028fa281SKalle Valo 	 */
390028fa281SKalle Valo 	if (!priv->ep_tx_count)
391028fa281SKalle Valo 		ret = rtl8xxxu_config_endpoints_no_sie(priv);
392028fa281SKalle Valo 
393028fa281SKalle Valo out:
394028fa281SKalle Valo 	return ret;
395028fa281SKalle Valo }
396028fa281SKalle Valo 
rtl8192cu_load_firmware(struct rtl8xxxu_priv * priv)397028fa281SKalle Valo static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
398028fa281SKalle Valo {
399028fa281SKalle Valo 	const char *fw_name;
400028fa281SKalle Valo 	int ret;
401028fa281SKalle Valo 
402028fa281SKalle Valo 	if (!priv->vendor_umc)
403028fa281SKalle Valo 		fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
404028fa281SKalle Valo 	else if (priv->chip_cut || priv->rtl_chip == RTL8192C)
405028fa281SKalle Valo 		fw_name = "rtlwifi/rtl8192cufw_B.bin";
406028fa281SKalle Valo 	else
407028fa281SKalle Valo 		fw_name = "rtlwifi/rtl8192cufw_A.bin";
408028fa281SKalle Valo 
409028fa281SKalle Valo 	ret = rtl8xxxu_load_firmware(priv, fw_name);
410028fa281SKalle Valo 
411028fa281SKalle Valo 	return ret;
412028fa281SKalle Valo }
413028fa281SKalle Valo 
rtl8192cu_parse_efuse(struct rtl8xxxu_priv * priv)414028fa281SKalle Valo static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
415028fa281SKalle Valo {
416028fa281SKalle Valo 	struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
417028fa281SKalle Valo 
418028fa281SKalle Valo 	if (efuse->rtl_id != cpu_to_le16(0x8129))
419028fa281SKalle Valo 		return -EINVAL;
420028fa281SKalle Valo 
421028fa281SKalle Valo 	ether_addr_copy(priv->mac_addr, efuse->mac_addr);
422028fa281SKalle Valo 
423028fa281SKalle Valo 	memcpy(priv->cck_tx_power_index_A,
424028fa281SKalle Valo 	       efuse->cck_tx_power_index_A,
425028fa281SKalle Valo 	       sizeof(efuse->cck_tx_power_index_A));
426028fa281SKalle Valo 	memcpy(priv->cck_tx_power_index_B,
427028fa281SKalle Valo 	       efuse->cck_tx_power_index_B,
428028fa281SKalle Valo 	       sizeof(efuse->cck_tx_power_index_B));
429028fa281SKalle Valo 
430028fa281SKalle Valo 	memcpy(priv->ht40_1s_tx_power_index_A,
431028fa281SKalle Valo 	       efuse->ht40_1s_tx_power_index_A,
432028fa281SKalle Valo 	       sizeof(efuse->ht40_1s_tx_power_index_A));
433028fa281SKalle Valo 	memcpy(priv->ht40_1s_tx_power_index_B,
434028fa281SKalle Valo 	       efuse->ht40_1s_tx_power_index_B,
435028fa281SKalle Valo 	       sizeof(efuse->ht40_1s_tx_power_index_B));
436028fa281SKalle Valo 	memcpy(priv->ht40_2s_tx_power_index_diff,
437028fa281SKalle Valo 	       efuse->ht40_2s_tx_power_index_diff,
438028fa281SKalle Valo 	       sizeof(efuse->ht40_2s_tx_power_index_diff));
439028fa281SKalle Valo 
440028fa281SKalle Valo 	memcpy(priv->ht20_tx_power_index_diff,
441028fa281SKalle Valo 	       efuse->ht20_tx_power_index_diff,
442028fa281SKalle Valo 	       sizeof(efuse->ht20_tx_power_index_diff));
443028fa281SKalle Valo 	memcpy(priv->ofdm_tx_power_index_diff,
444028fa281SKalle Valo 	       efuse->ofdm_tx_power_index_diff,
445028fa281SKalle Valo 	       sizeof(efuse->ofdm_tx_power_index_diff));
446028fa281SKalle Valo 
447028fa281SKalle Valo 	memcpy(priv->ht40_max_power_offset,
448028fa281SKalle Valo 	       efuse->ht40_max_power_offset,
449028fa281SKalle Valo 	       sizeof(efuse->ht40_max_power_offset));
450028fa281SKalle Valo 	memcpy(priv->ht20_max_power_offset,
451028fa281SKalle Valo 	       efuse->ht20_max_power_offset,
452028fa281SKalle Valo 	       sizeof(efuse->ht20_max_power_offset));
453028fa281SKalle Valo 
454028fa281SKalle Valo 	priv->power_base = &rtl8192c_power_base;
455028fa281SKalle Valo 
456028fa281SKalle Valo 	if (efuse->rf_regulatory & 0x20) {
457028fa281SKalle Valo 		strscpy(priv->chip_name, "8188RU", sizeof(priv->chip_name));
458028fa281SKalle Valo 		priv->rtl_chip = RTL8188R;
459028fa281SKalle Valo 		priv->hi_pa = 1;
460028fa281SKalle Valo 		priv->no_pape = 1;
461028fa281SKalle Valo 		priv->power_base = &rtl8188r_power_base;
462028fa281SKalle Valo 	}
463028fa281SKalle Valo 
464028fa281SKalle Valo 	return 0;
465028fa281SKalle Valo }
466028fa281SKalle Valo 
rtl8192cu_init_phy_rf(struct rtl8xxxu_priv * priv)467028fa281SKalle Valo static int rtl8192cu_init_phy_rf(struct rtl8xxxu_priv *priv)
468028fa281SKalle Valo {
469028fa281SKalle Valo 	const struct rtl8xxxu_rfregval *rftable;
470028fa281SKalle Valo 	int ret;
471028fa281SKalle Valo 
472028fa281SKalle Valo 	if (priv->rtl_chip == RTL8188R) {
473028fa281SKalle Valo 		rftable = rtl8188ru_radioa_1t_highpa_table;
474028fa281SKalle Valo 		ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
475028fa281SKalle Valo 	} else if (priv->rf_paths == 1) {
476028fa281SKalle Valo 		rftable = rtl8192cu_radioa_1t_init_table;
477028fa281SKalle Valo 		ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
478028fa281SKalle Valo 	} else {
479028fa281SKalle Valo 		rftable = rtl8192cu_radioa_2t_init_table;
480028fa281SKalle Valo 		ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
481028fa281SKalle Valo 		if (ret)
482028fa281SKalle Valo 			goto exit;
483028fa281SKalle Valo 		rftable = rtl8192cu_radiob_2t_init_table;
484028fa281SKalle Valo 		ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
485028fa281SKalle Valo 	}
486028fa281SKalle Valo 
487028fa281SKalle Valo exit:
488028fa281SKalle Valo 	return ret;
489028fa281SKalle Valo }
490028fa281SKalle Valo 
rtl8192cu_power_on(struct rtl8xxxu_priv * priv)491028fa281SKalle Valo static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
492028fa281SKalle Valo {
493028fa281SKalle Valo 	u8 val8;
494028fa281SKalle Valo 	u16 val16;
495028fa281SKalle Valo 	u32 val32;
496028fa281SKalle Valo 	int i;
497028fa281SKalle Valo 
498028fa281SKalle Valo 	for (i = 100; i; i--) {
499028fa281SKalle Valo 		val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
500028fa281SKalle Valo 		if (val8 & APS_FSMCO_PFM_ALDN)
501028fa281SKalle Valo 			break;
502028fa281SKalle Valo 	}
503028fa281SKalle Valo 
504028fa281SKalle Valo 	if (!i) {
505028fa281SKalle Valo 		pr_info("%s: Poll failed\n", __func__);
506028fa281SKalle Valo 		return -ENODEV;
507028fa281SKalle Valo 	}
508028fa281SKalle Valo 
509028fa281SKalle Valo 	/*
510028fa281SKalle Valo 	 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
511028fa281SKalle Valo 	 */
512028fa281SKalle Valo 	rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
513028fa281SKalle Valo 	rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
514028fa281SKalle Valo 	udelay(100);
515028fa281SKalle Valo 
516028fa281SKalle Valo 	val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
517028fa281SKalle Valo 	if (!(val8 & LDOV12D_ENABLE)) {
518028fa281SKalle Valo 		pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
519028fa281SKalle Valo 		val8 |= LDOV12D_ENABLE;
520028fa281SKalle Valo 		rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
521028fa281SKalle Valo 
522028fa281SKalle Valo 		udelay(100);
523028fa281SKalle Valo 
524028fa281SKalle Valo 		val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
525028fa281SKalle Valo 		val8 &= ~SYS_ISO_MD2PP;
526028fa281SKalle Valo 		rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
527028fa281SKalle Valo 	}
528028fa281SKalle Valo 
529028fa281SKalle Valo 	/*
530028fa281SKalle Valo 	 * Auto enable WLAN
531028fa281SKalle Valo 	 */
532028fa281SKalle Valo 	val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
533028fa281SKalle Valo 	val16 |= APS_FSMCO_MAC_ENABLE;
534028fa281SKalle Valo 	rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
535028fa281SKalle Valo 
536028fa281SKalle Valo 	for (i = 1000; i; i--) {
537028fa281SKalle Valo 		val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
538028fa281SKalle Valo 		if (!(val16 & APS_FSMCO_MAC_ENABLE))
539028fa281SKalle Valo 			break;
540028fa281SKalle Valo 	}
541028fa281SKalle Valo 	if (!i) {
542028fa281SKalle Valo 		pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
543028fa281SKalle Valo 		return -EBUSY;
544028fa281SKalle Valo 	}
545028fa281SKalle Valo 
546028fa281SKalle Valo 	/*
547028fa281SKalle Valo 	 * Enable radio, GPIO, LED
548028fa281SKalle Valo 	 */
549028fa281SKalle Valo 	val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
550028fa281SKalle Valo 		APS_FSMCO_PFM_ALDN;
551028fa281SKalle Valo 	rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
552028fa281SKalle Valo 
553028fa281SKalle Valo 	/*
554028fa281SKalle Valo 	 * Release RF digital isolation
555028fa281SKalle Valo 	 */
556028fa281SKalle Valo 	val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
557028fa281SKalle Valo 	val16 &= ~SYS_ISO_DIOR;
558028fa281SKalle Valo 	rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
559028fa281SKalle Valo 
560028fa281SKalle Valo 	val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
561028fa281SKalle Valo 	val8 &= ~APSD_CTRL_OFF;
562028fa281SKalle Valo 	rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
563028fa281SKalle Valo 	for (i = 200; i; i--) {
564028fa281SKalle Valo 		val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
565028fa281SKalle Valo 		if (!(val8 & APSD_CTRL_OFF_STATUS))
566028fa281SKalle Valo 			break;
567028fa281SKalle Valo 	}
568028fa281SKalle Valo 
569028fa281SKalle Valo 	if (!i) {
570028fa281SKalle Valo 		pr_info("%s: APSD_CTRL poll failed\n", __func__);
571028fa281SKalle Valo 		return -EBUSY;
572028fa281SKalle Valo 	}
573028fa281SKalle Valo 
574028fa281SKalle Valo 	/*
575028fa281SKalle Valo 	 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
576028fa281SKalle Valo 	 */
577028fa281SKalle Valo 	val16 = rtl8xxxu_read16(priv, REG_CR);
578028fa281SKalle Valo 	val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
579028fa281SKalle Valo 		CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
580028fa281SKalle Valo 		CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
581028fa281SKalle Valo 	rtl8xxxu_write16(priv, REG_CR, val16);
582028fa281SKalle Valo 
583028fa281SKalle Valo 	rtl8xxxu_write8(priv, 0xfe10, 0x19);
584028fa281SKalle Valo 
585028fa281SKalle Valo 	/*
586028fa281SKalle Valo 	 * Workaround for 8188RU LNA power leakage problem.
587028fa281SKalle Valo 	 */
588028fa281SKalle Valo 	if (priv->rtl_chip == RTL8188R) {
589028fa281SKalle Valo 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
590028fa281SKalle Valo 		val32 &= ~BIT(1);
591028fa281SKalle Valo 		rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
592028fa281SKalle Valo 	}
593028fa281SKalle Valo 	return 0;
594028fa281SKalle Valo }
595028fa281SKalle Valo 
rtl8192cu_led_brightness_set(struct led_classdev * led_cdev,enum led_brightness brightness)596028fa281SKalle Valo static int rtl8192cu_led_brightness_set(struct led_classdev *led_cdev,
597028fa281SKalle Valo 					enum led_brightness brightness)
598028fa281SKalle Valo {
599028fa281SKalle Valo 	struct rtl8xxxu_priv *priv = container_of(led_cdev,
600028fa281SKalle Valo 						  struct rtl8xxxu_priv,
601028fa281SKalle Valo 						  led_cdev);
602028fa281SKalle Valo 	u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG0);
603028fa281SKalle Valo 
604028fa281SKalle Valo 	if (brightness == LED_OFF)
605028fa281SKalle Valo 		ledcfg = LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE;
606028fa281SKalle Valo 	else if (brightness == LED_ON)
607028fa281SKalle Valo 		ledcfg = LEDCFG2_SW_LED_CONTROL;
608028fa281SKalle Valo 	else if (brightness == RTL8XXXU_HW_LED_CONTROL)
609028fa281SKalle Valo 		ledcfg = LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE;
610028fa281SKalle Valo 
611028fa281SKalle Valo 	rtl8xxxu_write8(priv, REG_LEDCFG0, ledcfg);
612028fa281SKalle Valo 
613028fa281SKalle Valo 	return 0;
614028fa281SKalle Valo }
615028fa281SKalle Valo 
616028fa281SKalle Valo struct rtl8xxxu_fileops rtl8192cu_fops = {
617028fa281SKalle Valo 	.identify_chip = rtl8192cu_identify_chip,
618028fa281SKalle Valo 	.parse_efuse = rtl8192cu_parse_efuse,
619028fa281SKalle Valo 	.load_firmware = rtl8192cu_load_firmware,
620028fa281SKalle Valo 	.power_on = rtl8192cu_power_on,
621028fa281SKalle Valo 	.power_off = rtl8xxxu_power_off,
622028fa281SKalle Valo 	.read_efuse = rtl8xxxu_read_efuse,
623028fa281SKalle Valo 	.reset_8051 = rtl8xxxu_reset_8051,
624028fa281SKalle Valo 	.llt_init = rtl8xxxu_init_llt_table,
625028fa281SKalle Valo 	.init_phy_bb = rtl8xxxu_gen1_init_phy_bb,
626028fa281SKalle Valo 	.init_phy_rf = rtl8192cu_init_phy_rf,
627028fa281SKalle Valo 	.phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
628028fa281SKalle Valo 	.phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate,
629028fa281SKalle Valo 	.config_channel = rtl8xxxu_gen1_config_channel,
630028fa281SKalle Valo 	.parse_rx_desc = rtl8xxxu_parse_rxdesc16,
631028fa281SKalle Valo 	.parse_phystats = rtl8723au_rx_parse_phystats,
632028fa281SKalle Valo 	.init_aggregation = rtl8xxxu_gen1_init_aggregation,
633028fa281SKalle Valo 	.enable_rf = rtl8xxxu_gen1_enable_rf,
634028fa281SKalle Valo 	.disable_rf = rtl8xxxu_gen1_disable_rf,
635028fa281SKalle Valo 	.usb_quirks = rtl8xxxu_gen1_usb_quirks,
636028fa281SKalle Valo 	.set_tx_power = rtl8xxxu_gen1_set_tx_power,
637028fa281SKalle Valo 	.update_rate_mask = rtl8xxxu_update_rate_mask,
638028fa281SKalle Valo 	.report_connect = rtl8xxxu_gen1_report_connect,
639028fa281SKalle Valo 	.report_rssi = rtl8xxxu_gen1_report_rssi,
640028fa281SKalle Valo 	.fill_txdesc = rtl8xxxu_fill_txdesc_v1,
641028fa281SKalle Valo 	.cck_rssi = rtl8723a_cck_rssi,
642028fa281SKalle Valo 	.led_classdev_brightness_set = rtl8192cu_led_brightness_set,
643028fa281SKalle Valo 	.writeN_block_size = 128,
644028fa281SKalle Valo 	.rx_agg_buf_size = 16000,
645028fa281SKalle Valo 	.tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
646028fa281SKalle Valo 	.rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),
647028fa281SKalle Valo 	.max_sec_cam_num = 32,
648028fa281SKalle Valo 	.adda_1t_init = 0x0b1b25a0,
649028fa281SKalle Valo 	.adda_1t_path_on = 0x0bdb25a0,
650028fa281SKalle Valo 	.adda_2t_path_on_a = 0x04db25a4,
651028fa281SKalle Valo 	.adda_2t_path_on_b = 0x0b1b25a4,
652028fa281SKalle Valo 	.trxff_boundary = 0x27ff,
653028fa281SKalle Valo 	.pbp_rx = PBP_PAGE_SIZE_128,
654028fa281SKalle Valo 	.pbp_tx = PBP_PAGE_SIZE_128,
655028fa281SKalle Valo 	.mactable = rtl8192cu_mac_init_table,
656028fa281SKalle Valo 	.total_page_num = TX_TOTAL_PAGE_NUM,
657028fa281SKalle Valo 	.page_num_hi = TX_PAGE_NUM_HI_PQ,
658028fa281SKalle Valo 	.page_num_lo = TX_PAGE_NUM_LO_PQ,
659028fa281SKalle Valo 	.page_num_norm = TX_PAGE_NUM_NORM_PQ,
660028fa281SKalle Valo };
661028fa281SKalle Valo #endif
662