| /linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_6_0_sh_mask.h | 26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
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| /linux/drivers/gpu/drm/amd/include/asic_reg/dce/ |
| H A D | dce_6_0_sh_mask.h | 26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL
27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000
28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL
29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000
30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000
34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001
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| /linux/drivers/gpu/drm/amd/include/asic_reg/smu/ |
| H A D | smu_6_0_sh_mask.h | 26 #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x03ffffffL
27 #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x00000000
28 #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x000003f0L
29 #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x00000004
30 #define GPIOPAD_A__GPIO_A_MASK 0x7fffffffL
31 #define GPIOPAD_A__GPIO_A__SHIFT 0x00000000
32 #define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffffL
33 #define GPIOPAD_EN__GPIO_EN__SHIFT 0x00000000
34 #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x00000020L
35 #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x00000005
[all …]
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| /linux/Documentation/devicetree/bindings/thermal/ |
| H A D | qoriq-thermal.yaml | 20 Register (IPBRR0) at offset 0x0BF8.
24 0x01900102 T1040
82 reg = <0xf0000 0x1000>;
83 interrupts = <18 2 0 0>;
84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
85 fsl,tmu-calibration = <0x00000000 0x00000025>,
86 <0x00000001 0x00000028>,
87 <0x00000002 0x0000002d>,
88 <0x00000003 0x00000031>,
89 <0x00000004 0x00000036>,
[all …]
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| /linux/drivers/gpu/drm/amd/include/asic_reg/bif/ |
| H A D | bif_3_0_sh_mask.h | 26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
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| /linux/drivers/gpu/drm/etnaviv/ |
| H A D | cmdstream.xml.h | 7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
42 #define FE_OPCODE_LOAD_STATE 0x00000001
43 #define FE_OPCODE_END 0x00000002
44 #define FE_OPCODE_NOP 0x00000003
45 #define FE_OPCODE_DRAW_2D 0x00000004
46 #define FE_OPCODE_DRAW_PRIMITIVES 0x00000005
47 #define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006
48 #define FE_OPCODE_WAIT 0x00000007
49 #define FE_OPCODE_LINK 0x00000008
[all …]
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| H A D | state.xml.h | 7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define VARYING_COMPONENT_USE_UNUSED 0x00000000
49 #define VARYING_COMPONENT_USE_USED 0x00000001
50 #define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002
51 #define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003
52 #define FE_DATA_TYPE_BYTE 0x00000000
53 #define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001
54 #define FE_DATA_TYPE_SHORT 0x00000002
55 #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003
[all …]
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| /linux/arch/alpha/include/uapi/asm/ |
| H A D | termbits.h | 54 #define VEOF 0
73 #define IXON 0x0200
74 #define IXOFF 0x0400
75 #define IUCLC 0x1000
76 #define IMAXBEL 0x2000
77 #define IUTF8 0x4000
80 #define ONLCR 0x00002
81 #define OLCUC 0x00004
82 #define NLDLY 0x00300
83 #define NL0 0x00000
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| /linux/arch/arm/include/uapi/asm/ |
| H A D | ptrace.h | 37 #define PTRACE_GETFDPIC_EXEC 0
44 #define USR26_MODE 0x00000000
45 #define FIQ26_MODE 0x00000001
46 #define IRQ26_MODE 0x00000002
47 #define SVC26_MODE 0x00000003
50 * Use 0 here to get code right that creates a userspace
53 #define USR_MODE 0x00000000
54 #define SVC_MODE 0x00000000
56 #define USR_MODE 0x00000010
57 #define SVC_MODE 0x00000013
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| /linux/drivers/media/pci/saa7164/ |
| H A D | saa7164-fw.c | 29 while ((saa7164_readl(reg) & 0x01) == 0) { in saa7164_dl_wait_ack()
31 if (timeout == 0) { in saa7164_dl_wait_ack()
39 return 0; in saa7164_dl_wait_ack()
45 while (saa7164_readl(reg) & 0x01) { in saa7164_dl_wait_clr()
47 if (timeout == 0) { in saa7164_dl_wait_clr()
55 return 0; in saa7164_dl_wait_clr()
74 "%s(image=%p, size=%d, flags=0x%x, dst=%p, dstsize=0x%x)\n", in saa7164_downloadimage()
95 dprintk(DBGLVL_FW, "%s() dlflag = 0x%x\n", __func__, dlflag); in saa7164_downloadimage()
96 dprintk(DBGLVL_FW, "%s() dlflag_ack = 0x%x\n", __func__, dlflag_ack); in saa7164_downloadimage()
97 dprintk(DBGLVL_FW, "%s() drflag = 0x%x\n", __func__, drflag); in saa7164_downloadimage()
[all …]
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| /linux/include/net/ |
| H A D | ieee80211_radiotap.h | 29 * @it_version: radiotap version, always 0
58 /* version is always 0 */
59 #define PKTHDR_RADIOTAP_VERSION 0
63 IEEE80211_RADIOTAP_TSFT = 0,
102 IEEE80211_RADIOTAP_F_CFP = 0x01,
103 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
104 IEEE80211_RADIOTAP_F_WEP = 0x04,
105 IEEE80211_RADIOTAP_F_FRAG = 0x08,
106 IEEE80211_RADIOTAP_F_FCS = 0x10,
107 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]
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| /linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| H A D | oss_1_0_sh_mask.h | 26 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
27 #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
28 #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L
29 #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004
30 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L
31 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014
32 #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L
33 #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018
34 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
35 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
[all …]
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| /linux/include/linux/ssb/ |
| H A D | ssb_driver_extif.h | 24 #define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
25 #define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
26 #define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
27 #define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
47 #define SSB_EXTIF_CTL 0x0000
48 #define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */
49 #define SSB_EXTIF_EXTSTAT 0x0004
50 #define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */
53 #define SSB_EXTIF_PCMCIA_CFG 0x0010
54 #define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014
[all …]
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| H A D | gm200.c | 41 pu &= 0x0f; in gm200_sor_dp_drive()
43 data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); in gm200_sor_dp_drive()
44 data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); in gm200_sor_dp_drive()
45 data[2] = nvkm_rd32(device, 0x61c130 + loff); in gm200_sor_dp_drive()
46 if ((data[2] & 0x00000f00) < (pu << 8) || ln == 0) in gm200_sor_dp_drive()
47 data[2] = (data[2] & ~0x00000f00) | (pu << 8); in gm200_sor_dp_drive()
49 nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift)); in gm200_sor_dp_drive()
50 nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift)); in gm200_sor_dp_drive()
51 nvkm_wr32(device, 0x61c130 + loff, data[2]); in gm200_sor_dp_drive()
53 data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift); in gm200_sor_dp_drive()
[all …]
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| /linux/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/ |
| H A D | instruction.json | 4 "EventCode": "0x00000006",
9 "EventCode": "0x00000007",
14 "EventCode": "0x00000008",
19 "EventCode": "0x00000009",
24 "EventCode": "0x0000000b",
29 "EventCode": "0x0000001d",
34 "EventCode": "0x0000001e",
39 "EventCode": "0x0000001f",
44 "EventCode": "0x00000020",
49 "EventCode": "0x00000021",
[all …]
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| /linux/drivers/net/ethernet/intel/igb/ |
| H A D | e1000_82575.h | 26 #define E1000_SW_SYNCH_MB 0x00000100
27 #define E1000_STAT_DEV_RST_SET 0x00100000
28 #define E1000_CTRL_DEV_RST 0x20000000
33 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
34 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
35 #define E1000_SRRCTL_DROP_EN 0x80000000
36 #define E1000_SRRCTL_TIMESTAMP 0x40000000
39 #define E1000_MRQC_ENABLE_RSS_MQ 0x00000002
40 #define E1000_MRQC_ENABLE_VMDQ 0x00000003
41 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
[all …]
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| H A D | gmc_6_0_sh_mask.h | 26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
[all …]
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| /linux/arch/powerpc/include/asm/nohash/ |
| H A D | mmu-e500.h | 9 #define BOOK3E_PAGESZ_1K 0
44 #define MAS0_TLBSEL_MASK 0x30000000
49 #define MAS0_ESEL_MASK 0x0FFF0000
52 #define MAS0_NV(x) ((x) & 0x00000FFF)
53 #define MAS0_HES 0x00004000
54 #define MAS0_WQ_ALLWAYS 0x00000000
55 #define MAS0_WQ_COND 0x00001000
56 #define MAS0_WQ_CLR_RSRV 0x00002000
58 #define MAS1_VALID 0x80000000
59 #define MAS1_IPROT 0x40000000
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/fault/ |
| H A D | gv100.c | 34 struct nvkm_fault_buffer *buffer = fault->buffer[0]; in gv100_fault_buffer_process()
45 const u32 instlo = nvkm_ro32(mem, base + 0x00); in gv100_fault_buffer_process()
46 const u32 insthi = nvkm_ro32(mem, base + 0x04); in gv100_fault_buffer_process()
47 const u32 addrlo = nvkm_ro32(mem, base + 0x08); in gv100_fault_buffer_process()
48 const u32 addrhi = nvkm_ro32(mem, base + 0x0c); in gv100_fault_buffer_process()
49 const u32 timelo = nvkm_ro32(mem, base + 0x10); in gv100_fault_buffer_process()
50 const u32 timehi = nvkm_ro32(mem, base + 0x14); in gv100_fault_buffer_process()
51 const u32 info0 = nvkm_ro32(mem, base + 0x18); in gv100_fault_buffer_process()
52 const u32 info1 = nvkm_ro32(mem, base + 0x1c); in gv100_fault_buffer_process()
56 get = 0; in gv100_fault_buffer_process()
[all …]
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| /linux/drivers/media/pci/cx88/ |
| H A D | cx88-tvaudio.c | 52 "Radio deemphasis time constant, 0=None, 1=50us (elsewhere), 2=75us (USA)");
58 } while (0)
96 for (i = 0; l[i].reg; i++) { in set_audio_registers()
120 cx_write(AUD_INIT_LD, 0x0001); in set_audio_start()
121 cx_write(AUD_SOFT_RESET, 0x0001); in set_audio_start()
130 cx_write(AUD_RATE_THRES_DMD, 0x000000C0); in set_audio_finish()
142 cx_write(AUD_I2SCNTL, 0); in set_audio_finish()
143 /* cx_write(AUD_APB_IN_RATE_ADJ, 0); */ in set_audio_finish()
151 cx_write(AUD_SOFT_RESET, 0x0000); in set_audio_finish()
166 {AUD_AFE_12DB_EN, 0x00000001}, in set_audio_standard_BTSC()
[all …]
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| /linux/arch/sparc/include/uapi/asm/ |
| H A D | psrcompat.h | 8 #define PSR_CWP 0x0000001f /* current window pointer */
9 #define PSR_ET 0x00000020 /* enable traps field */
10 #define PSR_PS 0x00000040 /* previous privilege level */
11 #define PSR_S 0x00000080 /* current privilege level */
12 #define PSR_PIL 0x00000f00 /* processor interrupt level */
13 #define PSR_EF 0x00001000 /* enable floating point */
14 #define PSR_EC 0x00002000 /* enable co-processor */
15 #define PSR_SYSCALL 0x00004000 /* inside of a syscall */
16 #define PSR_LE 0x00008000 /* SuperSparcII little-endian */
17 #define PSR_ICC 0x00f00000 /* integer condition codes */
[all …]
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/ |
| H A D | ga102.c | 31 nvkm_mask(device, 0x17e338, 0x0000001f, i); in ga102_ltc_zbc_clear_color()
32 nvkm_wr32(device, 0x17e33c, color[0]); in ga102_ltc_zbc_clear_color()
33 nvkm_wr32(device, 0x17e340, color[1]); in ga102_ltc_zbc_clear_color()
34 nvkm_wr32(device, 0x17e344, color[2]); in ga102_ltc_zbc_clear_color()
35 nvkm_wr32(device, 0x17e348, color[3]); in ga102_ltc_zbc_clear_color()
|
| /linux/drivers/net/wireless/realtek/rtw89/ |
| H A D | rtw8852a_rfk_table.c | 8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
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| /linux/include/linux/bcma/ |
| H A D | bcma_driver_gmac_cmn.h | 7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
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| /linux/tools/power/cpupower/debug/i386/ |
| H A D | powernow-k8-decode.c | 22 #define MSR_FIDVID_STATUS 0xc0010042
24 #define MSR_S_HI_CURRENT_VID 0x0000001f
25 #define MSR_S_LO_CURRENT_FID 0x0000003f
30 uint64_t msr = 0; in get_fidvid()
40 if (fd < 0) in get_fidvid()
46 *fid = ((uint32_t )(msr & 0xffffffffull)) & MSR_S_LO_CURRENT_FID; in get_fidvid()
47 *vid = ((uint32_t )(msr>>32 & 0xffffffffull)) & MSR_S_HI_CURRENT_VID; in get_fidvid()
48 err = 0; in get_fidvid()
75 cpu = 0; in main()
77 cpu = strtoul(argv[1], NULL, 0); in main()
[all …]
|