Lines Matching +full:0 +full:x0000001f
26 #define E1000_SW_SYNCH_MB 0x00000100
27 #define E1000_STAT_DEV_RST_SET 0x00100000
28 #define E1000_CTRL_DEV_RST 0x20000000
33 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
34 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
35 #define E1000_SRRCTL_DROP_EN 0x80000000
36 #define E1000_SRRCTL_TIMESTAMP 0x40000000
39 #define E1000_MRQC_ENABLE_RSS_MQ 0x00000002
40 #define E1000_MRQC_ENABLE_VMDQ 0x00000003
41 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
42 #define E1000_MRQC_ENABLE_VMDQ_RSS_MQ 0x00000005
43 #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
44 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
59 #define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
60 #define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
90 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
92 #define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
93 #define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
110 #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
111 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
112 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
113 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
114 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
115 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
116 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
117 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
118 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
130 #define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
131 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
132 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
133 #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
141 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
142 /* Tx Queue Arbitration Priority 0=low, 1=high */
145 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
148 #define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
149 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
151 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
157 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
164 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
165 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
175 #define E1000_ETQF_QUEUE_MASK 0x00070000
176 #define E1000_ETQF_ETYPE_MASK 0x0000FFFF
179 #define E1000_FTQF_VF_BP 0x00008000
180 #define E1000_FTQF_1588_TIME_STAMP 0x08000000
181 #define E1000_FTQF_MASK 0xF0000000
182 #define E1000_FTQF_MASK_PROTO_BP 0x10000000
183 #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
185 #define E1000_NVM_APME_82575 0x0400
188 #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */
189 #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
190 #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
196 #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
204 #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
205 #define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
206 #define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
207 #define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
208 #define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
209 #define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
210 #define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
211 #define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
212 #define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
213 #define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
215 #define E1000_DVMOLR_HIDEVLAN 0x20000000 /* Hide vlan enable */
216 #define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
217 #define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */
220 #define E1000_VLVF_VLANID_MASK 0x00000FFF
222 #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
223 #define E1000_VLVF_LVLAN 0x00100000
224 #define E1000_VLVF_VLANID_ENABLE 0x80000000
226 #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
227 #define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
229 #define E1000_IOVCTL 0x05BBC
230 #define E1000_IOVCTL_REUSE_VFQ 0x00000001
232 #define E1000_RPLOLR_STRVLAN 0x40000000
233 #define E1000_RPLOLR_STRCRC 0x80000000
235 #define E1000_DTXCTL_8023LL 0x0004
236 #define E1000_DTXCTL_VLAN_ADDED 0x0008
237 #define E1000_DTXCTL_OOS_ENABLE 0x0010
238 #define E1000_DTXCTL_MDP_EN 0x0020
239 #define E1000_DTXCTL_SPOOF_INT 0x0040
243 #define ALL_QUEUES 0xFFFF
246 #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
256 #define E1000_I2C_THERMAL_SENSOR_ADDR 0xF8
257 #define E1000_EMC_INTERNAL_DATA 0x00
258 #define E1000_EMC_INTERNAL_THERM_LIMIT 0x20
259 #define E1000_EMC_DIODE1_DATA 0x01
260 #define E1000_EMC_DIODE1_THERM_LIMIT 0x19
261 #define E1000_EMC_DIODE2_DATA 0x23
262 #define E1000_EMC_DIODE2_THERM_LIMIT 0x1A
263 #define E1000_EMC_DIODE3_DATA 0x2A
264 #define E1000_EMC_DIODE3_THERM_LIMIT 0x30