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/linux/drivers/misc/eeprom/
H A Ddigsy_mtc_eeprom.c55 GPIO_LOOKUP("gpio@b00", GPIO_EEPROM_CLK,
57 GPIO_LOOKUP("gpio@b00", GPIO_EEPROM_DI,
59 GPIO_LOOKUP("gpio@b00", GPIO_EEPROM_DO,
61 GPIO_LOOKUP("gpio@b00", GPIO_EEPROM_CS,
63 GPIO_LOOKUP("gpio@b00", GPIO_EEPROM_OE,
74 .chip_select = 0,
/linux/include/linux/irqchip/
H A Darm-gic-v5.h19 #define GICV5_HWIRQ_ID GENMASK(23, 0)
21 #define GICV5_HWIRQ_INTID GENMASK_ULL(31, 0)
23 #define GICV5_HWIRQ_TYPE_PPI UL(0x1)
24 #define GICV5_HWIRQ_TYPE_LPI UL(0x2)
25 #define GICV5_HWIRQ_TYPE_SPI UL(0x3)
30 #define GICV5_ARCH_PPI_S_DB_PPI 0x0
31 #define GICV5_ARCH_PPI_RL_DB_PPI 0x1
32 #define GICV5_ARCH_PPI_NS_DB_PPI 0x2
33 #define GICV5_ARCH_PPI_SW_PPI 0x3
34 #define GICV5_ARCH_PPI_HACDBSIRQ 0xf
[all …]
/linux/arch/powerpc/include/asm/
H A Dpnv-ocxl.h16 #define PNV_OCXL_ATSD_LNCH 0x00
18 #define PNV_OCXL_ATSD_LNCH_R PPC_BIT(0)
20 * 0b00 Just invalidate TLB.
21 * 0b01 Invalidate just Page Walk Cache.
22 * 0b10 Invalidate TLB, Page Walk Cache, and any
29 * 0b00 Invalidate just the target VA.
30 * 0b01 Invalidate matching PID.
33 /* 0b1: Process Scope, 0b0: Partition Scope */
45 * L=0b0 for 4KB pages
46 * L=0b1 for large pages)
[all …]
/linux/drivers/zorro/
H A Dzorro.ids16 0a00 [SCSI Host Adapter]
36 0a00 A590/A2052/A2058/A2091 [RAM Expansion]
58 0c00 A1000 [SCSI Host Adapter]
59 0e00 Escort [SCSI Host Adapter]
97 0a00 A4066 [Ethernet Card]
106 0a00 500RX/2000 [RAM Expansion]
107 0b00 2400zi [Modem]
108 0c00 500XP/SupraDrive WordSync [SCSI Host Adapter]
109 0d00 SupraDrive WordSync II [SCSI Host Adapter]
125 0e00 DKM 3128 [RAM Expansion]
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/
H A Dusb.txt9 #size-cells = <0>;
11 reg = <11b60 18 8b00 100>;
/linux/Documentation/devicetree/bindings/spi/
H A Dralink,mt7621-spi.yaml48 spi@b00 {
50 reg = <0xb00 0x100>;
57 #size-cells = <0>;
60 pinctrl-0 = <&spi_pins>;
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,spmi-clkdiv.yaml54 #size-cells = <0>;
56 clock-controller@5b00 {
58 reg = <0x5b00>;
/linux/arch/powerpc/sysdev/
H A Drtc_cmos_setup.c28 memset(&res, 0, sizeof(res)); in add_rtc()
30 np = of_find_compatible_node(NULL, NULL, "pnpPNP,b00"); in add_rtc()
34 ret = of_address_to_resource(np, 0, &res[0]); in add_rtc()
43 if (res[0].start != RTC_PORT(0)) in add_rtc()
54 * numbers 0..15. in add_rtc()
63 &res[0], num_res); in add_rtc()
/linux/Documentation/sound/soc/
H A Ddapm-graph.svg4 <!-- Generated by graphviz version 2.43.0 (0)
9 <g id="graph0" class="graph" transform="scale(1 1) rotate(0) translate(4 626)">
23 <title>cs42l51.0&#45;004a</title>
25 <text text-anchor="middle" x="607" y="-598.8" font-family="sans-serif" font-size="14.00">cs42l51.0&…
79 <!-- cs42l51.0&#45;004a_AIN1L -->
81 <title>cs42l51.0&#45;004a_AIN1L</title>
86 <!-- cs42l51.0&#45;004a_PGA&#45;ADC Mux Left -->
88 <title>cs42l51.0&#45;004a_PGA&#45;ADC Mux Left</title>
93 <!-- cs42l51.0&#45;004a_AIN1L&#45;&gt;cs42l51.0&#45;004a_PGA&#45;ADC Mux Left -->
95 <title>cs42l51.0&#45;004a_AIN1L&#45;&gt;cs42l51.0&#45;004a_PGA&#45;ADC Mux Left</title>
[all …]
/linux/include/uapi/linux/
H A Dcciss_defs.h12 #define CMD_SUCCESS 0x0000
13 #define CMD_TARGET_STATUS 0x0001
14 #define CMD_DATA_UNDERRUN 0x0002
15 #define CMD_DATA_OVERRUN 0x0003
16 #define CMD_INVALID 0x0004
17 #define CMD_PROTOCOL_ERR 0x0005
18 #define CMD_HARDWARE_ERR 0x0006
19 #define CMD_CONNECTION_LOST 0x0007
20 #define CMD_ABORTED 0x0008
21 #define CMD_ABORT_FAILED 0x0009
[all …]
/linux/arch/arm64/include/asm/
H A Dkvm_nested.h26 ((tcr & TCR_EL2_DS) ? TCR_DS : 0) | in translate_tcr_el2_to_tcr_el1()
27 ((tcr & TCR_EL2_TBI) ? TCR_TBI0 : 0) | in translate_tcr_el2_to_tcr_el1()
135 xn &= 0b10; in kvm_s2_trans_exec_el0()
138 case 0b00: in kvm_s2_trans_exec_el0()
139 case 0b01: in kvm_s2_trans_exec_el0()
151 xn &= 0b10; in kvm_s2_trans_exec_el1()
154 case 0b00: in kvm_s2_trans_exec_el1()
155 case 0b11: in kvm_s2_trans_exec_el1()
238 *elr = 0xbad9acc0debadbad; in kvm_auth_eretax()
253 u8 shift = 0; \
[all …]
/linux/arch/loongarch/include/asm/
H A Dhw_breakpoint.h13 #define LOONGARCH_BREAKPOINT_EXECUTE (0 << 0)
16 #define LOONGARCH_BREAKPOINT_LOAD (1 << 0)
32 #define LOONGARCH_BREAKPOINT_LEN_1 0b11
33 #define LOONGARCH_BREAKPOINT_LEN_2 0b10
34 #define LOONGARCH_BREAKPOINT_LEN_4 0b01
35 #define LOONGARCH_BREAKPOINT_LEN_8 0b00
45 #define CSR_CFG_ADDR 0
59 if (T == 0) \
63 } while (0)
67 if (T == 0) \
[all …]
/linux/drivers/clk/ralink/
H A Dclk-mtmips.c16 #define SYSC_REG_SYSTEM_CONFIG 0x10
17 #define SYSC_REG_CLKCFG0 0x2c
18 #define SYSC_REG_RESET_CTRL 0x34
19 #define SYSC_REG_CPU_SYS_CLKCFG 0x3c
20 #define SYSC_REG_CPLL_CONFIG0 0x54
21 #define SYSC_REG_CPLL_CONFIG1 0x58
25 #define RT2880_CONFIG_CPUCLK_MASK 0x3
26 #define RT2880_CONFIG_CPUCLK_250 0x0
27 #define RT2880_CONFIG_CPUCLK_266 0x1
28 #define RT2880_CONFIG_CPUCLK_280 0x2
[all …]
/linux/drivers/usb/host/
H A Docteon-hcd.h53 #define CVMX_USBCXBASE 0x00016F0010000000ull
56 ((bid) & 1) * 0x100000000000ull)
59 (((off) & 7) + ((bid) & 1) * 0x8000000000ull) * 32)
61 #define CVMX_USBCX_GAHBCFG(bid) CVMX_USBCXREG1(0x008, bid)
62 #define CVMX_USBCX_GHWCFG3(bid) CVMX_USBCXREG1(0x04c, bid)
63 #define CVMX_USBCX_GINTMSK(bid) CVMX_USBCXREG1(0x018, bid)
64 #define CVMX_USBCX_GINTSTS(bid) CVMX_USBCXREG1(0x014, bid)
65 #define CVMX_USBCX_GNPTXFSIZ(bid) CVMX_USBCXREG1(0x028, bid)
66 #define CVMX_USBCX_GNPTXSTS(bid) CVMX_USBCXREG1(0x02c, bid)
67 #define CVMX_USBCX_GOTGCTL(bid) CVMX_USBCXREG1(0x000, bid)
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dpmc.yaml17 example `sleep = <&pmc 0x00000030>`. Any cells after the &pmc phandle are
140 pmc: power@b00 {
142 reg = <0xb00 0x100>, <0xa00 0x100>;
149 reg = <0xe0070 0x20>;
/linux/arch/powerpc/boot/dts/
H A Dpdm360ng.dts23 reg = <0x00000000 0x20000000>; // 512MB at 0
27 bank-width = <0x1>;
28 chips = <0x1>;
30 partition@0 {
32 reg = <0x0 0x40000000>;
37 ranges = <0x0 0x0 0xf0000000 0x10000000 /* Flash */
38 0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */
40 flash@0,0 {
42 reg = <0 0x00000000 0x08000000
43 0 0x08000000 0x08000000>;
[all …]
H A Damigaone.dts20 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
29 timebase-frequency = <0>; // 33.3 MHz, from U-boot
30 clock-frequency = <0>; // From U-boot
31 bus-frequency = <0>; // From U-boot
37 reg = <0 0>; // From U-boot
44 bus-range = <0 0xff>;
45 ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00c00000 // PCI I/O
46 0x02000000 0 0x80000000 0x80000000 0 0x7d000000 // PCI memory
[all …]
H A Dtqm5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
H A Dcharon.dts23 #size-cells = <0>;
25 PowerPC,5200@0 {
27 reg = <0>;
30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
32 timebase-frequency = <0>; // from bootloader
33 bus-frequency = <0>; // from bootloader
34 clock-frequency = <0>; // from bootloader
38 memory@0 {
40 reg = <0x00000000 0x08000000>; // 128MB
[all …]
/linux/arch/powerpc/platforms/chrp/
H A Dtime.c33 #define NVRAM_AS0 0x74
34 #define NVRAM_AS1 0x75
35 #define NVRAM_DATA 0x77
47 rtcs = of_find_compatible_node(NULL, "rtc", "pnpPNP,b00"); in chrp_time_init()
51 return 0; in chrp_time_init()
52 if (of_address_to_resource(rtcs, 0, &r)) { in chrp_time_init()
54 return 0; in chrp_time_init()
59 nvram_as1 = 0; in chrp_time_init()
63 return 0; in chrp_time_init()
68 if (nvram_as1 != 0) in chrp_cmos_clock_read()
[all …]
/linux/drivers/net/mdio/
H A Dmdio-aspeed.c17 #define ASPEED_MDIO_CTRL 0x0
20 #define ASPEED_MDIO_CTRL_ST_C45 0
23 #define MDIO_C22_OP_WRITE 0b01
24 #define MDIO_C22_OP_READ 0b10
25 #define MDIO_C45_OP_ADDR 0b00
26 #define MDIO_C45_OP_WRITE 0b01
27 #define MDIO_C45_OP_PREAD 0b10
28 #define MDIO_C45_OP_READ 0b11
31 #define ASPEED_MDIO_CTRL_MIIWDATA GENMASK(15, 0)
33 #define ASPEED_MDIO_DATA 0x4
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8544ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x800000>;
44 partition@0 {
45 reg = <0x0 0x10000>;
50 reg = <0x20000 0x30000>;
56 reg = <0x200000 0x200000>;
62 reg = <0x400000 0x380000>;
67 reg = <0x780000 0x80000>;
82 phy0: ethernet-phy@0 {
83 interrupts = <10 1 0 0>;
[all …]
/linux/Documentation/admin-guide/perf/
H A Dhisi-pcie-pmu.rst42 $# perf stat -e hisi_pcie0_core0/rx_mwr_latency,port=0xffff/
43 $# perf stat -e hisi_pcie0_core0/rx_mwr_cnt,port=0xffff/
52 b) By event type, such as "event=0xXXXX, event=0x1XXXX".
56 …$# perf stat -e "{hisi_pcie0_core0/rx_mwr_latency,port=0xffff/,hisi_pcie0_core0/rx_mwr_cnt,port=0x…
73 "bdf" filter will be in effect, because "bdf=0" meaning 0000:000:00.0.
83 bitmap should be set, port=0x1; if target Root Port is 0000:00:04.0 (x4
84 lanes), bit8 is set, port=0x100; if these two Root Ports are both
85 monitored, port=0x101.
89 $# perf stat -e hisi_pcie0_core0/rx_mwr_latency,port=0x1/ sleep 5
97 For example, "bdf=0x3900" means BDF of target Endpoint is 0000:39:00.0.
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dam33xx-usb.txt61 endpoint number (0 … 14 for endpoints 1 … 15 on instance 0 and 15 … 29
62 for endpoints 1 … 15 on instance 1). The second number is 0 for RX and
81 reg = <0x47400000 0x1000>;
89 reg = <0x44e10620 0x10
90 0x44e10648 0x4>;
96 reg = <0x47401300 0x100>;
99 #phy-cells = <0>;
104 reg = <0x47401400 0x400
105 0x47401000 0x200>;
117 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
[all …]
/linux/arch/mips/boot/dts/brcm/
H A Dbcm7125.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
31 #address-cells = <0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
57 ranges = <0 0x10000000 0x01000000>;
61 reg = <0x441400 0x30>, <0x441600 0x30>;
72 reg = <0x401800 0x30>;
81 reg = <0x400000 0xdc>;
[all …]

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