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/linux/Documentation/devicetree/bindings/mips/
H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
11 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
21 - brcm,bmips3300
22 - brcm,bmips4350
23 - brcm,bmips4380
24 - brcm,bmips5000
25 - brcm,bmips5200
[all …]
/linux/arch/mips/boot/dts/ingenic/
H A Djz4780.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
4 #include <dt-bindings/dma/jz4780-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
[all …]
H A Djz4740.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
[all …]
H A Djz4725b.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
[all …]
H A Djz4770.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
17 reg = <0>;
[all …]
H A Dx1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
[all …]
/linux/arch/mips/include/asm/
H A Dcpu.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 register 15, select 0) is defined in this (backwards compatible) way:
18 +----------------+----------------+----------------+----------------+
20 +----------------+----------------+----------------+----------------+
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
[all …]
/linux/arch/mips/kernel/
H A Dcpu-probe.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 1994 - 2006 Ralf Baechle
19 #include <asm/cpu-features.h>
20 #include <asm/cpu-type.h>
27 #include <asm/pgtable-bits.h>
32 #include "fpu-probe.h"
34 #include <asm/mach-loongson64/cpucfg-emul.h>
57 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); in dsp_disable()
70 cpu_data[0].options &= ~MIPS_CPU_HTW; in htw_disable()
83 FTLB_EN = 1 << 0,
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