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/linux/Documentation/devicetree/bindings/net/
H A Dfsl,fman-mdio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Frame Manager MDIO Device
10 - Frank Li <Frank.Li@nxp.com>
12 description: FMan MDIO Node.
13 The MDIO is a bus to which the PHY devices are connected.
18 - fsl,fman-mdio
19 - fsl,fman-xmdio
[all …]
H A Dcavium-mdio.txt1 * System Management Interface (SMI) / MDIO
4 - compatible: One of:
6 "cavium,octeon-3860-mdio": Compatibility with all cn3XXX, cn5XXX
9 "cavium,thunder-8890-mdio": Compatibility with all cn8XXX SOCs.
11 - reg: The base address of the MDIO bus controller register bank.
13 - #address-cells: Must be <1>.
15 - #size-cells: Must be <0>. MDIO addresses have no size component.
17 Typically an MDIO bus might have several children.
20 mdio@1180000001800 {
21 compatible = "cavium,octeon-3860-mdio";
[all …]
H A Dmdio-mux-multiplexer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer consumer device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of MDIO mux when MDIO mux is defined as a consumer
19 - $ref: /schemas/net/mdio-mux.yaml#
23 const: mdio-mux-multiplexer
25 mux-controls:
[all …]
H A Dqcom,ipq4019-mdio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm IPQ40xx MDIO Controller
10 - Robert Marko <robert.marko@sartura.hr>
15 - enum:
16 - qcom,ipq4019-mdio
17 - qcom,ipq5018-mdio
19 - items:
[all …]
H A Dfsl,cpm-mdio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,cpm-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale CPM MDIO Device
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,pq1-fec-mdio
17 - fsl,cpm2-mdio-bitbang
18 - items:
[all …]
H A Dfsl,gianfar-mdio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,gianfar-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Gianfar (TSEC) MDIO Device
10 This binding describes the MDIO is a bus to which the PHY devices are
14 Some TSECs are associated with an internal Ten-Bit Interface (TBI) PHY. This
15 PHY is accessed through the local MDIO bus. These buses are defined similarly
16 to the mdio buses, except they are compatible with "fsl,gianfar-tbi". The TBI
22 - J. Neuschäfer <j.ne@posteo.net>
[all …]
H A Drealtek,rtl9301-mdio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/realtek,rtl9301-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek RTL9300 MDIO Controller
10 - Chris Packham <chris.packham@alliedtelesis.co.nz>
15 - items:
16 - enum:
17 - realtek,rtl9302b-mdio
18 - realtek,rtl9302c-mdio
[all …]
H A Dhisilicon-hns-mdio.txt1 Hisilicon MDIO bus controller
4 - compatible: can be one of:
5 "hisilicon,hns-mdio"
6 "hisilicon,mdio"
7 "hisilicon,hns-mdio" is recommended to be used for hip05 and later SOCs,
8 while "hisilicon,mdio" is optional for backwards compatibility only on
10 - reg: The base address of the MDIO bus controller register bank.
11 - #address-cells: Must be <1>.
12 - #size-cells: Must be <0>. MDIO addresses have no size component.
14 Typically an MDIO bus might have several children.
[all …]
H A Damlogic,gxl-mdio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/amlogic,gxl-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic GXL MDIO bus multiplexer
10 - Jerome Brunet <jbrunet@baylibre.com>
13 This is a special case of a MDIO bus multiplexer. It allows to choose between
14 the internal mdio bus leading to the embedded 10/100 PHY or the external
15 MDIO bus on the Amlogic GXL SoC family.
18 - $ref: mdio-mux.yaml#
[all …]
H A Dmdio-mux-mmioreg.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
[all …]
H A Damlogic,g12a-mdio-mux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/amlogic,g12a-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO bus multiplexer/glue of Amlogic G12a SoC family
10 This is a special case of a MDIO bus multiplexer. It allows to choose between
11 the internal mdio bus leading to the embedded 10/100 PHY or the external
12 MDIO bus.
15 - Neil Armstrong <neil.armstrong@linaro.org>
18 - $ref: mdio-mux.yaml#
[all …]
H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO Bus Common Properties
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
15 These are generic properties that can apply to any MDIO bus. Any
16 MDIO bus must have a list of child nodes, one per device on the
[all …]
H A Dbrcm,bcm6368-mdio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/brcm,bcm6368-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6368 MDIO bus multiplexer
10 - Álvaro Fernández Rojas <noltari@gmail.com>
13 This MDIO bus multiplexer defines buses that could be internal as well as
15 properties as well to generate desired MDIO transaction on appropriate bus.
18 - $ref: mdio-mux.yaml#
22 const: brcm,bcm6368-mdio-mux
[all …]
H A Dmdio-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO on GPIOs
10 - Andrew Lunn <andrew@lunn.ch>
11 - Heiner Kallweit <hkallweit1@gmail.com>
12 - Russell King <linux@armlinux.org.uk>
15 - $ref: mdio.yaml#
20 - virtual,mdio-gpio
[all …]
H A Daspeed,ast2600-mdio.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later
3 ---
4 $id: http://devicetree.org/schemas/net/aspeed,ast2600-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ASPEED AST2600 MDIO Controller
10 - Andrew Jeffery <andrew@aj.id.au>
13 The ASPEED AST2600 MDIO controller is the third iteration of ASPEED's MDIO
18 - $ref: mdio.yaml#
22 const: aspeed,ast2600-mdio
26 description: The register range of the MDIO controller instance
[all …]
H A Dqca,ar71xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Oleksij Rempel <o.rempel@pengutronix.de>
18 - items:
19 - enum:
20 - qca,ar7100-eth # Atheros AR7100
21 - qca,ar7240-eth # Atheros AR7240
22 - qca,ar7241-eth # Atheros AR7241
[all …]
/linux/drivers/net/mdio/
H A Dmdio-mvusb.c1 // SPDX-License-Identifier: GPL-2.0
9 #define USB_MARVELL_VID 0x1286
12 { USB_DEVICE(USB_MARVELL_VID, 0x1fa4) },
27 struct mii_bus *mdio; member
32 static int mvusb_mdio_read(struct mii_bus *mdio, int dev, int reg) in mvusb_mdio_read() argument
34 struct mvusb_mdio *mvusb = mdio->priv; in mvusb_mdio_read()
37 mvusb->buf[MVUSB_CMD_ADDR] = cpu_to_le16(0xa400 | (dev << 5) | reg); in mvusb_mdio_read()
39 err = usb_bulk_msg(mvusb->udev, usb_sndbulkpipe(mvusb->udev, 2), in mvusb_mdio_read()
40 mvusb->buf, 6, &alen, 100); in mvusb_mdio_read()
44 err = usb_bulk_msg(mvusb->udev, usb_rcvbulkpipe(mvusb->udev, 6), in mvusb_mdio_read()
[all …]
H A Dacpi_mdio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ACPI helpers for the MDIO (Ethernet PHY) API
19 MODULE_DESCRIPTION("ACPI MDIO bus (Ethernet PHY) accessors");
22 * __acpi_mdiobus_register - Register mii_bus and create PHYs from the ACPI ASL.
23 * @mdio: pointer to mii_bus structure
24 * @fwnode: pointer to fwnode of MDIO bus. This fwnode is expected to represent
25 * @owner: module owning this @mdio object.
26 * an ACPI device object corresponding to the MDIO bus and its children are
32 int __acpi_mdiobus_register(struct mii_bus *mdio, struct fwnode_handle *fwnode, in __acpi_mdiobus_register() argument
40 mdio->phy_mask = GENMASK(31, 0); in __acpi_mdiobus_register()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
H A Dfsl-lx2162a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2162a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "LTM4619-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
/linux/drivers/net/ethernet/hisilicon/
H A Dhns_mdio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014-2015 Hisilicon Limited.
23 #define MDIO_DRV_NAME "Hi-HNS_MDIO"
38 u8 __iomem *vbase; /* mdio reg base address */
43 /* mdio reg */
44 #define MDIO_COMMAND_REG 0x0
45 #define MDIO_ADDR_REG 0x4
46 #define MDIO_WDATA_REG 0x8
47 #define MDIO_RDATA_REG 0xc
48 #define MDIO_STA_REG 0x10
[all …]
/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet_mdio.c1 // SPDX-License-Identifier: GPL-2.0
3 * MDIO bus driver for the Xilinx Axi Ethernet device
6 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
7 * Copyright (c) 2010 - 2011 PetaLogix
9 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
24 * axienet_mdio_wait_until_ready - MDIO wait function
27 * Return : 0 on success, Negative value on errors
29 * Wait till MDIO interface is ready to accept a new transaction.
41 * axienet_mdio_mdc_enable - MDIO MDC enable function
44 * Enable the MDIO MDC. Called prior to a read/write operation
[all …]
/linux/drivers/net/ethernet/freescale/
H A Dfsl_pq_mdio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
9 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
34 #define MIIMIND_BUSY 0x00000001
35 #define MIIMIND_NOTVALID 0x00000004
36 #define MIIMCFG_INIT_VALUE 0x00000007
37 #define MIIMCFG_RESET 0x80000000
39 #define MII_READ_COMMAND 0x00000001
52 u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/
53 u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/
[all …]
/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-6352.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 struct mdio_device mdio; member
43 mutex_lock(&mpcs->mdio.bus->mdio_lock); in marvell_c22_pcs_set_fiber_page()
45 err = __mdiodev_read(&mpcs->mdio, MII_MARVELL_PHY_PAGE); in marvell_c22_pcs_set_fiber_page()
46 if (err < 0) { in marvell_c22_pcs_set_fiber_page()
47 dev_err(mpcs->mdio.dev.parent, in marvell_c22_pcs_set_fiber_page()
49 mpcs->name, ERR_PTR(err)); in marvell_c22_pcs_set_fiber_page()
55 err = __mdiodev_write(&mpcs->mdio, MII_MARVELL_PHY_PAGE, in marvell_c22_pcs_set_fiber_page()
58 dev_err(mpcs->mdio.dev.parent, in marvell_c22_pcs_set_fiber_page()
60 mpcs->name, ERR_PTR(err)); in marvell_c22_pcs_set_fiber_page()
[all …]
/linux/drivers/net/usb/
H A Dax88172a.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
12 * Copyright (c) 2002-2003 TiVo Inc.
19 struct mii_bus *mdio; member
31 struct phy_device *phydev = netdev->phydev; in ax88172a_adjust_link()
33 struct ax88172a_private *priv = dev->driver_priv; in ax88172a_adjust_link()
34 u16 mode = 0; in ax88172a_adjust_link()
36 if (phydev->link) { in ax88172a_adjust_link()
39 if (phydev->duplex == DUPLEX_HALF) in ax88172a_adjust_link()
42 if (phydev->speed != SPEED_100) in ax88172a_adjust_link()
[all …]

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