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/linux/arch/alpha/lib/
H A Dev6-memset.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memset.S
8 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
13 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
15 * E - either cluster
16 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
23 * A future enhancement might be to put in a byte store loop for really
25 * a win in the kernel would depend upon the contextual usage.
43 .frame $30,0,$26,0
[all …]
H A Dev6-memcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memcpy.S
4 * 21264 version by Rick Gorton <rick.gorton@alpha-processor.com>
8 * - memory accessed as aligned quadwords only
9 * - uses bcmpge to compare 8 bytes in parallel
14 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
16 * E - either cluster
17 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
18 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
21 * $1,$2, - scratch
[all …]
H A Dev6-csum_ipv6_magic.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
29 * Swap <proto> (takes form 0xaabb)
31 * 0xbbaa0000 00000000
32 * Then turn it back into a sign extended 32-bit item
[all …]
H A Dev6-copy_user.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-copy_user.S
5 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
10 * This is essentially the same as "memcpy()", but with a few twists.
11 * Notably, we have to make sure that $0 is always up-to-date and
13 * only _after_ a successful copy). There is also some rather minor
19 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
21 * E - either cluster
22 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
23 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
[all …]
H A Dev6-stxncpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-stxncpy.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@api-networks.com>
6 * Copy no more than COUNT bytes of the null-terminated string from
29 * Furthermore, v0, a3-a5, t11, and $at are untouched.
34 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
36 * E - either cluster
37 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
38 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
49 /* There is a problem with either gdb (as of 4.16) or gas (as of 2.7) that
[all …]
H A Dev6-stxcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-stxcpy.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
6 * Copy a null-terminated string from SRC to DST.
21 * Furthermore, v0, a3-a5, t11, and t12 are untouched.
26 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
28 * E - either cluster
29 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
30 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
41 /* There is a problem with either gdb (as of 4.16) or gas (as of 2.7) that
[all …]
/linux/arch/powerpc/crypto/
H A Daes-tab-4k.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * crypto/aes_generic.c and are designed to be simply accessed by a combination
11 * of rlwimi/lwz instructions with a minimum of table registers (usually only
14 * instructions. E.g. evldw, evlwwsplat, ...
16 * For the safety-conscious it has to be noted that they might be vulnerable
19 * This is a quite good tradeoff for low power devices (e.g. routers) without
25 #define R(a, b, c, d) \ argument
26 0x##a##b##c##d, 0x##d##a##b##c, 0x##c##d##a##b, 0x##b##c##d##a
32 /* encryption table, same as crypto_ft_tab in crypto/aes-generic.c */
33 .long R(c6, 63, 63, a5), R(f8, 7c, 7c, 84)
[all …]
/linux/tools/testing/selftests/hid/tests/
H A Dtest_multitouch.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
20 KERNEL_MODULE = ("hid-multitouch", "hid_multitouch")
28 "NOT_SEEN_MEANS_UP": BIT(0),
35 "CONFIDENCE": BIT(7),
66 self.azimuth = 0
74 super().__init__(0, x, y)
80 self.twist = 0
91 Usage Page (0xff00)
92 Usage (0xc5)
[all …]
H A Dtest_tablet.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
34 """Represents whether a button is pressed on the stylus"""
43 https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/windows-pen-states
66 def from_evdev(cls, evdev, test_button) -> "PenState":
99 ) -> "PenState":
146 def valid_transitions(self) -> Tuple["PenState", ...]:
206 def historically_tolerated_transitions(self) -> Tuple["PenState", ...]:
207 """Following the state machine in the URL above, with a couple of addition
208 for skipping the in-range state, due to historical reasons.
[all …]
/linux/arch/m68k/fpsp040/
H A Dtbldo.S10 | index with a 10-bit index, with the first
11 | 7 bits the opcode, and the remaining 3
46 | instruction ;opcode-stag Notes
49 .long smovcr |$00-0 fmovecr all
50 .long smovcr |$00-1 fmovecr all
51 .long smovcr |$00-2 fmovecr all
52 .long smovcr |$00-3 fmovecr all
53 .long smovcr |$00-4 fmovecr all
54 .long smovcr |$00-5 fmovecr all
55 .long smovcr |$00-6 fmovecr all
[all …]
/linux/arch/x86/crypto/
H A Dsha1_avx2_x86_64_asm.S2 * Implement fast SHA-1 with AVX2 instructions. (x86_64)
4 * This file is provided under a dual BSD/GPLv2 license. When using or
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
47 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
59 * SHA-1 implementation with Intel(R) AVX2 instruction set extensions.
62 *Visit http://software.intel.com/en-us/articles/
63 *and refer to improving-the-performance-of-the-secure-hash-algorithm-1/
65 *Updates 20-byte SHA-1 record at start of 'state', from 'input', for
66 *even number of 'blocks' consecutive 64-byte blocks.
100 .set A, REG_A define
[all …]
H A Dsha512-avx2-asm.S2 # Implement fast SHA-512 with AVX2 instructions. (x86_64)
12 # This software is available to you under a choice of one of two
22 # - Redistributions of source code must retain the above
26 # - Redistributions in binary form must reproduce the above
33 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 # This code is described in an Intel White-Paper:
43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
49 # This code schedules 1 blocks at a time, with 4 lanes per block
82 e = %rdx define
87 a = %rax define
[all …]
H A Dsha256-avx-asm.S2 # Implement fast SHA-256 with AVX1 instructions. (x86_64)
11 # This software is available to you under a choice of one of two
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 # This code is described in an Intel White-Paper:
41 # "Fast SHA-256 Implementations on Intel Architecture Processors"
47 # This code schedules 1 block at a time, with 4 lanes per block
59 # Add reg to mem using reg-mem add and store
67 shld $(32-(\p1)), \p2, \p2
[all …]
H A Dsha256-ssse3-asm.S2 # Implement fast SHA-256 with SSSE3 instructions. (x86_64)
11 # This software is available to you under a choice of one of two
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 # This code is described in an Intel White-Paper:
42 # "Fast SHA-256 Implementations on Intel Architecture Processors"
58 # Add reg to mem using reg-mem add and store
87 SHUF_00BA = %xmm10 # shuffle xBxA -> 00BA
88 SHUF_DC00 = %xmm11 # shuffle xDxC -> DC00
[all …]
H A Dsha256-avx2-asm.S2 # Implement fast SHA-256 with AVX2 instructions. (x86_64)
11 # This software is available to you under a choice of one of two
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 # This code is described in an Intel White-Paper:
42 # "Fast SHA-256 Implementations on Intel Architecture Processors"
48 # This code schedules 2 blocks at a time, with 4 lanes per block
60 # Add reg to mem using reg-mem add and store
87 SHUF_00BA = %ymm10 # shuffle xBxA -> 00BA
[all …]
H A Dsha512-ssse3-asm.S2 # Implement fast SHA-512 with SSSE3 instructions. (x86_64)
12 # This software is available to you under a choice of one of two
22 # - Redistributions of source code must retain the above
26 # - Redistributions in binary form must reproduce the above
33 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 # This code is described in an Intel White-Paper:
43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
79 frame_W = 0
103 # Rotate symbols a..h right
119 mov e_64, tmp0 # tmp = e
[all …]
/linux/arch/arm/crypto/
H A Dsha1-armv4-large.S2 @ SPDX-License-Identifier: GPL-2.0
23 @ Size/performance trade-off
28 @ armv4-small 392/+29% 1958/+64% 2250/+96%
29 @ armv4-compact 740/+89% 1552/+26% 1840/+22%
30 @ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
42 @ i-cache availability, branch penalties, etc.
44 @ diverse as ARM ones: e.g., there are only two arithmetic
49 @ [***] which is also ~35% better than compiler generated code. Dual-
55 @ Rescheduling for dual-issue pipeline resulted in 13% improvement on
61 @ Profiler-assisted and platform-specific optimization resulted in 10%
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32mp15-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
9 /omit-if-no-ref/
10 adc1_ain_pins_a: adc1-ain-0 {
14 <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */
15 <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */
17 <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1_INP15 */
21 /omit-if-no-ref/
22 adc1_in6_pins_a: adc1-in6-0 {
[all …]
H A Dstm32mp13-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
9 /omit-if-no-ref/
10 adc1_pins_a: adc1-pins-0 {
12 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
16 /omit-if-no-ref/
17 adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
20 <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
24 /omit-if-no-ref/
[all …]
/linux/lib/crypto/
H A Dsha256.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SHA-256, as specified in
4 * http://csrc.nist.gov/groups/STM/cavp/documents/shs/sha256-384-512.pdf
6 * SHA-256 code by Jean-Luc Cooke <jlcooke@certainkey.com>.
8 * Copyright (c) Jean-Luc Cooke <jlcooke@certainkey.com>
21 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5,
22 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5,
23 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
24 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174,
25 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc,
[all …]
/linux/crypto/
H A Dsm3.c1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * SM3 secure hash, as specified by OSCCA GM/T 0004-2012 SM3 and described
4 * at https://datatracker.ietf.org/doc/html/draft-sca-cfrg-sm3-02
7 * Copyright (C) 2017 Gilad Ben-Yossef <gilad@benyossef.com>
16 0x79cc4519, 0xf3988a32, 0xe7311465, 0xce6228cb,
17 0x9cc45197, 0x3988a32f, 0x7311465e, 0xe6228cbc,
18 0xcc451979, 0x988a32f3, 0x311465e7, 0x6228cbce,
19 0xc451979c, 0x88a32f39, 0x11465e73, 0x228cbce6,
20 0x9d8a7a87, 0x3b14f50f, 0x7629ea1e, 0xec53d43c,
21 0xd8a7a879, 0xb14f50f3, 0x629ea1e7, 0xc53d43ce,
[all …]
/linux/sound/pci/hda/
H A Dhda_eld.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 CEA_EDID_VER_NONE = 0,
36 "2-reserved",
37 "3-reserved"
41 AUDIO_CODING_TYPE_REF_STREAM_HEADER = 0,
48 AUDIO_CODING_TYPE_DTS = 7,
64 AUDIO_CODING_XTYPE_HE_REF_CT = 0,
72 /* 0 */ "undefined",
74 /* 2 */ "AC-3",
78 /* 6 */ "AAC-LC",
[all …]
/linux/Documentation/trace/
H A Dtracepoint-analysis.rst14 taken in conjunction with other tracepoints to build a "Big Picture" of
15 what is going on within the system. There are a large number of methods for
27 ----------------------
32 $ find /sys/kernel/tracing/events -type d
34 will give a fair indication of the number of events available.
37 ----------------------------------------
40 are available with the perf tool. Getting a list of available events is a
55 3.1 System-Wide Event Enabling
56 ------------------------------
58 See Documentation/trace/events.rst for a proper description on how events
[all …]
/linux/Documentation/ABI/stable/
H A Dsysfs-class-tpm4 Contact: linux-integrity@vger.kernel.org
5 Description: The device/ directory under a specific TPM instance exposes
12 Contact: linux-integrity@vger.kernel.org
13 Description: The "active" property prints a '1' if the TPM chip is accepting
16 visible to the OS, but will only accept a restricted set of
24 Contact: linux-integrity@vger.kernel.org
32 Contact: linux-integrity@vger.kernel.org
37 Manufacturer: 0x53544d20
41 Manufacturer is a hex dump of the 4 byte manufacturer info
42 space in a TPM. TCG version shows the TCG TPM spec level that
[all …]
/linux/Documentation/admin-guide/
H A Dlcd-panel-cgram.rst6 characters 0 to 7. The escape code to define a new character is
7 '\e[LG' followed by one digit from 0 to 7, representing the character
8 number, and up to 8 couples of hex digits terminated by a semi-colon
9 (';'). Each couple of digits represents a line, with 1-bits for each
11 top of the character to the bottom. On a 5x7 matrix, only the 5 lower
12 bits of the 7 first bytes are used for each character. If the string
16 printf "\e[LG0010101050D1F0C04;" => 0 = [enter]
17 printf "\e[LG1040E1F0000000000;" => 1 = [up]
18 printf "\e[LG2000000001F0E0400;" => 2 = [down]
19 printf "\e[LG3040E1F001F0E0400;" => 3 = [up-down]
[all …]

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