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2 # Implement fast SHA-512 with SSSE3 instructions. (x86_64)
12 # This software is available to you under a choice of one of two
22 # - Redistributions of source code must retain the above
26 # - Redistributions in binary form must reproduce the above
33 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 # This code is described in an Intel White-Paper:
43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
78 frame_W = 0
102 # Rotate symbols a..h right
118 mov e_64, tmp0 # tmp = e
120 ror $23, tmp0 # 41 # tmp = e ror 23
121 and e_64, T1 # T1 = (f ^ g) & e
122 xor e_64, tmp0 # tmp = (e ror 23) ^ e
123 xor g_64, T1 # T1 = ((f ^ g) & e) ^ g = CH(e,f,g)
126 ror $4, tmp0 # 18 # tmp = ((e ror 23) ^ e) ror 4
127 xor e_64, tmp0 # tmp = (((e ror 23) ^ e) ror 4) ^ e
128 mov a_64, T2 # T2 = a
129 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h
130 ror $14, tmp0 # 14 # tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e)
131 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
132 mov a_64, tmp0 # tmp = a
133 xor c_64, T2 # T2 = a ^ c
134 and c_64, tmp0 # tmp = a & c
135 and b_64, T2 # T2 = (a ^ c) & b
136 xor tmp0, T2 # T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c)
137 mov a_64, tmp0 # tmp = a
138 ror $5, tmp0 # 39 # tmp = a ror 5
139 xor a_64, tmp0 # tmp = (a ror 5) ^ a
140 add T1, d_64 # e(next_state) = d + T1
141 ror $6, tmp0 # 34 # tmp = ((a ror 5) ^ a) ror 6
142 xor a_64, tmp0 # tmp = (((a ror 5) ^ a) ror 6) ^ a
143 lea (T1, T2), h_64 # a(next_state) = T1 + Maj(a,b,c)
144 ror $28, tmp0 # 28 # tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a)
145 add tmp0, h_64 # a(next_state) = T1 + Maj(a,b,c) S0(a)
151 # Compute rounds t-2 and t-1
154 # Two rounds are computed based on the values for K[t-2]+W[t-2] and
155 # K[t-1]+W[t-1] which were previously stored at WK_2 by the message
161 # the first of a pair of QWORDS.
162 # Eg. XMM2=W[t-2] really means XMM2={W[t-2]|W[t-1]}
164 # stitched to take advantage of instruction-level parallelism.
170 idx = \rnd -2
171 movdqa W_t(idx), %xmm2 # XMM2 = W[t-2]
174 movdqa %xmm2, %xmm0 # XMM0 = W[t-2]
178 idx = \rnd - 15
179 movdqu W_t(idx), %xmm5 # XMM5 = W[t-15]
182 movdqa %xmm5, %xmm3 # XMM3 = W[t-15]
185 psrlq $61-19, %xmm0 # XMM0 = W[t-2] >> 42
188 psrlq $(8-7), %xmm3 # XMM3 = W[t-15] >> 1
191 pxor %xmm2, %xmm0 # XMM0 = (W[t-2] >> 42) ^ W[t-2]
194 pxor %xmm5, %xmm3 # XMM3 = (W[t-15] >> 1) ^ W[t-15]
197 psrlq $(19-6), %xmm0 # XMM0 = ((W[t-2]>>42)^W[t-2])>>13
200 psrlq $(7-1), %xmm3 # XMM3 = ((W[t-15]>>1)^W[t-15])>>6
203 pxor %xmm2, %xmm0 # XMM0 = (((W[t-2]>>42)^W[t-2])>>13)^W[t-2]
206 pxor %xmm5, %xmm3 # XMM3 = (((W[t-15]>>1)^W[t-15])>>6)^W[t-15]
209 psrlq $6, %xmm0 # XMM0 = ((((W[t-2]>>42)^W[t-2])>>13)^W[t-2])>>6
212 psrlq $1, %xmm3 # XMM3 = (((W[t-15]>>1)^W[t-15])>>6)^W[t-15]>>1
215 movdqa %xmm2, %xmm1 # XMM1 = W[t-2]
218 movdqa %xmm5, %xmm4 # XMM4 = W[t-15]
221 psllq $(64-19)-(64-61) , %xmm1 # XMM1 = W[t-2] << 42
225 psllq $(64-1)-(64-8), %xmm4 # XMM4 = W[t-15] << 7
228 pxor %xmm2, %xmm1 # XMM1 = (W[t-2] << 42)^W[t-2]
231 pxor %xmm5, %xmm4 # XMM4 = (W[t-15]<<7)^W[t-15]
234 psllq $(64-61), %xmm1 # XMM1 = ((W[t-2] << 42)^W[t-2])<<3
237 psllq $(64-8), %xmm4 # XMM4 = ((W[t-15]<<7)^W[t-15])<<56
240 pxor %xmm1, %xmm0 # XMM0 = s1(W[t-2])
243 idx = \rnd - 7
244 movdqu W_t(idx), %xmm1 # XMM1 = W[t-7]
246 pxor %xmm4, %xmm3 # XMM3 = s0(W[t-15])
248 paddq %xmm3, %xmm0 # XMM0 = s1(W[t-2]) + s0(W[t-15])
250 idx =\rnd-16
251 paddq W_t(idx), %xmm0 # XMM0 = s1(W[t-2]) + s0(W[t-15]) + W[t-16]
253 paddq %xmm1, %xmm0 # XMM0 = s1(W[t-2]) + W[t-7] + s0(W[t-15]) + W[t-16]
289 and $~(0x20 - 1), %rsp
294 mov DIGEST(0), a_64
301 mov DIGEST(7), h_64
303 t = 0
319 SHA512_Round t-2 # Round t-2
322 SHA512_Round t-1 # Round t-1
329 SHA512_Round t-2
330 SHA512_Round t-1
336 add a_64, DIGEST(0)
343 add h_64, DIGEST(7)
369 # Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb.
371 .octa 0x08090a0b0c0d0e0f0001020304050607
373 # Mergeable 640-byte rodata section. This allows linker to merge the table
374 # with other, exactly the same 640-byte fragment of another rodata section
380 .quad 0x428a2f98d728ae22,0x7137449123ef65cd
381 .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
382 .quad 0x3956c25bf348b538,0x59f111f1b605d019
383 .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
384 .quad 0xd807aa98a3030242,0x12835b0145706fbe
385 .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
386 .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
387 .quad 0x9bdc06a725c71235,0xc19bf174cf692694
388 .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
389 .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
390 .quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
391 .quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
392 .quad 0x983e5152ee66dfab,0xa831c66d2db43210
393 .quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
394 .quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
395 .quad 0x06ca6351e003826f,0x142929670a0e6e70
396 .quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
397 .quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
398 .quad 0x650a73548baf63de,0x766a0abb3c77b2a8
399 .quad 0x81c2c92e47edaee6,0x92722c851482353b
400 .quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
401 .quad 0xc24b8b70d0f89791,0xc76c51a30654be30
402 .quad 0xd192e819d6ef5218,0xd69906245565a910
403 .quad 0xf40e35855771202a,0x106aa07032bbd1b8
404 .quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
405 .quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
406 .quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
407 .quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
408 .quad 0x748f82ee5defb2fc,0x78a5636f43172f60
409 .quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
410 .quad 0x90befffa23631e28,0xa4506cebde82bde9
411 .quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
412 .quad 0xca273eceea26619c,0xd186b8c721c0c207
413 .quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
414 .quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
415 .quad 0x113f9804bef90dae,0x1b710b35131c471b
416 .quad 0x28db77f523047d84,0x32caab7b40c72493
417 .quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
418 .quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
419 .quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817