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/linux/fs/nls/
H A Dnls_ucs2_utils.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 MODULE_DESCRIPTION("NLS UCS-2");
26 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 000-00f */
27 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 010-01f */
28 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 020-02f */
29 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 030-03f */
30 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 040-04f */
31 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 050-05f */
32 0, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
33 -32, -32, -32, -32, -32, /* 060-06f */
[all …]
/linux/arch/sh/drivers/pci/
H A Dpcie-sh7786.h1 /* SPDX-License-Identifier: GPL-2.0
3 * SH7786 PCI-Express controller definitions.
11 /* PCIe bus-0(x4) on SH7786 */ // Rev1.171
12 #define SH4A_PCIE_SPW_BASE 0xFE000000 /* spw config address for controller 0 */
13 #define SH4A_PCIE_SPW_BASE1 0xFE200000 /* spw config address for controller 1 (Rev1.14)*/
14 #define SH4A_PCIE_SPW_BASE2 0xFCC00000 /* spw config address for controller 2 (Rev1.171)*/
15 #define SH4A_PCIE_SPW_BASE_LEN 0x00080000
17 #define SH4A_PCI_CNFG_BASE 0xFE040000 /* pci config address for controller 0 */
18 #define SH4A_PCI_CNFG_BASE1 0xFE240000 /* pci config address for controller 1 (Rev1.14)*/
19 #define SH4A_PCI_CNFG_BASE2 0xFCC40000 /* pci config address for controller 2 (Rev1.171)*/
[all …]
/linux/arch/x86/include/asm/
H A Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define NCAPINTS 22 /* N 32-bit words worth of info */
9 #define NBUGINTS 2 /* N 32-bit bug flags */
17 * please update the table in kernel/cpu/cpuid-deps.c as well.
20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
21 #define X86_FEATURE_FPU ( 0*32+ 0) /* "fpu" Onboard FPU */
22 #define X86_FEATURE_VME ( 0*32+ 1) /* "vme" Virtual Mode Extensions */
23 #define X86_FEATURE_DE ( 0*32+ 2) /* "de" Debugging Extensions */
24 #define X86_FEATURE_PSE ( 0*32+ 3) /* "pse" Page Size Extensions */
25 #define X86_FEATURE_TSC ( 0*32+ 4) /* "tsc" Time Stamp Counter */
[all …]
H A Dvmxfeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define NVMXINTS 5 /* N 32-bit words worth of info */
16 /* Pin-Based VM-Execution Controls, EPT/VPID, APIC and VM-Functions, word 0 */
17 #define VMX_FEATURE_INTR_EXITING ( 0*32+ 0) /* VM-Exit on vectored interrupts */
18 #define VMX_FEATURE_NMI_EXITING ( 0*32+ 3) /* VM-Exit on NMIs */
19 #define VMX_FEATURE_VIRTUAL_NMIS ( 0*32+ 5) /* "vnmi" NMI virtualization */
20 #define VMX_FEATURE_PREEMPTION_TIMER ( 0*32+ 6) /* "preemption_timer" VMX Preemption Timer */
21 #define VMX_FEATURE_POSTED_INTR ( 0*32+ 7) /* "posted_intr" Posted Interrupts */
23 /* EPT/VPID features, scattered to bits 16-23 */
24 #define VMX_FEATURE_INVVPID ( 0*32+ 16) /* "invvpid" INVVPID is supported */
[all …]
/linux/tools/arch/x86/include/asm/
H A Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define NCAPINTS 22 /* N 32-bit words worth of info */
9 #define NBUGINTS 2 /* N 32-bit bug flags */
17 * please update the table in kernel/cpu/cpuid-deps.c as well.
20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
21 #define X86_FEATURE_FPU ( 0*32+ 0) /* "fpu" Onboard FPU */
22 #define X86_FEATURE_VME ( 0*32+ 1) /* "vme" Virtual Mode Extensions */
23 #define X86_FEATURE_DE ( 0*32+ 2) /* "de" Debugging Extensions */
24 #define X86_FEATURE_PSE ( 0*32+ 3) /* "pse" Page Size Extensions */
25 #define X86_FEATURE_TSC ( 0*32+ 4) /* "tsc" Time Stamp Counter */
[all …]
/linux/drivers/staging/rtl8723bs/hal/
H A DHalHWImg8723B_RF.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
17 ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */ in CheckPositive()
18 ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */ in CheckPositive()
19 ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ in CheckPositive()
20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
24 pDM_Odm->CutVersion << 24 | in CheckPositive()
25 pDM_Odm->SupportPlatform << 16 | in CheckPositive()
26 pDM_Odm->PackageType << 12 | in CheckPositive()
[all …]
/linux/lib/crypto/powerpc/
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
76 mflr 0
77 std 0, 16(1)
78 stdu 1,-752(1)
100 SAVE_VRS 20, 0, 9
102 SAVE_VRS 22, 32, 9
135 RESTORE_VRS 20, 0, 9
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/linux/tools/testing/selftests/gpio/
H A Dgpio-mockup.sh1 #!/bin/bash -efu
2 # SPDX-License-Identifier: GPL-2.0
5 #0: success
7 #4: skip test - including run as non-root user
9 BASE=${0%/*}
13 module="gpio-mockup"
29 echo "$0 [-frv] [-t type]"
30 echo "-f: full test (minimal set run by default)"
31 echo "-r: test random lines as well as fence posts"
32 echo "-t: interface type:"
[all …]
/linux/arch/powerpc/kernel/
H A Dcpu_specs_book3s_32.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 .pvr_mask = 0xffff0000,
13 .pvr_value = 0x00030000,
17 .mmu_features = 0,
18 .icache_bsize = 32,
19 .dcache_bsize = 32,
25 .pvr_mask = 0xffff0000,
26 .pvr_value = 0x00060000,
30 .mmu_features = 0,
31 .icache_bsize = 32,
[all …]
H A Dcpu_specs_44x.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 .pvr_mask = 0xf0000fff,
12 .pvr_value = 0x40000850,
17 .icache_bsize = 32,
18 .dcache_bsize = 32,
22 { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
23 .pvr_mask = 0xf0000fff,
24 .pvr_value = 0x40000858,
29 .icache_bsize = 32,
30 .dcache_bsize = 32,
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 /delete-node/ &cpu0_opp_table;
10 /delete-node/ &cpu4_opp_table;
13 cpu0_opp_table: opp-table-cpu0 {
14 compatible = "operating-points-v2";
15 opp-shared;
17 opp-300000000 {
18 opp-hz = /bits/ 64 <300000000>;
19 opp-peak-kBps = <(300000 * 32)>;
21 opp-403200000 {
[all …]
/linux/tools/testing/selftests/bpf/progs/
H A Dverifier_subreg.c1 // SPDX-License-Identifier: GPL-2.0
8 /* This file contains sub-register zero extension checks for insns defining
9 * sub-registers, meaning:
10 * - All insns under BPF_ALU class. Their BPF_ALU32 variants or narrow width
11 * forms (BPF_END) could define sub-registers.
12 * - Narrow direct loads, BPF_B/H/W | BPF_LDX.
13 * - BPF_LD is not exposed to JIT back-ends, so no need for testing.
15 * "get_prandom_u32" is used to initialize low 32-bit of some registers to
16 * prevent potential optimizations done by verifier or JIT back-ends which could
23 __success __success_unpriv __retval(0)
[all …]
H A Datomics.c1 // SPDX-License-Identifier: GPL-2.0
13 __u32 pid = 0;
16 __u64 add64_result = 0;
18 __u32 add32_result = 0;
19 __u64 add_stack_value_copy = 0;
20 __u64 add_stack_result = 0;
26 if (pid != (bpf_get_current_pid_tgid() >> 32)) in add()
27 return 0; in add()
38 return 0; in add()
42 __s64 sub64_result = 0;
[all …]
/linux/drivers/scsi/qla2xxx/
H A Dqla_dbg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (c) 2003-2014 QLogic Corporation
17 __be16 mailbox_reg[32];
18 __be16 resp_dma_reg[32];
32 __be16 risc_ram[0xf800];
33 __be16 stack_ram[0x1000];
40 __be16 mailbox_reg[32];
54 __be16 risc_ram[0xf000];
60 __be32 host_reg[32];
62 __be16 mailbox_reg[32];
[all …]
/linux/arch/powerpc/boot/
H A Ddiv64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Divide a 64-bit unsigned number by a 32-bit unsigned number.
4 * This routine assumes that the top 32 bits of the dividend are
5 * non-zero to start with.
7 * the 64-bit quotient, and r4 contains the divisor.
16 lwz r5,0(r3) # get the dividend into r5/r6
19 li r7,0
20 li r8,0
26 1: mr r11,r5 # here dividend.hi != 0
27 andis. r0,r5,0xc000
[all …]
/linux/drivers/gpu/drm/imagination/
H A Dpvr_stream_defs.c1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
20 PVR_STREAM_DEF_SET(owner, member, PVR_STREAM_SIZE_ ## member_size, 0, PVR_FEATURE_NONE)
23 PVR_STREAM_DEF_SET(owner, member, PVR_STREAM_SIZE_ ## member_size, 0, feature)
26 PVR_STREAM_DEF_SET(owner, member, PVR_STREAM_SIZE_ ## member_size, 0, \
31 sizeof(((struct owner *)0)->member), PVR_FEATURE_NONE)
35 sizeof(((struct owner *)0)->member), feature)
39 sizeof(((struct owner *)0)->member), (feature) | PVR_FEATURE_NOT)
51 PVR_STREAM_DEF_FEATURE(rogue_fwif_cmd_geom, regs.vdm_draw_indirect1, 32,
53 PVR_STREAM_DEF(rogue_fwif_cmd_geom, regs.ppp_ctrl, 32),
54 PVR_STREAM_DEF(rogue_fwif_cmd_geom, regs.te_psg, 32),
[all …]
/linux/drivers/net/fddi/skfp/h/
H A Dskfbi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
34 #define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */
38 * Bank 0
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
[all …]
/linux/arch/x86/crypto/
H A Dsm4-aesni-avx2-asm_64.S1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SM4 Cipher Algorithm, AES-NI/AVX2 optimized.
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
7 * Copyright (C) 2018 Markku-Juhani O. Saarinen <mjos@iki.fi>
12 /* Based on SM4 AES-NI work by libgcrypt and Markku-Juhani O. Saarinen at:
61 /* Transpose four 32-bit words between 128-bit vector lanes. */
75 /* post-SubByte transform. */
85 /* post-SubByte transform. Note: x has been XOR'ed with mask4bit by
101 * Following four affine transform look-up tables are from work by
102 * Markku-Juhani O. Saarinen, at https://github.com/mjosaarinen/sm4ni
[all …]
H A Daria-aesni-avx2-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ARIA Cipher 32-way parallel algorithm (AVX2)
11 #include <asm/asm-offsets.h>
35 ( (((a0) & 1) << 0) | \
45 ( ((l7) << (0 * 8)) | \
186 /* load blocks to registers and apply pre-whitening */
192 vmovdqu (0 * 32)(rio), x0; \
193 vmovdqu (1 * 32)(rio), x1; \
194 vmovdqu (2 * 32)(rio), x2; \
195 vmovdqu (3 * 32)(rio), x3; \
[all …]
/linux/lib/crypto/arm/
H A Dchacha-neon-core.S11 * ChaCha20 256-bit cipher algorithm, RFC7539, x64 SSE3 functions
26 * (c) vrev32.16 (16-bit rotations only)
30 * ChaCha has 16, 12, 8, and 7-bit rotations. For the 12 and 7-bit rotations,
31 * the only choices are (a) and (b). We use (a) since it takes two-thirds the
32 * cycles of (b) on both Cortex-A7 and Cortex-A53.
34 * For the 16-bit rotation, we use vrev32.16 since it's consistently fastest
37 * For the 8-bit rotation, we use vtbl.8 + vtbl.8. On Cortex-A7, this sequence
42 * A disadvantage is that on Cortex-A53, the vtbl sequence is the same speed as
46 * CPUs, e.g. ~4.8% faster ChaCha20 on Cortex-A7.
57 * chacha_permute - permute one block
[all …]
/linux/lib/crc/s390/
H A Dcrc32le-vx.c1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of bitreflected CRC-32 checksums for IEEE 802.3 Ethernet
9 * This CRC-32 implementation algorithm is bitreflected and processes
10 * the least-significant bit first (Little-Endian).
18 #include "crc32-vx.h"
20 /* Vector register range containing CRC-32 constants */
29 * The CRC-32 constant block contains reduction constants to fold and
32 * For the CRC-32 variants, the constants are precomputed according to
35 * R1 = [(x4*128+32 mod P'(x) << 32)]' << 1
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8703b_tables.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
9 { 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200, },
10 { 0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200, },
11 { 0, 0, 0, 0x00000e00, 0xffffffff, 0x34363636, },
12 { 0, 0, 0, 0x00000e04, 0xffffffff, 0x28303234, },
13 { 0, 0, 0, 0x00000e10, 0xffffffff, 0x30343434, },
14 { 0, 0, 0, 0x00000e14, 0xffffffff, 0x26262830, },
19 /* Regd: FCC -> 0, ETSI -> 2, MKK -> 1
20 * Band: 2.4G -> 0, 5G -> 1
21 * Bandwidth (bw): 20M -> 0, 40M -> 1, 80M -> 2, 160M -> 3
[all …]
/linux/drivers/misc/mchp_pci1xxxx/
H A Dmchp_pci1xxxx_gpio.c1 // SPDX-License-Identifier: GPL-2.0
17 #define PCI_DEV_REV_OFFSET 0x08
18 #define PERI_GEN_RESET 0
19 #define OUT_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400)
20 #define INP_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x10)
21 #define OUT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x20)
22 #define INP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x30)
23 #define PULLUP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x40)
24 #define PULLDOWN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x50)
25 #define OPENDRAIN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x60)
[all …]
/linux/lib/raid6/
H A Drecov_avx2.c1 // SPDX-License-Identifier: GPL-2.0-only
22 const u8 x0f = 0x0f; in raid6_2data_recov_avx2()
24 p = (u8 *)ptrs[disks-2]; in raid6_2data_recov_avx2()
25 q = (u8 *)ptrs[disks-1]; in raid6_2data_recov_avx2()
32 ptrs[disks-2] = dp; in raid6_2data_recov_avx2()
35 ptrs[disks-1] = dq; in raid6_2data_recov_avx2()
42 ptrs[disks-2] = p; in raid6_2data_recov_avx2()
43 ptrs[disks-1] = q; in raid6_2data_recov_avx2()
46 pbmul = raid6_vgfmul[raid6_gfexi[failb-faila]]; in raid6_2data_recov_avx2()
53 asm volatile("vpbroadcastb %0, %%ymm7" : : "m" (x0f)); in raid6_2data_recov_avx2()
[all …]
/linux/Documentation/scsi/
H A Daic7xxx.rst1 .. SPDX-License-Identifier: GPL-2.0
5 Adaptec Aic7xxx Fast -> Ultra160 Family Manager Set v7.0
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
[all …]

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