Lines Matching +full:0 +full:- +full:32
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
76 mflr 0
77 std 0, 16(1)
78 stdu 1,-752(1)
100 SAVE_VRS 20, 0, 9
102 SAVE_VRS 22, 32, 9
135 RESTORE_VRS 20, 0, 9
137 RESTORE_VRS 22, 32, 9
187 ld 0, 16(1)
188 mtlr 0
193 xxlor 0, 32+25, 32+25
194 xxlor 32+25, 20, 20
195 vadduwm 0, 0, 4
204 vpermxor 12, 12, 0, 25
212 xxlor 32+25, 0, 0
230 xxlor 0, 32+25, 32+25
231 xxlor 32+25, 21, 21
240 xxlor 32+25, 0, 0
241 vadduwm 0, 0, 4
250 xxlor 0, 32+25, 32+25
251 xxlor 32+25, 22, 22
252 vpermxor 12, 12, 0, 25
260 xxlor 32+25, 0, 0
269 xxlor 0, 32+28, 32+28
270 xxlor 32+28, 23, 23
287 xxlor 32+28, 0, 0
290 xxlor 0, 32+25, 32+25
291 xxlor 32+25, 20, 20
292 vadduwm 0, 0, 5
301 vpermxor 15, 15, 0, 25
310 xxlor 32+25, 0, 0
328 xxlor 0, 32+25, 32+25
329 xxlor 32+25, 21, 21
338 xxlor 32+25, 0, 0
340 vadduwm 0, 0, 5
349 xxlor 0, 32+25, 32+25
350 xxlor 32+25, 22, 22
351 vpermxor 15, 15, 0, 25
359 xxlor 32+25, 0, 0
370 xxlor 0, 32+28, 32+28
371 xxlor 32+28, 23, 23
388 xxlor 32+28, 0, 0
393 vadduwm 0, 0, 4
397 vpermxor 12, 12, 0, 20
413 vadduwm 0, 0, 4
417 vpermxor 12, 12, 0, 22
435 vadduwm 0, 0, 5
439 vpermxor 15, 15, 0, 20
455 vadduwm 0, 0, 5
459 vpermxor 15, 15, 0, 22
479 xxmrghw 10, 32+\a0, 32+\a1 # a0, a1, b0, b1
480 xxmrghw 11, 32+\a2, 32+\a3 # a2, a3, b2, b3
481 xxmrglw 12, 32+\a0, 32+\a1 # c0, c1, d0, d1
482 xxmrglw 13, 32+\a2, 32+\a3 # c2, c3, d2, d3
483 xxpermdi 32+\a0, 10, 11, 0 # a0, a1, a2, a3
484 xxpermdi 32+\a1, 10, 11, 3 # b0, b1, b2, b3
485 xxpermdi 32+\a2, 12, 13, 0 # c0, c1, c2, c3
486 xxpermdi 32+\a3, 12, 13, 3 # d0, d1, d2, d3
491 vadduwm \S+0, \S+0, 16-\S
492 vadduwm \S+4, \S+4, 17-\S
493 vadduwm \S+8, \S+8, 18-\S
494 vadduwm \S+12, \S+12, 19-\S
496 vadduwm \S+1, \S+1, 16-\S
497 vadduwm \S+5, \S+5, 17-\S
498 vadduwm \S+9, \S+9, 18-\S
499 vadduwm \S+13, \S+13, 19-\S
501 vadduwm \S+2, \S+2, 16-\S
502 vadduwm \S+6, \S+6, 17-\S
503 vadduwm \S+10, \S+10, 18-\S
504 vadduwm \S+14, \S+14, 19-\S
506 vadduwm \S+3, \S+3, 16-\S
507 vadduwm \S+7, \S+7, 17-\S
508 vadduwm \S+11, \S+11, 18-\S
509 vadduwm \S+15, \S+15, 19-\S
518 lxvw4x 0, 0, 9
535 xxlxor \S+32, \S+32, 0
552 stxvw4x \S+32, 0, 16
580 cmpdi 6, 0
585 # r17 - r31 mainly for Write_256 macro.
587 li 18, 32
603 li 14, 0 # offset to inp and outp
605 lxvw4x 48, 0, 3 # vr16, constants
610 # create (0, 1, 2, 3) counters
611 vspltisw 0, 0
615 vmrghw 4, 0, 1
617 vsldoi 30, 4, 5, 8 # vr30 counter, 4 (0, 1, 2, 3)
624 lxvw4x 32+20, 0, 11
625 lxvw4x 32+22, 17, 11
640 xxlor 25, 32+26, 32+26
641 xxlor 24, 32+25, 32+25
643 vadduwm 31, 30, 25 # counter = (0, 1, 2, 3) + (4, 4, 4, 4)
644 xxlor 30, 32+30, 32+30
645 xxlor 31, 32+31, 32+31
647 xxlor 20, 32+20, 32+20
648 xxlor 21, 32+21, 32+21
649 xxlor 22, 32+22, 32+22
650 xxlor 23, 32+23, 32+23
656 xxspltw 32+0, 16, 0
657 xxspltw 32+1, 16, 1
658 xxspltw 32+2, 16, 2
659 xxspltw 32+3, 16, 3
661 xxspltw 32+4, 17, 0
662 xxspltw 32+5, 17, 1
663 xxspltw 32+6, 17, 2
664 xxspltw 32+7, 17, 3
665 xxspltw 32+8, 18, 0
666 xxspltw 32+9, 18, 1
667 xxspltw 32+10, 18, 2
668 xxspltw 32+11, 18, 3
669 xxspltw 32+12, 19, 0
670 xxspltw 32+13, 19, 1
671 xxspltw 32+14, 19, 2
672 xxspltw 32+15, 19, 3
675 xxspltw 32+16, 16, 0
676 xxspltw 32+17, 16, 1
677 xxspltw 32+18, 16, 2
678 xxspltw 32+19, 16, 3
680 xxspltw 32+20, 17, 0
681 xxspltw 32+21, 17, 1
682 xxspltw 32+22, 17, 2
683 xxspltw 32+23, 17, 3
684 xxspltw 32+24, 18, 0
685 xxspltw 32+25, 18, 1
686 xxspltw 32+26, 18, 2
687 xxspltw 32+27, 18, 3
688 xxspltw 32+28, 19, 0
689 xxspltw 32+29, 19, 1
691 xxspltw 32+30, 19, 2
692 xxspltw 32+31, 19, 3
700 xxlor 0, 32+30, 32+30
701 xxlor 32+30, 30, 30
703 xxlor 32+30, 0, 0
704 TP_4x 0, 1, 2, 3
709 xxlor 0, 48, 48
717 Add_state 0
718 xxlor 48, 0, 0
722 Write_256 0
724 addi 15, 15, -256 # len -=256
726 xxlor 5, 32+31, 32+31
727 xxlor 32+31, 31, 31
729 xxlor 32+31, 5, 5
730 TP_4x 16+0, 16+1, 16+2, 16+3
735 xxlor 32, 16, 16
742 addi 15, 15, -256 # len +=256
744 xxlor 32+24, 24, 24
745 xxlor 32+25, 25, 25
746 xxlor 32+30, 30, 30
749 xxlor 30, 32+30, 32+30
750 xxlor 31, 32+31, 32+31
752 cmpdi 15, 0
762 lxvw4x 48, 0, 3 # vr16, constants
771 lxvw4x 32+20, 0, 11
772 lxvw4x 32+22, 17, 11
778 vspltw 0, 16, 0
783 vspltw 4, 17, 0
787 vspltw 8, 18, 0
791 vspltw 12, 19, 0
804 TP_4x 0, 1, 2, 3
809 Add_state 0
810 Write_256 0
812 addi 15, 15, -256 # len += 256
818 cmpdi 15, 0
831 li 3, 0
838 .long 0x22330011, 0x66774455, 0xaabb8899, 0xeeffccdd
839 .long 0x11223300, 0x55667744, 0x99aabb88, 0xddeeffcc