1 // SPDX-License-Identifier: GPL-2.0
17 #define PCI_DEV_REV_OFFSET		0x08
18 #define PERI_GEN_RESET			0
19 #define OUT_EN_OFFSET(x)		((((x) / 32) * 4) + 0x400)
20 #define INP_EN_OFFSET(x)		((((x) / 32) * 4) + 0x400 + 0x10)
21 #define OUT_OFFSET(x)			((((x) / 32) * 4) + 0x400 + 0x20)
22 #define INP_OFFSET(x)			((((x) / 32) * 4) + 0x400 + 0x30)
23 #define PULLUP_OFFSET(x)		((((x) / 32) * 4) + 0x400 + 0x40)
24 #define PULLDOWN_OFFSET(x)		((((x) / 32) * 4) + 0x400 + 0x50)
25 #define OPENDRAIN_OFFSET(x)		((((x) / 32) * 4) + 0x400 + 0x60)
26 #define WAKEMASK_OFFSET(x)		((((x) / 32) * 4) + 0x400 + 0x70)
27 #define MODE_OFFSET(x)			((((x) / 32) * 4) + 0x400 + 0x80)
28 #define INTR_LO_TO_HI_EDGE_CONFIG(x)	((((x) / 32) * 4) + 0x400 + 0x90)
29 #define INTR_HI_TO_LO_EDGE_CONFIG(x)	((((x) / 32) * 4) + 0x400 + 0xA0)
30 #define INTR_LEVEL_CONFIG_OFFSET(x)	((((x) / 32) * 4) + 0x400 + 0xB0)
31 #define INTR_LEVEL_MASK_OFFSET(x)	((((x) / 32) * 4) + 0x400 + 0xC0)
32 #define INTR_STAT_OFFSET(x)		((((x) / 32) * 4) + 0x400 + 0xD0)
33 #define DEBOUNCE_OFFSET(x)		((((x) / 32) * 4) + 0x400 + 0xE0)
34 #define PIO_GLOBAL_CONFIG_OFFSET	(0x400 + 0xF0)
35 #define PIO_PCI_CTRL_REG_OFFSET	(0x400 + 0xF4)
36 #define INTR_MASK_OFFSET(x)		((((x) / 32) * 4) + 0x400 + 0x100)
37 #define INTR_STATUS_OFFSET(x)		(((x) * 4) + 0x400 + 0xD0)
52 	struct device *parent = priv->aux_dev->dev.parent;  in pci1xxxx_gpio_get_device_revision()
61 	priv->dev_rev = val;  in pci1xxxx_gpio_get_device_revision()
63 	return 0;  in pci1xxxx_gpio_get_device_revision()
70 	int ret = -EINVAL;  in pci1xxxx_gpio_get_direction()
72 	data = readl(priv->reg_base + INP_EN_OFFSET(nr));  in pci1xxxx_gpio_get_direction()
73 	if (data & BIT(nr % 32)) {  in pci1xxxx_gpio_get_direction()
76 		data = readl(priv->reg_base + OUT_EN_OFFSET(nr));  in pci1xxxx_gpio_get_direction()
77 		if (data & BIT(nr % 32))  in pci1xxxx_gpio_get_direction()
78 			ret =  0;  in pci1xxxx_gpio_get_direction()
102 	spin_lock_irqsave(&priv->lock, flags);  in pci1xxxx_gpio_direction_input()
103 	pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true);  in pci1xxxx_gpio_direction_input()
104 	pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false);  in pci1xxxx_gpio_direction_input()
105 	spin_unlock_irqrestore(&priv->lock, flags);  in pci1xxxx_gpio_direction_input()
107 	return 0;  in pci1xxxx_gpio_direction_input()
114 	return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1;  in pci1xxxx_gpio_get()
124 	spin_lock_irqsave(&priv->lock, flags);  in pci1xxxx_gpio_direction_output()
125 	pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false);  in pci1xxxx_gpio_direction_output()
126 	pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true);  in pci1xxxx_gpio_direction_output()
127 	data = readl(priv->reg_base + OUT_OFFSET(nr));  in pci1xxxx_gpio_direction_output()
129 		data |= (1 << (nr % 32));  in pci1xxxx_gpio_direction_output()
131 		data &= ~(1 << (nr % 32));  in pci1xxxx_gpio_direction_output()
132 	writel(data, priv->reg_base + OUT_OFFSET(nr));  in pci1xxxx_gpio_direction_output()
133 	spin_unlock_irqrestore(&priv->lock, flags);  in pci1xxxx_gpio_direction_output()
135 	return 0;  in pci1xxxx_gpio_direction_output()
143 	spin_lock_irqsave(&priv->lock, flags);  in pci1xxxx_gpio_set()
144 	pci1xxx_assign_bit(priv->reg_base, OUT_OFFSET(nr), (nr % 32), val);  in pci1xxxx_gpio_set()
145 	spin_unlock_irqrestore(&priv->lock, flags);  in pci1xxxx_gpio_set()
147 	return 0;  in pci1xxxx_gpio_set()
155 	int ret = 0;  in pci1xxxx_gpio_set_config()
157 	spin_lock_irqsave(&priv->lock, flags);  in pci1xxxx_gpio_set_config()
160 		pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), true);  in pci1xxxx_gpio_set_config()
163 		pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), true);  in pci1xxxx_gpio_set_config()
166 		pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), false);  in pci1xxxx_gpio_set_config()
167 		pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), false);  in pci1xxxx_gpio_set_config()
170 		pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), true);  in pci1xxxx_gpio_set_config()
173 		pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), false);  in pci1xxxx_gpio_set_config()
176 		ret = -ENOTSUPP;  in pci1xxxx_gpio_set_config()
179 	spin_unlock_irqrestore(&priv->lock, flags);  in pci1xxxx_gpio_set_config()
191 	spin_lock_irqsave(&priv->lock, flags);  in pci1xxxx_gpio_irq_ack()
192 	writel(BIT(gpio % 32), priv->reg_base + INTR_STAT_OFFSET(gpio));  in pci1xxxx_gpio_irq_ack()
193 	spin_unlock_irqrestore(&priv->lock, flags);  in pci1xxxx_gpio_irq_ack()
205 	spin_lock_irqsave(&priv->lock, flags);  in pci1xxxx_gpio_irq_set_mask()
206 	pci1xxx_assign_bit(priv->reg_base, INTR_MASK_OFFSET(gpio), (gpio % 32), set);  in pci1xxxx_gpio_irq_set_mask()
207 	spin_unlock_irqrestore(&priv->lock, flags);  in pci1xxxx_gpio_irq_set_mask()
227 	unsigned int bitpos = gpio % 32;  in pci1xxxx_gpio_set_type()
230 		pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio),  in pci1xxxx_gpio_set_type()
232 		pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio),  in pci1xxxx_gpio_set_type()
236 		pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio),  in pci1xxxx_gpio_set_type()
241 		pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio),  in pci1xxxx_gpio_set_type()
243 		pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,  in pci1xxxx_gpio_set_type()
247 		pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio),  in pci1xxxx_gpio_set_type()
252 		pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio),  in pci1xxxx_gpio_set_type()
254 		pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio),  in pci1xxxx_gpio_set_type()
256 		pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,  in pci1xxxx_gpio_set_type()
262 		pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio),  in pci1xxxx_gpio_set_type()
264 		pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio),  in pci1xxxx_gpio_set_type()
266 		pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,  in pci1xxxx_gpio_set_type()
272 		pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), bitpos, true);  in pci1xxxx_gpio_set_type()
282 	unsigned int bitpos = gpio % 32;  in pci1xxxx_gpio_set_wake()
283 	unsigned int bank = gpio / 32;  in pci1xxxx_gpio_set_wake()
286 		priv->gpio_wake_mask[bank] |= (1 << bitpos);  in pci1xxxx_gpio_set_wake()
288 		priv->gpio_wake_mask[bank] &= ~(1 << bitpos);  in pci1xxxx_gpio_set_wake()
290 	return 0;  in pci1xxxx_gpio_set_wake()
296 	struct gpio_chip *gc =  &priv->gpio;  in pci1xxxx_gpio_irq_handler()
297 	unsigned long int_status = 0;  in pci1xxxx_gpio_irq_handler()
304 	spin_lock_irqsave(&priv->lock, flags);  in pci1xxxx_gpio_irq_handler()
305 	pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, true);  in pci1xxxx_gpio_irq_handler()
306 	spin_unlock_irqrestore(&priv->lock, flags);  in pci1xxxx_gpio_irq_handler()
307 	for (gpiobank = 0; gpiobank < 3; gpiobank++) {  in pci1xxxx_gpio_irq_handler()
308 		spin_lock_irqsave(&priv->lock, flags);  in pci1xxxx_gpio_irq_handler()
309 		int_status = readl(priv->reg_base + INTR_STATUS_OFFSET(gpiobank));  in pci1xxxx_gpio_irq_handler()
310 		spin_unlock_irqrestore(&priv->lock, flags);  in pci1xxxx_gpio_irq_handler()
314 			pincount = 32;  in pci1xxxx_gpio_irq_handler()
318 			spin_lock_irqsave(&priv->lock, flags);  in pci1xxxx_gpio_irq_handler()
319 			writel(BIT(bit), priv->reg_base + INTR_STATUS_OFFSET(gpiobank));  in pci1xxxx_gpio_irq_handler()
320 			spin_unlock_irqrestore(&priv->lock, flags);  in pci1xxxx_gpio_irq_handler()
321 			irq = irq_find_mapping(gc->irq.domain, (bit + (gpiobank * 32)));  in pci1xxxx_gpio_irq_handler()
322 			raw_spin_lock_irqsave(&priv->wa_lock, wa_flags);  in pci1xxxx_gpio_irq_handler()
324 			raw_spin_unlock_irqrestore(&priv->wa_lock, wa_flags);  in pci1xxxx_gpio_irq_handler()
327 	spin_lock_irqsave(&priv->lock, flags);  in pci1xxxx_gpio_irq_handler()
328 	pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, false);  in pci1xxxx_gpio_irq_handler()
329 	spin_unlock_irqrestore(&priv->lock, flags);  in pci1xxxx_gpio_irq_handler()
348 	struct device *parent = priv->aux_dev->dev.parent;  in pci1xxxx_gpio_suspend()
355 	for (gpiobank = 0; gpiobank < 3; gpiobank++) {  in pci1xxxx_gpio_suspend()
356 		wake_mask = priv->gpio_wake_mask[gpiobank];  in pci1xxxx_gpio_suspend()
359 			gpio_bank_base = gpiobank * 32;  in pci1xxxx_gpio_suspend()
361 			pci1xxx_assign_bit(priv->reg_base,  in pci1xxxx_gpio_suspend()
362 					   PIO_PCI_CTRL_REG_OFFSET, 0, true);  in pci1xxxx_gpio_suspend()
363 			writel(~wake_mask, priv->reg_base +  in pci1xxxx_gpio_suspend()
368 	spin_lock_irqsave(&priv->lock, flags);  in pci1xxxx_gpio_suspend()
369 	pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,  in pci1xxxx_gpio_suspend()
371 	pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,  in pci1xxxx_gpio_suspend()
373 	pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, true);  in pci1xxxx_gpio_suspend()
375 	if (priv->dev_rev >= 0xC0)  in pci1xxxx_gpio_suspend()
376 		pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 17, true);  in pci1xxxx_gpio_suspend()
378 	spin_unlock_irqrestore(&priv->lock, flags);  in pci1xxxx_gpio_suspend()
380 	device_set_wakeup_enable(&pcidev->dev, true);  in pci1xxxx_gpio_suspend()
383 	return 0;  in pci1xxxx_gpio_suspend()
389 	struct device *parent = priv->aux_dev->dev.parent;  in pci1xxxx_gpio_resume()
396 	for (gpiobank = 0; gpiobank < 3; gpiobank++) {  in pci1xxxx_gpio_resume()
397 		wake_mask = priv->gpio_wake_mask[gpiobank];  in pci1xxxx_gpio_resume()
400 			gpio_bank_base = gpiobank * 32;  in pci1xxxx_gpio_resume()
402 			writel(wake_mask, priv->reg_base +  in pci1xxxx_gpio_resume()
404 			pci1xxx_assign_bit(priv->reg_base,  in pci1xxxx_gpio_resume()
405 					   PIO_PCI_CTRL_REG_OFFSET, 0, false);  in pci1xxxx_gpio_resume()
406 			writel(0xffffffff, priv->reg_base +  in pci1xxxx_gpio_resume()
411 	spin_lock_irqsave(&priv->lock, flags);  in pci1xxxx_gpio_resume()
412 	pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,  in pci1xxxx_gpio_resume()
414 	pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,  in pci1xxxx_gpio_resume()
416 	pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, false);  in pci1xxxx_gpio_resume()
418 	if (priv->dev_rev >= 0xC0)  in pci1xxxx_gpio_resume()
419 		pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 17, false);  in pci1xxxx_gpio_resume()
421 	spin_unlock_irqrestore(&priv->lock, flags);  in pci1xxxx_gpio_resume()
425 	return 0;  in pci1xxxx_gpio_resume()
430 	struct gpio_chip *gchip = &priv->gpio;  in pci1xxxx_gpio_setup()
434 	gchip->label = dev_name(&priv->aux_dev->dev);  in pci1xxxx_gpio_setup()
435 	gchip->parent = &priv->aux_dev->dev;  in pci1xxxx_gpio_setup()
436 	gchip->owner = THIS_MODULE;  in pci1xxxx_gpio_setup()
437 	gchip->direction_input = pci1xxxx_gpio_direction_input;  in pci1xxxx_gpio_setup()
438 	gchip->direction_output = pci1xxxx_gpio_direction_output;  in pci1xxxx_gpio_setup()
439 	gchip->get_direction = pci1xxxx_gpio_get_direction;  in pci1xxxx_gpio_setup()
440 	gchip->get = pci1xxxx_gpio_get;  in pci1xxxx_gpio_setup()
441 	gchip->set = pci1xxxx_gpio_set;  in pci1xxxx_gpio_setup()
442 	gchip->set_config = pci1xxxx_gpio_set_config;  in pci1xxxx_gpio_setup()
443 	gchip->dbg_show = NULL;  in pci1xxxx_gpio_setup()
444 	gchip->base = -1;  in pci1xxxx_gpio_setup()
445 	gchip->ngpio =  PCI1XXXX_NR_PINS;  in pci1xxxx_gpio_setup()
446 	gchip->can_sleep = false;  in pci1xxxx_gpio_setup()
448 	retval = devm_request_threaded_irq(&priv->aux_dev->dev, irq,  in pci1xxxx_gpio_setup()
455 	girq = &priv->gpio.irq;  in pci1xxxx_gpio_setup()
457 	girq->parent_handler = NULL;  in pci1xxxx_gpio_setup()
458 	girq->num_parents = 0;  in pci1xxxx_gpio_setup()
459 	girq->parents = NULL;  in pci1xxxx_gpio_setup()
460 	girq->default_type = IRQ_TYPE_NONE;  in pci1xxxx_gpio_setup()
461 	girq->handler = handle_bad_irq;  in pci1xxxx_gpio_setup()
463 	return 0;  in pci1xxxx_gpio_setup()
478 	pdata = &aux_dev_wrapper->gp_aux_data;  in pci1xxxx_gpio_probe()
481 		return -EINVAL;  in pci1xxxx_gpio_probe()
483 	priv = devm_kzalloc(&aux_dev->dev, sizeof(struct pci1xxxx_gpio), GFP_KERNEL);  in pci1xxxx_gpio_probe()
485 		return -ENOMEM;  in pci1xxxx_gpio_probe()
487 	spin_lock_init(&priv->lock);  in pci1xxxx_gpio_probe()
488 	priv->aux_dev = aux_dev;  in pci1xxxx_gpio_probe()
490 	if (!devm_request_mem_region(&aux_dev->dev, pdata->region_start, 0x800, aux_dev->name))  in pci1xxxx_gpio_probe()
491 		return -EBUSY;  in pci1xxxx_gpio_probe()
493 	priv->reg_base = devm_ioremap(&aux_dev->dev, pdata->region_start, 0x800);  in pci1xxxx_gpio_probe()
494 	if (!priv->reg_base)  in pci1xxxx_gpio_probe()
495 		return -ENOMEM;  in pci1xxxx_gpio_probe()
497 	writel(0x0264, (priv->reg_base + 0x400 + 0xF0));  in pci1xxxx_gpio_probe()
499 	retval = pci1xxxx_gpio_setup(priv, pdata->irq_num);  in pci1xxxx_gpio_probe()
501 	if (retval < 0)  in pci1xxxx_gpio_probe()
508 	dev_set_drvdata(&aux_dev->dev, priv);  in pci1xxxx_gpio_probe()
510 	return devm_gpiochip_add_data(&aux_dev->dev, &priv->gpio, priv);  in pci1xxxx_gpio_probe()