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/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl502d.h2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_WAIT_FOR_IDLE 0x0110
30 …_WAIT_FOR_IDLE_V 31:0
32 …_SET_DST_CONTEXT_DMA 0x0184
33 …_SET_DST_CONTEXT_DMA_HANDLE 31:0
35 …_SET_SRC_CONTEXT_DMA 0x0188
36 …_SET_SRC_CONTEXT_DMA_HANDLE 31:0
38 …_SET_SEMAPHORE_CONTEXT_DMA 0x018c
[all …]
H A Dcl902d.h2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_CLASS_ID 15:0
30 …_WAIT_FOR_IDLE 0x0110
31 …_WAIT_FOR_IDLE_V 31:0
33 …_SET_DST_FORMAT 0x0200
34 …_SET_DST_FORMAT_V 7:0
35 …_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF
36 …_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0
37 …_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF
[all …]
H A Dcl5039.h2 * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_NO_OPERATION 0x0100
30 …_NO_OPERATION_V 31:0
32 …_SET_CONTEXT_DMA_NOTIFY 0x0180
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
35 …_SET_CONTEXT_DMA_BUFFER_IN 0x0184
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
38 …_SET_CONTEXT_DMA_BUFFER_OUT 0x0188
[all …]
/linux/arch/powerpc/lib/
H A Dfeature-fixups-test.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 #include <asm/feature-fixups.h>
9 #include <asm/asm-compat.h>
10 #include <asm/ppc-opcode.h>
48 or 31,31,31
52 or 31,31,31
68 or 31,31,31
69 or 31,31,31
83 or 31,31,31
84 or 31,31,31
[all …]
/linux/arch/powerpc/xmon/
H A Dppc-opc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
135 #define UNUSED 0
136 { 0, 0, NULL, NULL, 0 },
142 #define BI_MASK (0x1f << 16)
143 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
148 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
152 #define BB_MASK (0x1f << 11)
[all …]
/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv1 # SPDX-License-Identifier: CC0-1.0
2 # Generator: x86-cpuid-db v3.0
5 # Auto-generated file.
6 # Please submit all updates and bugfixes to https://x86-cpuid.org
12 # Leaf 0H
15 0x
[all...]
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_ethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
90 /* MAC-Level Diagnostic Counters */
94 .offset = 0,
95 .start = 31,
101 .offset = 0x0,
108 .offset = 0x0,
115 .offset = 0x0,
117 .end = 0,
119 /* MAC-Level Diagnostic Flags */
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-vsp1-hgo.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _v4l2-meta-fmt-vsp1-hgo:
10 Renesas R-Car VSP1 1-D Histogram Data
16 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
21 computes the minimum, maximum and sum of all pixels as well as per-channel
29 - In *64 bins normal mode*, the HGO operates on the three channels independently
30 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
32 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
33 channels to compute a single 64-bins histogram. Only the RGB image format is
35 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
[all …]
H A Dmetafmt-vsp1-hgt.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _v4l2-meta-fmt-vsp1-hgt:
10 Renesas R-Car VSP1 2-D Histogram Data
16 This format describes histogram data generated by the Renesas R-Car VSP1
17 2-D Histogram (HGT) engine.
29 The Saturation position **n** (0 - 31) of the bucket in the matrix is
34 The Hue position **m** (0 - 5) of the bucket in the matrix depends on
44 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5
51 5U 0L 0U 1L 1U 2L 2U 3L 3U 4L 4U 5L 5U 0L
52 <0..............................Hue Value............................255>
[all …]
/linux/drivers/video/fbdev/nvidia/
H A Dnv_dma.h8 |* hereby granted a nonexclusive, royalty-free copyright license to *|
11 |* Any use of this source code must include, in the user documenta- *|
19 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
21 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
23 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
24 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
33 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
35 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
42 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
43 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
[all …]
/linux/lib/crypto/powerpc/
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
16 # clamp r &= 0x0FFFFFFC0FFFFFFC 0x0FFFFFFC0FFFFFFF
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-ciu2-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 …ine CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * …
32 …ine CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * …
33 … CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * …
34 …CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * …
35 …CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * …
36 …_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * …
37 …_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * …
[all …]
H A Dcvmx-pexp-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31…
32 #define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
33 #define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
34 #define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
35 #define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
36 #define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
37 #define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
[all …]
/linux/drivers/net/ipa/reg/
H A Dipa_reg-v3.1.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 [COMP_CFG_ENABLE] = BIT(0),
18 /* Bits 5-31 reserved */
21 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
24 [CLKON_RX] = BIT(0),
41 /* Bits 17-31 reserved */
44 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
47 [ROUTE_DIS] = BIT(0),
52 /* Bits 22-23 reserved */
[all …]
H A Dipa_reg-v5.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
13 [MAX_PIPES] = GENMASK(7, 0),
16 [PROD_LOWEST] = GENMASK(31, 24),
19 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
39 /* Bits 17-18 reserved */
44 /* Bits 28-29 reserved */
46 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
49 REG_FIELDS(COMP_CFG, comp_cfg, 0x00000048);
[all …]
H A Dipa_reg-v5.0.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
13 [MAX_PIPES] = GENMASK(7, 0),
16 [PROD_LOWEST] = GENMASK(31, 24),
19 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
45 /* Bits 28-29 reserved */
47 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
50 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000002c);
53 [CLKON_RX] = BIT(0),
[all …]
H A Dipa_reg-v3.5.1.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 [COMP_CFG_ENABLE] = BIT(0),
18 /* Bits 5-31 reserved */
21 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
24 [CLKON_RX] = BIT(0),
46 /* Bits 22-31 reserved */
49 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
52 [ROUTE_DIS] = BIT(0),
57 /* Bits 22-23 reserved */
[all …]
H A Dipa_reg-v4.2.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 /* Bit 0 reserved */
31 /* Bits 21-31 reserved */
34 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
37 [CLKON_RX] = BIT(0),
67 /* Bits 30-31 reserved */
70 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
73 [ROUTE_DIS] = BIT(0),
78 /* Bits 22-23 reserved */
[all …]
H A Dipa_reg-v4.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 /* Bit 0 reserved */
32 /* Bits 22-31 reserved */
35 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
38 [CLKON_RX] = BIT(0),
69 /* Bit 31 reserved */
72 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
75 [ROUTE_DIS] = BIT(0),
80 /* Bits 22-23 reserved */
[all …]
H A Dipa_reg-v4.11.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
36 /* Bits 24-29 reserved */
38 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
41 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
44 [CLKON_RX] = BIT(0),
75 [DRBIP] = BIT(31),
78 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
81 [ROUTE_DIS] = BIT(0),
[all …]
H A Dipa_reg-v4.7.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
32 /* Bits 22-31 reserved */
35 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
38 [CLKON_RX] = BIT(0),
69 [DRBIP] = BIT(31),
72 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
75 [ROUTE_DIS] = BIT(0),
80 /* Bits 22-23 reserved */
[all …]
H A Dipa_reg-v4.9.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
35 /* Bits 25-29 reserved */
37 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
40 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
43 [CLKON_RX] = BIT(0),
74 [DRBIP] = BIT(31),
77 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
80 [ROUTE_DIS] = BIT(0),
[all …]
/linux/drivers/ras/amd/atl/
H A Dreg_fields.h1 /* SPDX-License-Identifier: GPL-2.0 */
50 * D18F1x208 [System Fabric ID Mask 0]
51 * DF3 ComponentIdMask [9:0]
53 * D18F1x150 [System Fabric ID Mask 0]
54 * DF3p5 ComponentIdMask [15:0]
56 * D18F4x1B0 [System Fabric ID Mask 0]
57 * DF4 ComponentIdMask [15:0]
58 * DF4p5 ComponentIdMask [15:0]
60 #define DF3_COMPONENT_ID_MASK GENMASK(9, 0)
61 #define DF4_COMPONENT_ID_MASK GENMASK(15, 0)
[all …]
/linux/tools/testing/selftests/hid/tests/
H A Dtest_multitouch.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
21 KERNEL_MODULE = base.KernelModule("hid-multitouch", "hid_multitouch")
29 "NOT_SEEN_MEANS_UP": BIT(0),
67 self.azimuth = 0
75 super().__init__(0, x, y)
81 self.twist = 0
92 Usage Page (0xff00)
93 Usage (0xc5)
94 Logical Minimum (0)
[all …]
/linux/drivers/bus/mhi/
H A Dcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #define MHIREGLEN 0x00
15 #define MHIVER 0x08
16 #define MHICFG 0x10
17 #define CHDBOFF 0x18
18 #define ERDBOFF 0x20
19 #define BHIOFF 0x28
20 #define BHIEOFF 0x2c
21 #define DEBUGOFF 0x30
22 #define MHICTRL 0x38
[all …]

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