Lines Matching +full:0 +full:- +full:31
1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
32 /* Bits 22-31 reserved */
35 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
38 [CLKON_RX] = BIT(0),
69 [DRBIP] = BIT(31),
72 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
75 [ROUTE_DIS] = BIT(0),
80 /* Bits 22-23 reserved */
82 /* Bits 25-31 reserved */
85 REG_FIELDS(ROUTE, route, 0x00000048);
88 [MEM_SIZE] = GENMASK(15, 0),
89 [MEM_BADDR] = GENMASK(31, 16),
92 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
95 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
97 /* Bits 8-31 reserved */
100 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
103 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
105 /* Bits 8-15 reserved */
107 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
110 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
113 [IPV6_ROUTER_HASH] = BIT(0),
114 /* Bits 1-3 reserved */
116 /* Bits 5-7 reserved */
118 /* Bits 9-11 reserved */
120 /* Bits 13-31 reserved */
123 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
125 /* Valid bits defined by ipa->available */
126 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
129 [IPA_BASE_ADDR] = GENMASK(17, 0),
130 /* Bits 18-31 reserved */
134 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
136 /* Valid bits defined by ipa->available */
137 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
140 /* Bits 0-1 reserved */
149 /* Bits 19-31 reserved */
152 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
155 [MAX_PIPES] = GENMASK(3, 0),
156 /* Bits 4-7 reserved */
158 /* Bits 13-15 reserved */
160 /* Bits 21-23 reserved */
162 /* Bits 28-31 reserved */
165 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
168 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
170 /* Bits 17-31 reserved */
173 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
176 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
177 /* Bits 5-6 reserved */
180 /* Bits 13-15 reserved */
182 /* Bits 21-31 reserved */
185 REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
188 [DIV_VALUE] = GENMASK(8, 0),
189 /* Bits 9-30 reserved */
190 [DIV_ENABLE] = BIT(31),
193 REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
196 [PULSE_GRAN_0] = GENMASK(2, 0),
201 REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
204 [X_MIN_LIM] = GENMASK(5, 0),
205 /* Bits 6-7 reserved */
207 /* Bits 14-15 reserved */
209 /* Bits 22-23 reserved */
211 /* Bits 30-31 reserved */
215 0x00000400, 0x0020);
218 [X_MIN_LIM] = GENMASK(5, 0),
219 /* Bits 6-7 reserved */
221 /* Bits 14-15 reserved */
223 /* Bits 22-23 reserved */
225 /* Bits 30-31 reserved */
229 0x00000404, 0x0020);
232 [X_MIN_LIM] = GENMASK(5, 0),
233 /* Bits 6-7 reserved */
235 /* Bits 14-15 reserved */
237 /* Bits 22-23 reserved */
239 /* Bits 30-31 reserved */
243 0x00000500, 0x0020);
246 [X_MIN_LIM] = GENMASK(5, 0),
247 /* Bits 6-7 reserved */
249 /* Bits 14-15 reserved */
251 /* Bits 22-23 reserved */
253 /* Bits 30-31 reserved */
257 0x00000504, 0x0020);
260 [FRAG_OFFLOAD_EN] = BIT(0),
265 /* Bits 9-31 reserved */
268 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
271 [NAT_EN] = GENMASK(1, 0),
272 /* Bits 2-31 reserved */
275 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
278 [HDR_LEN] = GENMASK(5, 0),
287 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
290 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
293 [HDR_ENDIANNESS] = BIT(0),
299 /* Bits 14-15 reserved */
303 /* Bits 22-31 reserved */
306 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
309 0x00000818, 0x0070);
312 [ENDP_MODE] = GENMASK(2, 0),
315 /* Bits 9-11 reserved */
319 /* Bits 30-31 reserved */
322 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
325 [AGGR_EN] = GENMASK(1, 0),
336 /* Bits 28-31 reserved */
339 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
342 [HOL_BLOCK_EN] = BIT(0),
343 /* Bits 1-31 reserved */
347 0x0000082c, 0x0070);
350 [TIMER_LIMIT] = GENMASK(4, 0),
351 /* Bits 5-7 reserved */
353 /* Bits 9-31 reserved */
357 0x00000830, 0x0070);
360 [DEAGGR_HDR_LEN] = GENMASK(5, 0),
366 [MAX_PACKET_LEN] = GENMASK(31, 16),
369 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
372 [ENDP_RSRC_GRP] = BIT(0),
373 /* Bits 1-31 reserved */
376 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
379 [SEQ_TYPE] = GENMASK(7, 0),
380 /* Bits 8-31 reserved */
383 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
386 [STATUS_EN] = BIT(0),
388 /* Bits 6-8 reserved */
390 /* Bits 10-31 reserved */
393 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
396 [FILTER_HASH_MSK_SRC_ID] = BIT(0),
403 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0),
404 /* Bits 7-15 reserved */
413 /* Bits 23-31 reserved */
417 0x0000085c, 0x0070);
420 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
423 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
426 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
429 [UC_INTR] = BIT(0),
430 /* Bits 1-31 reserved */
433 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
435 /* Valid bits defined by ipa->available */
437 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
439 /* Valid bits defined by ipa->available */
441 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
443 /* Valid bits defined by ipa->available */
445 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);