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/linux/arch/xtensa/variants/de212/include/variant/
H A Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 #define XCHAL_CP_NUM 0 /* number of coprocessors */
36 #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
40 /* Save area for non-coprocessor optional and custom (TIE) state: */
45 #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
58 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
59 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
[all …]
/linux/arch/xtensa/variants/csp/include/variant/
H A Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
43 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
45 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
48 #define XCHAL_CP0_SA_SIZE 0
50 #define XCHAL_CP1_SA_SIZE 0
52 #define XCHAL_CP2_SA_SIZE 0
[all …]
/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
55 #define XCHAL_CP2_SA_SIZE 0
[all …]
/linux/tools/testing/selftests/cgroup/
H A Dtest_cpuset_prs.sh2 # SPDX-License-Identifier: GPL-2.0
16 [[ $(id -u) -eq 0 ]] || skip_test "Test must be run as root!"
20 WAIT_INOTIFY=$(cd $(dirname $0); pwd)/wait_inotify
23 CGROUP2=$(mount -t cgroup2 | head -1 | awk -e '{print $3}')
24 [[ -n "$CGROUP2" ]] || skip_test "Cgroup v2 mount point not found!"
28 NR_CPUS=$(lscpu | grep "^CPU(s):" | sed -e "s/.*:[[:space:]]*//")
29 [[ $NR_CPUS -lt 8 ]] && skip_test "Test needs at least 8 cpus available!"
32 if [[ -c /dev/console && -w /dev/console ]]
41 VERBOSE=0
44 while [[ "$1" = -* ]]
[all …]
/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
55 #define XCHAL_CP2_SA_SIZE 0
[all …]
/linux/tools/testing/selftests/kvm/aarch64/
H A Dget-reg-list.c
/linux/tools/arch/arm64/include/asm/
H A Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-
[all...]
/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #define LP_OPTIONS 0
20 * If page size and eraseblock size are 0, the sizes are taken from the
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
30 { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
33 { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
[all …]
H A Dsm_common.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2009 - Maxim Levitsky
16 return -ERANGE; in oob_sm_ooblayout_ecc()
18 oobregion->length = 3; in oob_sm_ooblayout_ecc()
19 oobregion->offset = ((section + 1) * 8) - 3; in oob_sm_ooblayout_ecc()
21 return 0; in oob_sm_ooblayout_ecc()
28 case 0: in oob_sm_ooblayout_free()
30 oobregion->offset = 0; in oob_sm_ooblayout_free()
31 oobregion->length = 4; in oob_sm_ooblayout_free()
35 oobregion->offset = 6; in oob_sm_ooblayout_free()
[all …]
/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A Duncore-cache.json3 …ries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",
4 "Counter": "0,1,2,3",
5 "EventCode": "0x35",
8 "UMask": "0x18",
12 …ries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",
13 "Counter": "0,1,2,3",
14 "EventCode": "0x35",
17 "UMask": "0x28",
21 …ries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ",
22 "Counter": "0,1,2,3",
[all …]
/linux/arch/mips/boot/dts/cavium-octeon/
H A Docteon_68xx.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 * use. Because of this, it contains a super-set of the available
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
16 soc@0 {
17 compatible = "simple-bus";
18 #address-cells = <2>;
[all …]
H A Docteon_3xxx.dts1 // SPDX-License-Identifier: GPL-2.0
3 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
6 * use. Because of this, it contains a super-set of the available
13 soc@0 {
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
19 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
[all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Duncore-memory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x4",
10 "UMask": "0x3",
15 "Counter": "0,1,2,3",
16 "EventCode": "0x4",
21 "UMask": "0xc",
26 "Counter": "0,1,2,3",
27 "EventCode": "0x1",
32 "UMask": "0x8",
37 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Duncore-memory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x4",
10 "UMask": "0x3",
15 "Counter": "0,1,2,3",
16 "EventCode": "0x4",
21 "UMask": "0xc",
26 "Counter": "0,1,2,3",
27 "EventCode": "0x1",
31 "UMask": "0x8",
36 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Duncore-memory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x4",
10 "UMask": "0x3",
15 "Counter": "0,1,2,3",
16 "EventCode": "0x4",
21 "UMask": "0xc",
26 "Counter": "0,1,2,3",
27 "EventCode": "0x1",
31 "UMask": "0x8",
36 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Duncore-memory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x1",
9 "UMask": "0x8",
14 "Counter": "0,1,2,3",
15 "EventCode": "0x1",
19 "UMask": "0x1",
24 "Counter": "0,1,2,3",
25 "EventCode": "0x1",
29 "UMask": "0x2",
34 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-memory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x4",
10 "UMask": "0x3",
15 "Counter": "0,1,2,3",
16 "EventCode": "0x4",
21 "UMask": "0xc",
26 "Counter": "0,1,2,3",
27 "EventCode": "0x1",
32 "UMask": "0x8",
37 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A Duncore-interconnect.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x01",
12 "Counter": "0,1,2,3",
13 "EventCode": "0x17",
17 "UMask": "0x1",
22 "Counter": "0,1,2,3",
23 "EventCode": "0x16",
26 "UMask": "0x1",
31 "Counter": "0,1,2,3",
32 "EventCode": "0x18",
[all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A Duncore-interconnect.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x01",
12 "Counter": "0,1,2,3",
13 "EventCode": "0x17",
16 "UMask": "0x1",
21 "Counter": "0,1,2,3",
22 "EventCode": "0x16",
25 "UMask": "0x1",
30 "Counter": "0,1,2,3",
31 "EventCode": "0x18",
[all …]
/linux/lib/
H A Dutil_macros_kunit.c1 // SPDX-License-Identifier: GPL-2.0+
28 static int array_prog1a[] = { 1, 2, 3, 4, 5 }; in test_find_closest()
29 static u32 array_prog1b[] = { 2, 3, 4, 5, 6 }; in test_find_closest()
30 static int array_prog1mix[] = { -2, -1, 0, 1, 2 }; in test_find_closest()
31 static int array_prog2a[] = { 1, 3, 5, 7 }; in test_find_closest()
38 FIND_CLOSEST_RANGE_CHECK(-3, 2, ina226_avg_tab, 0); in test_find_closest()
39 FIND_CLOSEST_RANGE_CHECK(3, 10, ina226_avg_tab, 1); in test_find_closest()
41 FIND_CLOSEST_RANGE_CHECK(41, 96, ina226_avg_tab, 3); in test_find_closest()
48 FIND_CLOSEST_RANGE_CHECK(-3, 1, ad7616_oversampling_avail, 0); in test_find_closest()
49 FIND_CLOSEST_RANGE_CHECK(2, 3, ad7616_oversampling_avail, 1); in test_find_closest()
[all …]
/linux/arch/m68k/include/asm/
H A Dbvme6000hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define BVME_PIT_BASE 0xffa00000
15 pad_a[3], pgcr,
16 pad_b[3], psrr,
17 pad_c[3], paddr,
18 pad_d[3], pbddr,
19 pad_e[3], pcddr,
20 pad_f[3], pivr,
21 pad_g[3], pacr,
22 pad_h[3], pbcr,
[all …]
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A Dpipeline.json3 …ressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specifi…
4 "Counter": "0,1,2,3",
5 "EventCode": "0xB6",
8 "UMask": "0x1"
12 "Counter": "0,1,2,3",
15 "EventCode": "0x14",
19 "UMask": "0x1"
23 "Counter": "0,1,2,3",
24 "EventCode": "0x14",
27 "UMask": "0x1"
[all …]
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Dpipeline.json4 "Counter": "0,1,2,3",
7 "EventCode": "0x14",
11 "UMask": "0x4"
15 "Counter": "0,1,2,3",
16 "EventCode": "0x14",
20 "UMask": "0x1"
24 "Counter": "0,1,2,3",
25 "EventCode": "0x88",
29 "UMask": "0xff"
32 "BriefDescription": "Speculative and retired macro-conditional branches",
[all …]
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A Dpipeline.json4 "Counter": "0,1,2,3",
7 "EventCode": "0x14",
11 "UMask": "0x4"
15 "Counter": "0,1,2,3",
16 "EventCode": "0x14",
20 "UMask": "0x1"
24 "Counter": "0,1,2,3",
25 "EventCode": "0x88",
29 "UMask": "0xff"
32 "BriefDescription": "Speculative and retired macro-conditional branches",
[all …]
/linux/tools/perf/pmu-events/arch/x86/westmereex/
H A Dpipeline.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x14",
8 "UMask": "0x1"
12 "Counter": "0,1,2,3",
15 "EventCode": "0x14",
19 "UMask": "0x1"
23 "Counter": "0,1,2,3",
24 "EventCode": "0x14",
27 "UMask": "0x2"
31 "Counter": "0,1,2,3",
[all …]

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