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2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration11 Copyright (c) 1999-2015 Cadence Design Systems Inc.35 #define XCHAL_CP_NUM 0 /* number of coprocessors */36 #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */37 #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */38 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */40 /* Save area for non-coprocessor optional and custom (TIE) state: */45 #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */58 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)59 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)[all …]
2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration11 Copyright (c) 1999-2015 Cadence Design Systems Inc.36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */37 #define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */43 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */45 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */48 #define XCHAL_CP0_SA_SIZE 050 #define XCHAL_CP1_SA_SIZE 052 #define XCHAL_CP2_SA_SIZE 0[all …]
2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration11 Copyright (c) 1999-2015 Cadence Design Systems Inc.36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */53 #define XCHAL_CP0_SA_SIZE 055 #define XCHAL_CP2_SA_SIZE 0[all …]
2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration11 Copyright (c) 1999-2014 Tensilica Inc.36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */53 #define XCHAL_CP0_SA_SIZE 055 #define XCHAL_CP2_SA_SIZE 0[all …]
2 # SPDX-License-Identifier: GPL-2.016 [[ $(id -u) -eq 0 ]] || skip_test "Test must be run as root!"20 WAIT_INOTIFY=$(cd $(dirname $0); pwd)/wait_inotify23 CGROUP2=$(mount -t cgroup2 | head -1 | awk -e '{print $3}')24 [[ -n "$CGROUP2" ]] || skip_test "Cgroup v2 mount point not found!"28 NR_CPUS=$(lscpu | grep "^CPU(s):" | sed -e "s/.*:[[:space:]]*//")29 [[ $NR_CPUS -lt 8 ]] && skip_test "Test needs at least 8 cpus available!"32 if [[ -c /dev/console && -w /dev/console ]]41 VERBOSE=044 while [[ "$1" = -* ]][all …]
1 // SPDX-License-Identifier: GPL-2.087 for (i = 0; i < ARRAY_SIZE(feat_id_regs); i++) { in check_supported_feat_reg()90 if (ret < 0) in check_supported_feat_reg()93 feat_val = ((data >> feat_id_regs[i].feat_shift) & 0xf); in check_supported_feat_reg()117 if (s->finalize) { in finalize_vcpu()118 feature = s->feature; in finalize_vcpu()138 case KVM_REG_ARM_CORE_REG(regs.regs[0]) ... in core_id_to_str()140 idx = (core_off - KVM_REG_ARM_CORE_REG(regs.regs[0])) / CORE_REGS_XX_NR_WORDS; in core_id_to_str()153 case KVM_REG_ARM_CORE_REG(spsr[0]) ... in core_id_to_str()154 KVM_REG_ARM_CORE_REG(spsr[KVM_NR_SPSR - 1]): in core_id_to_str()[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */14 #include <linux/kasan-tags.h>16 #include <asm/gpr-num.h>22 * [20-19] : Op023 * [18-16] : Op124 * [15-12] : CRn25 * [11-8] : CRm26 * [7-5] : Op229 #define Op0_mask 0x331 #define Op1_mask 0x7[all …]
1 // SPDX-License-Identifier: GPL-2.0-only10 #define LP_OPTIONS 020 * If page size and eraseblock size are 0, the sizes are taken from the29 {"TC58NVG0S3E 1G 3.3V 8-bit",30 { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },32 {"TC58NVG2S0F 4G 3.3V 8-bit",33 { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },35 {"TC58NVG2S0H 4G 3.3V 8-bit",[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright © 2009 - Maxim Levitsky16 return -ERANGE; in oob_sm_ooblayout_ecc()18 oobregion->length = 3; in oob_sm_ooblayout_ecc()19 oobregion->offset = ((section + 1) * 8) - 3; in oob_sm_ooblayout_ecc()21 return 0; in oob_sm_ooblayout_ecc()28 case 0: in oob_sm_ooblayout_free()30 oobregion->offset = 0; in oob_sm_ooblayout_free()31 oobregion->length = 4; in oob_sm_ooblayout_free()35 oobregion->offset = 6; in oob_sm_ooblayout_free()[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */14 #include <linux/kasan-tags.h>17 #include <asm/gpr-num.h>23 * [20-19] : Op024 * [18-16] : Op125 * [15-12] : CRn26 * [11-8] : CRm27 * [7-5] : Op230 #define Op0_mask 0x332 #define Op1_mask 0x7[all …]
3 …ries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",4 "Counter": "0,1,2,3",5 "EventCode": "0x35",8 "UMask": "0x18",12 …ries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",13 "Counter": "0,1,2,3",14 "EventCode": "0x35",17 "UMask": "0x28",21 …ries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ",22 "Counter": "0,1,2,3",[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;7 * use. Because of this, it contains a super-set of the available11 compatible = "cavium,octeon-6880";12 #address-cells = <2>;13 #size-cells = <2>;14 interrupt-parent = <&ciu2>;16 soc@0 {17 compatible = "simple-bus";18 #address-cells = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.6 * use. Because of this, it contains a super-set of the available13 soc@0 {15 phy0: ethernet-phy@0 {17 marvell,reg-init =19 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */22 /* irq, blink-activity, blink-link */23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */[all …]
4 "Counter": "0,1,2,3",5 "EventCode": "0x4",10 "UMask": "0x3",15 "Counter": "0,1,2,3",16 "EventCode": "0x4",21 "UMask": "0xc",26 "Counter": "0,1,2,3",2 { global() object 34 { global() object [all...]
4 "Counter": "0,1,2,3",5 "EventCode": "0x4",10 "UMask": "0x3",15 "Counter": "0,1,2,3",16 "EventCode": "0x4",21 "UMask": "0xc",26 "Counter": "0,1,2,3",27 "EventCode": "0x1",31 "UMask": "0x8",36 "Counter": "0,1,2,3",[all …]
4 "Counter": "0,1,2,3",5 "EventCode": "0x4",10 "UMask": "0x3",15 "Counter": "0,1,2,3",16 "EventCode": "0x4",21 "UMask": "0xc",26 "Counter": "0,1,2,3",27 "EventCode": "0x1",32 "UMask": "0x8",37 "Counter": "0,1,2,3",[all …]
4 "Counter": "0,1,2,3",5 "EventCode": "0x1",9 "UMask": "0x8",14 "Counter": "0,1,2,3",15 "EventCode": "0x1",19 "UMask": "0x1",24 "Counter": "0,1,2,3",25 "EventCode": "0x1",29 "UMask": "0x2",34 "Counter": "0,1,2,3",[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */11 #define BVME_PIT_BASE 0xffa0000015 pad_a[3], pgcr,16 pad_b[3], psrr,17 pad_c[3], paddr,18 pad_d[3], pbddr,19 pad_e[3], pcddr,20 pad_f[3], pivr,21 pad_g[3], pacr,22 pad_h[3], pbcr,[all …]
4 "Counter": "0,1,2,3",5 "EventCode": "0x01",12 "Counter": "0,1,2,3",13 "EventCode": "0x17",17 "UMask": "0x1",22 "Counter": "0,1,2,3",23 "EventCode": "0x16",26 "UMask": "0x1",31 "Counter": "0,1,2,3",32 "EventCode": "0x18",[all …]
4 "Counter": "0,1,2,3",5 "EventCode": "0x01",12 "Counter": "0,1,2,3",13 "EventCode": "0x17",16 "UMask": "0x1",21 "Counter": "0,1,2,3",22 "EventCode": "0x16",25 "UMask": "0x1",30 "Counter": "0,1,2,3",31 "EventCode": "0x18",[all …]
4 "Counter": "0,1,2,3",5 "EventCode": "0x02",8 "UMask": "0xf7",13 "Counter": "0,1,2,3",14 "EventCode": "0x02",18 "UMask": "0xf1",23 "Counter": "0,1,2,3",24 "EventCode": "0x02",28 "UMask": "0xf4",33 "Counter": "0,1,2,3",[all …]
3 …ressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specifi…4 "Counter": "0,1,2,3",5 "EventCode": "0xB6",8 "UMask": "0x1"12 "Counter": "0,1,2,3",15 "EventCode": "0x14",19 "UMask": "0x1"23 "Counter": "0,1,2,3",24 "EventCode": "0x14",27 "UMask": "0x1"[all …]
4 "Counter": "0,1,2,3",7 "EventCode": "0x14",11 "UMask": "0x4"15 "Counter": "0,1,2,3",16 "EventCode": "0x14",20 "UMask": "0x1"24 "Counter": "0,1,2,3",25 "EventCode": "0x88",29 "UMask": "0xff"32 "BriefDescription": "Speculative and retired macro-conditional branches",[all …]