Lines Matching +full:0 +full:- +full:3
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
17 #include <asm/gpr-num.h>
23 * [20-19] : Op0
24 * [18-16] : Op1
25 * [15-12] : CRn
26 * [11-8] : CRm
27 * [7-5] : Op2
30 #define Op0_mask 0x3
32 #define Op1_mask 0x7
34 #define CRn_mask 0xf
36 #define CRm_mask 0xf
38 #define Op2_mask 0x7
68 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
69 (((x) << 8) & 0x00ff0000) | \
70 (((x) >> 8) & 0x0000ff00) | \
71 (((x) >> 24) & 0x000000ff))
84 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
87 * Op0 = 0, CRn = 4
90 * Rt = 0x1f
94 #define SET_PSTATE(x, r) __emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
96 #define PSTATE_PAN pstate_field(0, 4)
97 #define PSTATE_UAO pstate_field(0, 3)
98 #define PSTATE_SSBS pstate_field(3, 1)
99 #define PSTATE_DIT pstate_field(3, 2)
100 #define PSTATE_TCO pstate_field(3, 4)
113 /* Register-based PAN access, for save/restore purposes */
114 #define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3)
117 __emit_inst(0xd5000000 | \
119 ((Rt) & 0x1f))
121 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 3, 3, 0, 7, 31)
122 #define GSB_SYS_BARRIER_INSN __SYS_BARRIER_INSN(1, 0, 12, 0, 0, 31)
123 #define GSB_ACK_BARRIER_INSN __SYS_BARRIER_INSN(1, 0, 12, 0, 1, 31)
126 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
127 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
128 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
129 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
130 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
131 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
132 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
133 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
134 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
136 #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
137 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
138 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
140 #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
141 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
142 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
144 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
145 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
146 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
148 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
150 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
151 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
152 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
154 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
155 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
156 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
158 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
159 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
160 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
162 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
163 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
164 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
166 #define SYS_DC_CIVAPS sys_insn(1, 0, 7, 15, 1)
167 #define SYS_DC_CIGDVAPS sys_insn(1, 0, 7, 15, 5)
175 #include "asm/sysreg-defs.h"
181 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
182 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
183 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
185 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
186 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
187 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
188 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
189 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
191 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
192 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
193 #define OSLSR_EL1_OSLM_NI 0
194 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
197 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
198 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
199 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
200 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
201 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
202 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
203 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
204 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
205 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
206 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
208 #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
212 #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
213 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
214 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
216 #define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0)
217 #define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0)
218 #define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0)
219 #define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
220 #define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
221 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
224 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
225 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
226 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
227 #define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0)
230 #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
231 #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
232 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
233 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
234 #define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6)
235 #define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
236 #define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6)
237 #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
238 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
239 #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
240 #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
241 #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
242 #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
243 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
244 #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
245 #define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6)
246 #define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6)
247 #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
248 #define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1)
250 #define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0)
251 #define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1)
252 #define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
253 #define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0)
254 #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
255 #define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4)
256 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
259 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
260 #define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0)
261 #define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
262 #define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0)
263 #define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1)
264 #define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0)
265 #define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2)
266 #define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2)
267 #define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
268 #define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2)
269 #define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
270 #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
271 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
274 #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
276 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
277 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
278 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
280 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
281 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
282 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
284 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
285 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
286 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
287 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
289 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
290 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
291 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
292 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
294 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
295 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
297 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
298 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
300 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
302 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
303 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
304 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
306 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
307 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
308 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
309 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
310 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
311 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
312 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
313 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
314 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
315 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
316 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
317 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
318 #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
319 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
320 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
322 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
324 #define SYS_PAR_EL1_F BIT(0)
336 /* When PAR_EL1.F == 0 */
352 #define PMBSR_EL1_BUF_BSC_FULL 0x1UL
356 #define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
357 #define TRBSR_EL1_BSC_SHIFT 0
359 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
360 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
362 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
364 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
365 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
367 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
368 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
370 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
371 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
372 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
373 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
374 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
375 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
378 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
379 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
380 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
383 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
384 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
385 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
386 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
387 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
388 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
389 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
390 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
391 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
392 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
393 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
394 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
395 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
396 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
398 #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
400 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
402 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
404 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
405 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
407 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
408 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
409 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
410 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
411 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
412 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
413 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
414 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
415 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
416 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
417 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
418 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
420 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
421 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
422 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
424 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
427 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
428 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0)
431 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
434 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
435 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
438 * Group 0 of activity monitors (architected):
440 * Counter: 11 011 1101 010:n<3> n<2:0>
441 * Type: 11 011 1101 011:n<3> n<2:0>
442 * n: 0-15
446 * Counter: 11 011 1101 110:n<3> n<2:0>
447 * Type: 11 011 1101 111:n<3> n<2:0>
448 * n: 0-15
451 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
452 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
453 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
454 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
457 #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0)
460 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
462 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
464 #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
465 #define SYS_CNTVCT_EL0 sys_reg(3, 3, 14, 0, 2)
466 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
467 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
469 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
470 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
471 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
473 #define SYS_CNTV_TVAL_EL0 sys_reg(3, 3, 14, 3, 0)
474 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
475 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
477 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
478 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
479 #define SYS_AARCH32_CNTPCT sys_reg(0, 0, 0, 14, 0)
480 #define SYS_AARCH32_CNTVCT sys_reg(0, 1, 0, 14, 0)
481 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
482 #define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0)
483 #define SYS_AARCH32_CNTVCTSS sys_reg(0, 9, 0, 14, 0)
485 #define __PMEV_op2(n) ((n) & 0x7)
486 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
487 #define SYS_PMEVCNTSVRn_EL1(n) sys_reg(2, 0, 14, __CNTR_CRm(n), __PMEV_op2(n))
488 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
489 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
490 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
492 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
494 #define SYS_SPMCGCRn_EL1(n) sys_reg(2, 0, 9, 13, ((n) & 1))
496 #define __SPMEV_op2(n) ((n) & 0x7)
497 #define __SPMEV_crm(p, n) ((((p) & 7) << 1) | (((n) >> 3) & 1))
498 #define SYS_SPMEVCNTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n))
499 #define SYS_SPMEVFILT2Rn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n))
500 #define SYS_SPMEVFILTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n))
501 #define SYS_SPMEVTYPERn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n))
503 #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0)
504 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
506 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
507 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
508 #define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
509 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
510 #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
511 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
512 #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
513 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
515 #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
516 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
517 #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
518 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
519 #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
521 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
522 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
523 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
524 #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
525 #define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
526 #define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
527 #define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
528 #define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3)
529 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
530 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
531 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
532 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
533 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
534 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
535 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
537 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
538 #define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4)
540 #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
541 #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
543 #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
544 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
545 #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
546 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
547 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
548 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
551 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
553 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
554 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
557 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
559 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
560 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
561 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
562 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
563 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
565 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
566 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
569 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
575 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
576 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
579 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
585 #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
586 #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
587 #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
589 #define __AMEV_op2(m) (m & 0x7)
590 #define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3))
591 #define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
593 #define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
596 #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
597 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
598 #define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
599 #define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
600 #define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
601 #define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
602 #define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
603 #define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
606 #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
607 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
608 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
609 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
610 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
611 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
612 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
613 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
614 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
615 #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
616 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
617 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
618 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
619 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
620 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
621 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
622 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
623 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
624 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
625 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
626 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
628 #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
634 #define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
635 #define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
636 #define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
637 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
638 #define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
639 #define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
640 #define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
641 #define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
652 #define TLBI_Op1_EL1 0 /* Accessible from EL1 or higher */
658 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
659 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
660 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
661 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
662 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
663 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
664 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
665 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
667 #define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
668 #define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
669 #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
670 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
671 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
672 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
673 #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
674 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
675 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
676 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
677 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
678 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
679 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
680 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
681 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
682 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
683 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
684 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
685 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
686 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
687 #define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
688 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
689 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
690 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
691 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
692 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
693 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
694 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
695 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
696 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
697 #define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
698 #define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
699 #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
700 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
701 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
702 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
703 #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
704 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
705 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
706 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
707 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
708 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
709 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
710 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
711 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
712 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
713 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
714 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
715 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
716 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
717 #define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
718 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
719 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
720 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
721 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
722 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
723 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
724 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
725 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
726 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
727 #define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
728 #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
729 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
730 #define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
731 #define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
738 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
739 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
740 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
741 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
742 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
743 #define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
746 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
755 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
760 #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
761 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
762 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
763 #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
764 #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
771 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
772 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
773 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
774 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
775 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
776 #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
779 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
788 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
795 #define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
796 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
797 #define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
798 #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
802 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
803 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
804 #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
805 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
810 #define BRB_IALL_INSN __emit_inst(0xd5000000 | OP_BRB_IALL | (0x1f))
811 #define BRB_INJ_INSN __emit_inst(0xd5000000 | OP_BRB_INJ | (0x1f))
835 #define SCTLR_ELx_SA (BIT(3))
838 #define SCTLR_ELx_M (BIT(0))
849 #define ENDIAN_SET_EL2 0
864 #define ENDIAN_SET_EL1 0
881 #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00)
882 #define MAIR_ATTR_DEVICE_nGnRE UL(0x04)
883 #define MAIR_ATTR_NORMAL_NC UL(0x44)
884 #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0)
885 #define MAIR_ATTR_NORMAL UL(0xff)
886 #define MAIR_ATTR_MASK UL(0xff)
892 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0
894 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7
895 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0
896 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7
897 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1
899 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf
903 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0
904 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1
905 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2
906 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3
907 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7
945 #define SYS_GCR_EL1_EXCL_MASK 0xffffUL
950 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
952 #define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf)
953 #define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf)
963 #define SYS_RGSR_EL1_TAG_MASK 0xfUL
965 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL
968 #define SYS_TFSR_EL1_TF0_SHIFT 0
973 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
978 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
983 #define ICH_LR_STATE (3ULL << 62)
987 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
989 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
994 #define ICH_VMCR_FIQ_EN_SHIFT 3
1005 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
1006 #define ICH_VMCR_ENG0_SHIFT 0
1015 #define PIE_NONE_O UL(0x0)
1016 #define PIE_R_O UL(0x1)
1017 #define PIE_X_O UL(0x2)
1018 #define PIE_RX_O UL(0x3)
1019 #define PIE_RW_O UL(0x5)
1020 #define PIE_RWnX_O UL(0x6)
1021 #define PIE_RWX_O UL(0x7)
1022 #define PIE_R UL(0x8)
1023 #define PIE_GCS UL(0x9)
1024 #define PIE_RX UL(0xa)
1025 #define PIE_RW UL(0xc)
1026 #define PIE_RWX UL(0xe)
1027 #define PIE_MASK UL(0xf)
1036 #define POE_NONE UL(0x0)
1037 #define POE_R UL(0x1)
1038 #define POE_X UL(0x2)
1039 #define POE_RX UL(0x3)
1040 #define POE_W UL(0x4)
1041 #define POE_RW UL(0x5)
1042 #define POE_WX UL(0x6)
1043 #define POE_RWX UL(0x7)
1044 #define POE_MASK UL(0xf)
1060 #define GCS_CAP_TOKEN_MASK GENMASK(11, 0)
1061 #define GCS_CAP_TOKEN_SHIFT 0
1065 #define GCS_CAP_VALID_TOKEN 0x1
1066 #define GCS_CAP_IN_PROGRESS_TOKEN 0x5
1073 #define GICV5_OP_GIC_CDAFF sys_insn(1, 0, 12, 1, 3)
1074 #define GICV5_OP_GIC_CDDI sys_insn(1, 0, 12, 2, 0)
1075 #define GICV5_OP_GIC_CDDIS sys_insn(1, 0, 12, 1, 0)
1076 #define GICV5_OP_GIC_CDHM sys_insn(1, 0, 12, 2, 1)
1077 #define GICV5_OP_GIC_CDEN sys_insn(1, 0, 12, 1, 1)
1078 #define GICV5_OP_GIC_CDEOI sys_insn(1, 0, 12, 1, 7)
1079 #define GICV5_OP_GIC_CDPEND sys_insn(1, 0, 12, 1, 4)
1080 #define GICV5_OP_GIC_CDPRI sys_insn(1, 0, 12, 1, 2)
1081 #define GICV5_OP_GIC_CDRCFG sys_insn(1, 0, 12, 1, 5)
1082 #define GICV5_OP_GICR_CDIA sys_insn(1, 0, 12, 3, 0)
1088 #define GICV5_GIC_CDAFF_ID_MASK GENMASK_ULL(23, 0)
1092 #define GICV5_GIC_CDDI_ID_MASK GENMASK_ULL(23, 0)
1097 #define GICV5_GIC_CDDIS_ID_MASK GENMASK_ULL(23, 0)
1102 #define GICV5_GIC_CDEN_ID_MASK GENMASK_ULL(23, 0)
1107 #define GICV5_GIC_CDHM_ID_MASK GENMASK_ULL(23, 0)
1112 #define GICV5_GIC_CDPEND_ID_MASK GENMASK_ULL(23, 0)
1117 #define GICV5_GIC_CDPRI_ID_MASK GENMASK_ULL(23, 0)
1121 #define GICV5_GIC_CDRCFG_ID_MASK GENMASK_ULL(23, 0)
1127 #define GICV5_GIC_CDIA_ID_MASK GENMASK_ULL(23, 0)
1137 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
1141 __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
1163 __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) \
1169 __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) \
1194 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
1206 } while (0)
1219 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \
1227 } while (0)
1231 * set mask are set. Other bits are left as-is.
1238 } while (0)
1245 } while (0)
1252 } while (0)
1263 } while (0)