Lines Matching +full:0 +full:- +full:3
4 "Counter": "0,1,2,3",
7 "EventCode": "0x14",
11 "UMask": "0x4"
15 "Counter": "0,1,2,3",
16 "EventCode": "0x14",
20 "UMask": "0x1"
24 "Counter": "0,1,2,3",
25 "EventCode": "0x88",
29 "UMask": "0xff"
32 "BriefDescription": "Speculative and retired macro-conditional branches",
33 "Counter": "0,1,2,3",
34 "EventCode": "0x88",
36 "PublicDescription": "Speculative and retired macro-conditional branches.",
38 "UMask": "0xc1"
41 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
42 "Counter": "0,1,2,3",
43 "EventCode": "0x88",
45 …"PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and ind…
47 "UMask": "0xc2"
51 "Counter": "0,1,2,3",
52 "EventCode": "0x88",
56 "UMask": "0xd0"
60 "Counter": "0,1,2,3",
61 "EventCode": "0x88",
65 "UMask": "0xc4"
69 "Counter": "0,1,2,3",
70 "EventCode": "0x88",
73 "UMask": "0xc8"
76 "BriefDescription": "Not taken macro-conditional branches",
77 "Counter": "0,1,2,3",
78 "EventCode": "0x88",
80 "PublicDescription": "Not taken macro-conditional branches.",
82 "UMask": "0x41"
85 "BriefDescription": "Taken speculative and retired macro-conditional branches",
86 "Counter": "0,1,2,3",
87 "EventCode": "0x88",
89 "PublicDescription": "Taken speculative and retired macro-conditional branches.",
91 "UMask": "0x81"
94 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
95 "Counter": "0,1,2,3",
96 "EventCode": "0x88",
98 …"PublicDescription": "Taken speculative and retired macro-conditional branch instructions excludin…
100 "UMask": "0x82"
104 "Counter": "0,1,2,3",
105 "EventCode": "0x88",
109 "UMask": "0x90"
113 "Counter": "0,1,2,3",
114 "EventCode": "0x88",
118 "UMask": "0x84"
122 "Counter": "0,1,2,3",
123 "EventCode": "0x88",
127 "UMask": "0xa0"
131 "Counter": "0,1,2,3",
132 "EventCode": "0x88",
136 "UMask": "0x88"
140 "Counter": "0,1,2,3",
141 "EventCode": "0xC4",
148 "Counter": "0,1,2,3",
149 "EventCode": "0xC4",
153 "UMask": "0x4"
157 "Counter": "0,1,2,3",
158 "EventCode": "0xC4",
162 "UMask": "0x1"
166 "Counter": "0,1,2,3",
167 "EventCode": "0xC4",
171 "UMask": "0x40"
175 "Counter": "0,1,2,3",
176 "EventCode": "0xC4",
180 "UMask": "0x2"
183 …riefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
184 "Counter": "0,1,2,3",
185 "EventCode": "0xC4",
189 "UMask": "0x2"
193 "Counter": "0,1,2,3",
194 "EventCode": "0xC4",
198 "UMask": "0x8"
202 "Counter": "0,1,2,3",
203 "EventCode": "0xC4",
207 "UMask": "0x20"
211 "Counter": "0,1,2,3",
212 "EventCode": "0xC4",
216 "UMask": "0x10"
220 "Counter": "0,1,2,3",
221 "EventCode": "0x89",
225 "UMask": "0xff"
229 "Counter": "0,1,2,3",
230 "EventCode": "0x89",
234 "UMask": "0xc1"
238 "Counter": "0,1,2,3",
239 "EventCode": "0x89",
243 "UMask": "0xc4"
247 "Counter": "0,1,2,3",
248 "EventCode": "0x89",
250 …"PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Cou…
252 "UMask": "0xe4"
256 "Counter": "0,1,2,3",
257 "EventCode": "0x89",
261 "UMask": "0x41"
265 "Counter": "0,1,2,3",
266 "EventCode": "0x89",
270 "UMask": "0x81"
274 "Counter": "0,1,2,3",
275 "EventCode": "0x89",
279 "UMask": "0x84"
283 "Counter": "0,1,2,3",
284 "EventCode": "0x89",
288 "UMask": "0xa0"
292 "Counter": "0,1,2,3",
293 "EventCode": "0x89",
297 "UMask": "0x88"
301 "Counter": "0,1,2,3",
302 "EventCode": "0xC5",
309 "Counter": "0,1,2,3",
310 "EventCode": "0xC5",
314 "UMask": "0x4"
318 "Counter": "0,1,2,3",
319 "EventCode": "0xC5",
323 "UMask": "0x1"
327 "Counter": "0,1,2,3",
328 "EventCode": "0xC5",
332 "UMask": "0x20"
336 "Counter": "0,1,2,3",
337 "EventCode": "0x3C",
340 "UMask": "0x2"
344 "Counter": "0,1,2,3",
345 "EventCode": "0x3C",
349 "UMask": "0x1"
354 "Counter": "0,1,2,3",
355 "EventCode": "0x3C",
358 "UMask": "0x1"
362 "Counter": "0,1,2,3",
363 "EventCode": "0x3C",
366 "UMask": "0x2"
373 "UMask": "0x3"
377 "Counter": "0,1,2,3",
378 "EventCode": "0x3C",
382 "UMask": "0x1"
387 "Counter": "0,1,2,3",
388 "EventCode": "0x3C",
391 "UMask": "0x1"
398 "UMask": "0x2"
407 "UMask": "0x2"
411 "Counter": "0,1,2,3",
412 "EventCode": "0x3C",
420 "Counter": "0,1,2,3",
421 "EventCode": "0x3C",
430 "EventCode": "0xA3",
433 "UMask": "0x8"
439 "EventCode": "0xA3",
443 "UMask": "0x8"
447 "Counter": "0,1,2,3",
449 "EventCode": "0xA3",
452 "UMask": "0x1"
456 "Counter": "0,1,2,3",
458 "EventCode": "0xA3",
462 "UMask": "0x1"
466 "Counter": "0,1,2,3",
468 "EventCode": "0xA3",
472 "UMask": "0x2"
476 "Counter": "0,1,2,3",
478 "EventCode": "0xA3",
481 "UMask": "0x2"
485 "Counter": "0,1,2,3",
487 "EventCode": "0xA3",
491 "UMask": "0x4"
497 "EventCode": "0xA3",
500 "UMask": "0xc"
506 "EventCode": "0xA3",
508 "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.",
510 "UMask": "0xc"
514 "Counter": "0,1,2,3",
516 "EventCode": "0xA3",
519 "UMask": "0x5"
523 "Counter": "0,1,2,3",
525 "EventCode": "0xA3",
529 "UMask": "0x5"
533 "Counter": "0,1,2,3",
535 "EventCode": "0xA3",
538 "UMask": "0x6"
542 "Counter": "0,1,2,3",
544 "EventCode": "0xA3",
547 "UMask": "0x6"
551 "Counter": "0,1,2,3",
553 "EventCode": "0xA3",
556 "UMask": "0x4"
560 "Counter": "0,1,2,3",
561 "EventCode": "0x87",
565 "UMask": "0x4"
569 "Counter": "0,1,2,3",
570 "EventCode": "0x87",
573 "UMask": "0x1"
577 "Counter": "Fixed counter 0",
580 "UMask": "0x1"
583 … "BriefDescription": "Number of instructions retired. General Counter - architectural event",
584 "Counter": "0,1,2,3",
585 "EventCode": "0xC0",
593 "EventCode": "0xC0",
598 "UMask": "0x1"
602 "Counter": "0,1,2,3",
604 "EventCode": "0x0D",
607 "UMask": "0x3"
612 "Counter": "0,1,2,3",
614 "EventCode": "0x0D",
617 "UMask": "0x3"
621 "Counter": "0,1,2,3",
624 "EventCode": "0x0D",
627 "UMask": "0x3"
631 "Counter": "0,1,2,3",
632 "EventCode": "0x03",
636 "UMask": "0x8"
639 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
640 "Counter": "0,1,2,3",
641 "EventCode": "0x03",
645 "UMask": "0x2"
649 "Counter": "0,1,2,3",
650 "EventCode": "0x07",
654 "UMask": "0x1"
657 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
658 "Counter": "0,1,2,3",
659 "EventCode": "0x4C",
661 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefe…
663 "UMask": "0x2"
666 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
667 "Counter": "0,1,2,3",
668 "EventCode": "0x4C",
670 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefe…
672 "UMask": "0x1"
676 "Counter": "0,1,2,3",
678 "EventCode": "0xA8",
682 "UMask": "0x1"
686 "Counter": "0,1,2,3",
688 "EventCode": "0xA8",
692 "UMask": "0x1"
696 "Counter": "0,1,2,3",
697 "EventCode": "0xA8",
700 "UMask": "0x1"
704 "Counter": "0,1,2,3",
707 "EventCode": "0xC3",
710 "UMask": "0x1"
713 …el AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
714 "Counter": "0,1,2,3",
715 "EventCode": "0xC3",
717 …ed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
719 "UMask": "0x20"
722 "BriefDescription": "Self-modifying code (SMC) detected.",
723 "Counter": "0,1,2,3",
724 "EventCode": "0xC3",
726 "PublicDescription": "Number of self-modifying-code machine clears detected.",
728 "UMask": "0x4"
732 "Counter": "0,1,2,3",
733 "EventCode": "0x58",
736 "UMask": "0x1"
740 "Counter": "0,1,2,3",
741 "EventCode": "0x58",
744 "UMask": "0x4"
748 "Counter": "0,1,2,3",
749 "EventCode": "0xC1",
752 "UMask": "0x80"
755 "BriefDescription": "Resource-related stall cycles",
756 "Counter": "0,1,2,3",
757 "EventCode": "0xA2",
761 "UMask": "0x1"
764 "BriefDescription": "Cycles stalled due to re-order buffer full.",
765 "Counter": "0,1,2,3",
766 "EventCode": "0xA2",
769 "UMask": "0x10"
773 "Counter": "0,1,2,3",
774 "EventCode": "0xA2",
777 "UMask": "0x4"
781 "Counter": "0,1,2,3",
782 "EventCode": "0xA2",
786 "UMask": "0x8"
790 "Counter": "0,1,2,3",
791 "EventCode": "0xCC",
795 "UMask": "0x20"
799 "Counter": "0,1,2,3",
800 "EventCode": "0x5E",
804 "UMask": "0x1"
808 "Counter": "0,1,2,3",
811 "EventCode": "0x5E",
815 "UMask": "0x1"
818 "BriefDescription": "Cycles per thread when uops are dispatched to port 0",
819 "Counter": "0,1,2,3",
820 "EventCode": "0xA1",
822 "PublicDescription": "Cycles which a Uop is dispatched on port 0.",
824 "UMask": "0x1"
828 "BriefDescription": "Cycles per core when uops are dispatched to port 0",
829 "Counter": "0,1,2,3",
830 "EventCode": "0xA1",
832 "PublicDescription": "Cycles per core when uops are dispatched to port 0.",
834 "UMask": "0x1"
838 "Counter": "0,1,2,3",
839 "EventCode": "0xA1",
843 "UMask": "0x2"
848 "Counter": "0,1,2,3",
849 "EventCode": "0xA1",
853 "UMask": "0x2"
857 "Counter": "0,1,2,3",
858 "EventCode": "0xA1",
862 "UMask": "0xc"
867 "Counter": "0,1,2,3",
868 "EventCode": "0xA1",
871 "UMask": "0xc"
874 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",
875 "Counter": "0,1,2,3",
876 "EventCode": "0xA1",
878 "PublicDescription": "Cycles which a Uop is dispatched on port 3.",
880 "UMask": "0x30"
884 "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",
885 "Counter": "0,1,2,3",
886 "EventCode": "0xA1",
888 "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
890 "UMask": "0x30"
894 "Counter": "0,1,2,3",
895 "EventCode": "0xA1",
899 "UMask": "0x40"
904 "Counter": "0,1,2,3",
905 "EventCode": "0xA1",
909 "UMask": "0x40"
913 "Counter": "0,1,2,3",
914 "EventCode": "0xA1",
918 "UMask": "0x80"
923 "Counter": "0,1,2,3",
924 "EventCode": "0xA1",
928 "UMask": "0x80"
932 "Counter": "0,1,2,3",
933 "EventCode": "0xB1",
935 "PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
937 "UMask": "0x2"
940 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
941 "Counter": "0,1,2,3",
943 "EventCode": "0xB1",
945 … "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
947 "UMask": "0x2"
950 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
951 "Counter": "0,1,2,3",
953 "EventCode": "0xB1",
955 … "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
957 "UMask": "0x2"
960 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
961 "Counter": "0,1,2,3",
962 "CounterMask": "3",
963 "EventCode": "0xB1",
965 … "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
967 "UMask": "0x2"
970 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
971 "Counter": "0,1,2,3",
973 "EventCode": "0xB1",
975 … "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
977 "UMask": "0x2"
980 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
981 "Counter": "0,1,2,3",
982 "EventCode": "0xB1",
985 "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.",
987 "UMask": "0x2"
990 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
991 "Counter": "0,1,2,3",
993 "EventCode": "0xB1",
995 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
997 "UMask": "0x1"
1000 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1001 "Counter": "0,1,2,3",
1003 "EventCode": "0xB1",
1005 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
1007 "UMask": "0x1"
1010 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1011 "Counter": "0,1,2,3",
1012 "CounterMask": "3",
1013 "EventCode": "0xB1",
1015 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1017 "UMask": "0x1"
1020 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1021 "Counter": "0,1,2,3",
1023 "EventCode": "0xB1",
1025 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1027 "UMask": "0x1"
1031 "Counter": "0,1,2,3",
1033 "EventCode": "0xB1",
1037 "UMask": "0x1"
1040 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1041 "Counter": "0,1,2,3",
1042 "EventCode": "0xB1",
1044 …"PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask …
1046 "UMask": "0x1"
1050 "Counter": "0,1,2,3",
1051 "EventCode": "0x0E",
1055 "UMask": "0x1"
1060 "Counter": "0,1,2,3",
1062 "EventCode": "0x0E",
1067 "UMask": "0x1"
1070 "BriefDescription": "Number of flags-merge uops being allocated.",
1071 "Counter": "0,1,2,3",
1072 "EventCode": "0x0E",
1074 "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.",
1076 "UMask": "0x10"
1080 "Counter": "0,1,2,3",
1081 "EventCode": "0x0E",
1085 "UMask": "0x40"
1088 …w LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sour…
1089 "Counter": "0,1,2,3",
1090 "EventCode": "0x0E",
1092 …"PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2…
1094 "UMask": "0x20"
1098 "Counter": "0,1,2,3",
1100 "EventCode": "0x0E",
1105 "UMask": "0x1"
1109 "Counter": "0,1,2,3",
1110 "EventCode": "0xC2",
1114 "UMask": "0x1"
1119 "Counter": "0,1,2,3",
1121 "EventCode": "0xC2",
1125 "UMask": "0x1"
1129 "Counter": "0,1,2,3",
1130 "EventCode": "0xC2",
1134 "UMask": "0x2"
1138 "Counter": "0,1,2,3",
1140 "EventCode": "0xC2",
1144 "UMask": "0x1"
1148 "Counter": "0,1,2,3",
1150 "EventCode": "0xC2",
1154 "UMask": "0x1"