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/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c1 // SPDX-License-Identifier: MIT
35 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
47 memset(pps_header, 0, sizeof(*pps_header)); in drm_dsc_dp_pps_header_init()
49 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
50 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
55 * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
57 * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
60 * buffer size in bytes, or 0 on invalid input
76 return 0; in drm_dsc_dp_rc_buffer_size()
82 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
[all …]
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra234.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
16 #include "pinctrl-tegra.h"
1382 #define PINGROUP_REG_N(r) -1
1385 #define DRV_PINGROUP_N(r) -1
1388 .drv_reg = -1, \
1389 .drv_bank = -1, \
1390 .drvdn_bit = -1, \
1391 .drvup_bit = -1, \
1392 .slwr_bit = -1, \
[all …]
H A Dpinctrl-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
23 #include "pinctrl-tegra.h"
1281 #define PINGROUP_REG_N(r) -1
1284 #define DRV_PINGROUP_N(r) -1
1287 .drv_reg = -1, \
1288 .drv_bank = -1, \
1289 .drvdn_bit = -1, \
1290 .drvup_bit = -1, \
1291 .slwr_bit = -1, \
[all …]
/linux/drivers/media/platform/ti/omap3isp/
H A Dcfa_coef_table.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - CFA coefficients table
7 * Copyright (C) 2009-2010 Nokia Corporation
13 { 244, 0, 247, 0, 12, 27, 36, 247, 250, 0, 27, 0, 4, 250, 12, 244,
14 248, 0, 0, 0, 0, 40, 0, 0, 244, 12, 250, 4, 0, 27, 0, 250,
15 247, 36, 27, 12, 0, 247, 0, 244, 0, 0, 40, 0, 0, 0, 0, 248,
16 244, 0, 247, 0, 12, 27, 36, 247, 250, 0, 27, 0, 4, 250, 12, 244,
17 248, 0, 0, 0, 0, 40, 0, 0, 244, 12, 250, 4, 0, 27, 0, 250,
18 247, 36, 27, 12, 0, 247, 0, 244, 0, 0, 40, 0, 0, 0, 0, 248,
19 244, 0, 247, 0, 12, 27, 36, 247, 250, 0, 27, 0, 4, 250, 12, 244,
[all …]
/linux/arch/powerpc/crypto/
H A Dcurve25519-ppc64le_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 # [1] https://github.com/dot-asm/cryptogams/
11 # Copyright (c) 2006-2017, CRYPTOGAMS by <appro@openssl.org>
58 # - Added x25519_fe51_sqr_times, x25519_fe51_frombytes, x25519_fe51_tobytes
61 # Copyright 2024- IBM Corp.
63 # X25519 lower-level primitives for PPC64.
73 stdu 1,-144(1)
86 ld 6,0(5)
87 ld 7,0(4)
109 mulld 12,11,4
[all …]
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
16 # clamp r &= 0x0FFFFFFC0FFFFFFC 0x0FFFFFFC0FFFFFFF
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
[all …]
/linux/drivers/pmdomain/mediatek/
H A Dmt8195-pm-domains.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
10 #include "mtk-pm-domains.h"
11 #include <dt-bindings/power/mt8195-power.h>
21 .ctl_offs = 0x328,
22 .pwr_sta_offs = 0x174,
23 .pwr_sta2nd_offs = 0x178,
25 .sram_pdn_ack_bits = GENMASK(12, 12),
41 .sta_mask = BIT(12),
42 .ctl_offs = 0x32C,
[all …]
H A Dmt8192-pm-domains.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include "mtk-pm-domains.h"
7 #include <dt-bindings/power/mt8192-power.h>
17 .ctl_offs = 0x0354,
18 .pwr_sta_offs = 0x016c,
19 .pwr_sta2nd_offs = 0x0170,
21 .sram_pdn_ack_bits = GENMASK(12, 12),
33 .ctl_offs = 0x0304,
34 .pwr_sta_offs = 0x016c,
35 .pwr_sta2nd_offs = 0x0170,
[all …]
H A Dmt8183-pm-domains.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include "mtk-pm-domains.h"
7 #include <dt-bindings/power/mt8183-power.h>
17 .ctl_offs = 0x0314,
18 .pwr_sta_offs = 0x0180,
19 .pwr_sta2nd_offs = 0x0184,
21 .sram_pdn_ack_bits = GENMASK(15, 12),
26 .ctl_offs = 0x032c,
27 .pwr_sta_offs = 0x0180,
28 .pwr_sta2nd_offs = 0x0184,
[all …]
/linux/sound/ppc/
H A Dburgundy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #define MASK_ADDR_BURGUNDY_INPBOOST (0x10 << 12)
13 #define MASK_ADDR_BURGUNDY_INPSEL21 (0x11 << 12)
14 #define MASK_ADDR_BURGUNDY_INPSEL3 (0x12 << 12)
16 #define MASK_ADDR_BURGUNDY_GAINCH1 (0x13 << 12)
17 #define MASK_ADDR_BURGUNDY_GAINCH2 (0x14 << 12)
18 #define MASK_ADDR_BURGUNDY_GAINCH3 (0x15 << 12)
19 #define MASK_ADDR_BURGUNDY_GAINCH4 (0x16 << 12)
21 #define MASK_ADDR_BURGUNDY_VOLCH1 (0x20 << 12)
22 #define MASK_ADDR_BURGUNDY_VOLCH2 (0x21 << 12)
[all …]
/linux/drivers/tty/serial/8250/
H A D8250_boca.c1 // SPDX-License-Identifier: GPL-2.0
4 * Data taken from include/asm-i386/serial.h
13 SERIAL8250_PORT(0x100, 12),
14 SERIAL8250_PORT(0x108, 12),
15 SERIAL8250_PORT(0x110, 12),
16 SERIAL8250_PORT(0x118, 12),
17 SERIAL8250_PORT(0x120, 12),
18 SERIAL8250_PORT(0x128, 12),
19 SERIAL8250_PORT(0x130, 12),
20 SERIAL8250_PORT(0x138, 12),
[all …]
/linux/drivers/net/dsa/
H A Dmv88e6060.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * drivers/net/dsa/mv88e6060.h - Marvell 88e6060 switch chip support
15 #define REG_PORT(p) (0x8 + (p))
16 #define PORT_STATUS 0x00
21 #define PORT_STATUS_LINK BIT(12)
26 #define PORT_SWITCH_ID 0x03
27 #define PORT_SWITCH_ID_6060 0x0600
28 #define PORT_SWITCH_ID_6060_MASK 0xfff0
29 #define PORT_SWITCH_ID_6060_R1 0x0601
30 #define PORT_SWITCH_ID_6060_R2 0x0602
[all …]
/linux/sound/soc/codecs/
H A Drt5677.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5677.h -- RT5677 ALSA SoC audio driver
16 #define RT5677_RESET 0x00
17 #define RT5677_VENDOR_ID 0xfd
18 #define RT5677_VENDOR_ID1 0xfe
19 #define RT5677_VENDOR_ID2 0xff
20 /* I/O - Output */
21 #define RT5677_LOUT1 0x01
22 /* I/O - Input */
23 #define RT5677_IN1 0x03
[all …]
H A Drt5640.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5640.h -- RT5640 ALSA SoC audio driver
15 #include <dt-bindings/sound/rt5640.h>
18 #define RT5640_RESET 0x00
19 #define RT5640_VENDOR_ID 0xfd
20 #define RT5640_VENDOR_ID1 0xfe
21 #define RT5640_VENDOR_ID2 0xff
22 /* I/O - Output */
23 #define RT5640_SPK_VOL 0x01
24 #define RT5640_HP_VOL 0x02
[all …]
H A Drt5651.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5651.h -- RT5651 ALSA SoC audio driver
12 #include <dt-bindings/sound/rt5651.h>
15 #define RT5651_RESET 0x00
16 #define RT5651_VERSION_ID 0xfd
17 #define RT5651_VENDOR_ID 0xfe
18 #define RT5651_DEVICE_ID 0xff
19 /* I/O - Output */
20 #define RT5651_HP_VOL 0x02
21 #define RT5651_LOUT_CTRL1 0x03
[all …]
H A Drt5665.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver
14 #define DEVICE_ID 0x6451
17 #define RT5665_RESET 0x0000
18 #define RT5665_VENDOR_ID 0x00fd
19 #define RT5665_VENDOR_ID_1 0x00fe
20 #define RT5665_DEVICE_ID 0x00ff
21 /* I/O - Output */
22 #define RT5665_LOUT 0x0001
23 #define RT5665_HP_CTRL_1 0x0002
[all …]
/linux/drivers/iio/adc/
H A Dad7091r8.c1 // SPDX-License-Identifier: GPL-2.0
3 * Analog Devices AD7091R8 12-bit SAR ADC driver
15 #include "ad7091r-base.h"
19 #define AD7091R8_REG_DATA_MSK GENMASK(9, 0)
31 /* AD7091R-2/-4/-8 don't set sample/command/autocycle mode in conf reg */ in ad7091r8_set_mode()
32 st->mode = mode; in ad7091r8_set_mode()
33 return 0; in ad7091r8_set_mode()
68 AD7091R_CHANNEL(0, 12, NULL, 0),
69 AD7091R_CHANNEL(1, 12, NULL, 0),
73 AD7091R_CHANNEL(0, 12, NULL, 0),
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_qp_tables.c1 // SPDX-License-Identifier: MIT
24 /* from BPP 4 to 12 in steps of 0.5 */
39 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
40 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
41 { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
42 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
43 { 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
44 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
45 { 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
46 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8167.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include "pinctrl-mtk-common.h"
15 #include "pinctrl-mtk-mt8167.h"
18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
22 /* E8E4E2 2/4/6/8/10/12/14/16 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
27 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
28 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
[all …]
H A Dpinctrl-mt8516.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include "pinctrl-mtk-common.h"
15 #include "pinctrl-mtk-mt8516.h"
18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
22 /* E8E4E2 2/4/6/8/10/12/14/16 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
27 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
28 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
[all …]
H A Dpinctrl-mt2712.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/pinctrl/pinconf-generic.h>
14 #include <dt-bindings/pinctrl/mt65xx.h>
16 #include "pinctrl-mtk-common.h"
17 #include "pinctrl-mtk-mt2712.h"
20 MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
21 MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
22 MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
23 MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
24 MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dsc/
H A Drc_calc_fpu.c57 num = num - 0.5; in dsc_roundf()
69 int table_size = 0; in get_qp_set()
80 TABLE_CASE(444, 12, max); in get_qp_set()
81 TABLE_CASE(444, 12, min); in get_qp_set()
86 TABLE_CASE(422, 12, max); in get_qp_set()
87 TABLE_CASE(422, 12, min); in get_qp_set()
92 TABLE_CASE(420, 12, max); in get_qp_set()
93 TABLE_CASE(420, 12, min); in get_qp_set()
99 index = (bpp - table[0].bpp) * 2; in get_qp_set()
115 …0) : ((((bpp >= 8) && (bpp <= 12))) ? (2) : ((bpp >= 15) ? (10) : ((((bpp > 6) && (bpp < 8))) ? (… in get_ofs_set()
[all …]
/linux/arch/arm/mach-davinci/
H A Dda830.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <linux/irqchip/irq-davinci-cp-intc.h>
16 #include <clocksource/timer-davinci.h>
27 #define DA830_CMP12_0 0x60
28 #define DA830_CMP12_1 0x64
29 #define DA830_CMP12_2 0x68
30 #define DA830_CMP12_3 0x6c
31 #define DA830_CMP12_4 0x70
32 #define DA830_CMP12_5 0x74
[all …]
/linux/lib/crypto/
H A Dchacha.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 WARN_ON_ONCE(nrounds != 20 && nrounds != 12); in chacha_permute()
23 for (i = 0; i < nrounds; i += 2) { in chacha_permute()
24 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute()
29 x[8] += x[12]; x[4] = rol32(x[4] ^ x[8], 12); in chacha_permute()
30 x[9] += x[13]; x[5] = rol32(x[5] ^ x[9], 12); in chacha_permute()
31 x[10] += x[14]; x[6] = rol32(x[6] ^ x[10], 12); in chacha_permute()
32 x[11] += x[15]; x[7] = rol32(x[7] ^ x[11], 12); in chacha_permute()
34 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 8); in chacha_permute()
39 x[8] += x[12]; x[4] = rol32(x[4] ^ x[8], 7); in chacha_permute()
[all …]
/linux/arch/riscv/kernel/probes/
H A Dsimulate-insn.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include "decode-insn.h"
8 #include "simulate-insn.h"
13 if (index == 0) in rv_insn_reg_get_val()
14 *ptr = 0; in rv_insn_reg_get_val()
26 if (index == 0) in rv_insn_reg_set_val()
39 * 31 30 21 20 19 12 11 7 6 0 in simulate_jal()
40 * imm [20] | imm[10:1] | imm[11] | imm[19:12] | rd | opcode in simulate_jal()
45 u32 index = (opcode >> 7) & 0x1f; in simulate_jal()
51 imm = ((opcode >> 21) & 0x3ff) << 1; in simulate_jal()
[all …]

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