1 // SPDX-License-Identifier: GPL-2.0+
7 #include "decode-insn.h"
8 #include "simulate-insn.h"
13 	if (index == 0)  in rv_insn_reg_get_val()
14 		*ptr = 0;  in rv_insn_reg_get_val()
26 	if (index == 0)  in rv_insn_reg_set_val()
39 	 *     31    30       21    20     19        12 11 7 6      0  in simulate_jal()
40 	 * imm [20] | imm[10:1] | imm[11] | imm[19:12] | rd | opcode  in simulate_jal()
45 	u32 index = (opcode >> 7) & 0x1f;  in simulate_jal()
51 	imm  = ((opcode >> 21) & 0x3ff) << 1;  in simulate_jal()
52 	imm |= ((opcode >> 20) & 0x1)   << 11;  in simulate_jal()
53 	imm |= ((opcode >> 12) & 0xff)  << 12;  in simulate_jal()
54 	imm |= ((opcode >> 31) & 0x1)   << 20;  in simulate_jal()
64 	 * 31          20 19 15 14 12 11 7 6      0  in simulate_jalr()
65 	 *  offset[11:0] | rs1 | 010 | rd | opcode  in simulate_jalr()
66 	 *      12         5      3    5    JALR/JR  in simulate_jalr()
70 	u32 imm = (opcode >> 20) & 0xfff;  in simulate_jalr()
71 	u32 rd_index = (opcode >> 7) & 0x1f;  in simulate_jalr()
72 	u32 rs1_index = (opcode >> 15) & 0x1f;  in simulate_jalr()
88 	((opcode >> 7) & 0x1f)
91 	((((opcode) >> 12) & 0xfffff) << 12)
105 	 *  31        12 11 7 6      0  in simulate_auipc()
106 	 * | imm[31:12] | rd | opcode |  in simulate_auipc()
122 	(((opcode) >> 15) & 0x1f)
125 	(((opcode) >> 20) & 0x1f)
128 	(((opcode) >> 12) & 0x7)
131 	(((((opcode) >>  8) & 0xf ) <<  1) | \
132 	 ((((opcode) >> 25) & 0x3f) <<  5) | \
133 	 ((((opcode) >>  7) & 0x1 ) << 11) | \
134 	 ((((opcode) >> 31) & 0x1 ) << 12))
137 	sign_extend32((branch_imm(opcode)), 12)
143 	 *      31    30       25 24 20 19 15 14    12 11       8    7      6      0  in simulate_branch()
144 	 * | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode |  in simulate_branch()
146 	 *     imm[12|10:5]        rs2   rs1    000       imm[4:1|11]       1100011  BEQ  in simulate_branch()
147 	 *     imm[12|10:5]        rs2   rs1    001       imm[4:1|11]       1100011  BNE  in simulate_branch()
148 	 *     imm[12|10:5]        rs2   rs1    100       imm[4:1|11]       1100011  BLT  in simulate_branch()
149 	 *     imm[12|10:5]        rs2   rs1    101       imm[4:1|11]       1100011  BGE  in simulate_branch()
150 	 *     imm[12|10:5]        rs2   rs1    110       imm[4:1|11]       1100011  BLTU  in simulate_branch()
151 	 *     imm[12|10:5]        rs2   rs1    111       imm[4:1|11]       1100011  BGEU  in simulate_branch()
195 	 *  15    13 12                            2 1      0  in simulate_c_j()
202 	offset  = ((opcode >> 3)  & 0x7) << 1;  in simulate_c_j()
203 	offset |= ((opcode >> 11) & 0x1) << 4;  in simulate_c_j()
204 	offset |= ((opcode >> 2)  & 0x1) << 5;  in simulate_c_j()
205 	offset |= ((opcode >> 7)  & 0x1) << 6;  in simulate_c_j()
206 	offset |= ((opcode >> 6)  & 0x1) << 7;  in simulate_c_j()
207 	offset |= ((opcode >> 9)  & 0x3) << 8;  in simulate_c_j()
208 	offset |= ((opcode >> 8)  & 0x1) << 10;  in simulate_c_j()
209 	offset |= ((opcode >> 12) & 0x1) << 11;  in simulate_c_j()
220 	 *  15    12 11  7 6   2 1  0  in simulate_c_jr_jalr()
227 	u32 rs1 = (opcode >> 7) & 0x1f;  in simulate_c_jr_jalr()
229 	if (rs1 == 0) /* C.JR is only valid when rs1 != x0 */  in simulate_c_jr_jalr()
257 	 *  15    13 12           10 9    7 6                 2 1  0  in simulate_c_bnez_beqz()
266 	rs1 = 0x8 | ((opcode >> 7) & 0x7);  in simulate_c_bnez_beqz()
271 	if ((rs1_val != 0 && is_bnez) || (rs1_val == 0 && !is_bnez)) {  in simulate_c_bnez_beqz()
272 		offset =  ((opcode >> 3)  & 0x3) << 1;  in simulate_c_bnez_beqz()
273 		offset |= ((opcode >> 10) & 0x3) << 3;  in simulate_c_bnez_beqz()
274 		offset |= ((opcode >> 2)  & 0x1) << 5;  in simulate_c_bnez_beqz()
275 		offset |= ((opcode >> 5)  & 0x3) << 6;  in simulate_c_bnez_beqz()
276 		offset |= ((opcode >> 12) & 0x1) << 8;  in simulate_c_bnez_beqz()