| /linux/sound/drivers/ |
| H A D | serial-u16550.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Added support for the Midiator MS-124T and for the MS-124W in
17 * More documentation can be found in serial-u16550.txt.
39 #define SNDRV_SERIAL_MS124T 1 /* Midiator MS-124T */
40 #define SNDRV_SERIAL_MS124W_SA 2 /* Midiator MS-12
157 snd_uart16550_add_timer(struct snd_uart16550 * uart) snd_uart16550_add_timer() argument
166 snd_uart16550_del_timer(struct snd_uart16550 * uart) snd_uart16550_del_timer() argument
175 snd_uart16550_buffer_output(struct snd_uart16550 * uart) snd_uart16550_buffer_output() argument
192 snd_uart16550_io_loop(struct snd_uart16550 * uart) snd_uart16550_io_loop() argument
281 struct snd_uart16550 *uart; snd_uart16550_interrupt() local
300 struct snd_uart16550 *uart; snd_uart16550_buffer_timer() local
314 snd_uart16550_detect(struct snd_uart16550 * uart) snd_uart16550_detect() argument
357 snd_uart16550_do_open(struct snd_uart16550 * uart) snd_uart16550_do_open() argument
449 snd_uart16550_do_close(struct snd_uart16550 * uart) snd_uart16550_do_close() argument
503 struct snd_uart16550 *uart = substream->rmidi->private_data; snd_uart16550_input_open() local
517 struct snd_uart16550 *uart = substream->rmidi->private_data; snd_uart16550_input_close() local
532 struct snd_uart16550 *uart = substream->rmidi->private_data; snd_uart16550_input_trigger() local
545 struct snd_uart16550 *uart = substream->rmidi->private_data; snd_uart16550_output_open() local
559 struct snd_uart16550 *uart = substream->rmidi->private_data; snd_uart16550_output_close() local
570 snd_uart16550_buffer_can_write(struct snd_uart16550 * uart,int Num) snd_uart16550_buffer_can_write() argument
579 snd_uart16550_write_buffer(struct snd_uart16550 * uart,unsigned char byte) snd_uart16550_write_buffer() argument
596 snd_uart16550_output_byte(struct snd_uart16550 * uart,struct snd_rawmidi_substream * substream,unsigned char midi_byte) snd_uart16550_output_byte() argument
637 struct snd_uart16550 *uart = substream->rmidi->private_data; snd_uart16550_output_write() local
728 struct snd_uart16550 *uart = substream->rmidi->private_data; snd_uart16550_output_trigger() local
763 struct snd_uart16550 *uart; snd_uart16550_create() local
833 snd_uart16550_rmidi(struct snd_uart16550 * uart,int device,int outs,int ins,struct snd_rawmidi ** rmidi) snd_uart16550_rmidi() argument
863 struct snd_uart16550 *uart; snd_serial_probe() local
[all...] |
| /linux/Documentation/devicetree/bindings/serial/ |
| H A D | mediatek,uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
10 - Matthias Brugger <matthias.bgg@gmail.com>
13 - $ref: serial.yaml#
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
24 - items:
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| H A D | samsung_uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - enum:
22 - apple,s5l-uart
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| H A D | amlogic,meson-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson SoC UART Serial Interface
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
15 of SoCs, and can be present either in the "Always-On" power domain or the
16 "Everything-Else" power domain.
18 The particularity of the "Always-On" Serial Interface is that the hardware
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|
| H A D | snps-dw-apb-uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare ABP UART
10 - Rob Herring <robh@kernel.org>
13 - $ref: serial.yaml#
14 - $ref: rs485.yaml#
16 - if:
20 - {}
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|
| H A D | fsl-imx-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
10 - Fabio Estevam <festevam@gmail.com>
15 - const: fsl,imx1-uart
16 - const: fsl,imx21-uart
17 - items:
18 - enum:
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|
| H A D | marvell,armada-3700-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/marvell,armada-3700-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Armada-3700 UART
10 - Pali Rohár <pali@kernel.org>
13 Marvell UART is a non standard UART used in some of Marvell EBU SoCs (e.g.
14 Armada-3700).
19 - marvell,armada-3700-uart
20 - marvell,armada-3700-uart-ext
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|
| H A D | 8250.yaml | 3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter)
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
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|
| H A D | brcm,bcm7271-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Al Cooper <alcooperx@gmail.com>
13 - $ref: serial.yaml#
16 The Broadcom UART is based on the basic 8250 UART but with
23 - enum:
24 - brcm,bcm7271-uart
25 - brcm,bcm7278-uart
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|
| H A D | ingenic,uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/ingenic,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs UART controller
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: serial.yaml#
17 pattern: "^serial@[0-9a-f]+$"
21 - enum:
22 - ingenic,jz4740-uart
[all …]
|
| /linux/drivers/tty/serial/ |
| H A D | men_z135_uart.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * MEN 16z135 High Speed UART
104 MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)");
108 MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)");
131 * men_z135_reg_set() - Set value in register
132 * @uart: The UART port
136 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
139 struct uart_port *port = &uart->port; in men_z135_reg_set()
143 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
145 reg = ioread32(port->membase + addr); in men_z135_reg_set()
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|
| H A D | timbuart.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
55 struct timbuart_port *uart = in timbuart_start_tx() local
58 /* do not transfer anything here -> fire off the tasklet */ in timbuart_start_tx()
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
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|
| H A D | liteuart.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
25 * The definitions below are true for LiteX SoC configured for 8-bit CSR Bus,
26 * 32-bit aligned.
73 struct liteuart_port *uart = to_liteuart_port(port); in liteuart_update_irq_reg() local
76 uart->irq_reg |= mask; in liteuart_update_irq_reg()
78 uart->irq_reg &= ~mask; in liteuart_update_irq_reg()
80 if (port->irq) in liteuart_update_irq_reg()
81 litex_write8(port->membase + OFF_EV_ENABLE, uart->irq_reg); in liteuart_update_irq_reg()
96 struct liteuart_port *uart = to_liteuart_port(port); in liteuart_stop_rx() local
[all …]
|
| /linux/drivers/tty/serial/8250/ |
| H A D | 8250_tegra.c | 1 // SPDX-License-Identifier: GPL-2.0+
31 status = p->serial_in(p, UART_LSR); in tegra_uart_handle_break()
35 p->serial_in(p, UART_RX); in tegra_uart_handle_break()
37 if (--tmout == 0) in tegra_uart_handle_break()
46 struct tegra_uart *uart; in tegra_uart_probe() local
51 uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL); in tegra_uart_probe()
52 if (!uart) in tegra_uart_probe()
53 return -ENOMEM; in tegra_uart_probe()
58 spin_lock_init(&port->lock); in tegra_uart_probe()
60 port->flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_FIXED_TYPE; in tegra_uart_probe()
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|
| H A D | 8250_lpc18xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Serial port driver for NXP LPC18xx/43xx UART
43 if (rs485->flags & SER_RS485_ENABLED) { in lpc18xx_rs485_config()
47 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpc18xx_rs485_config()
51 if (rs485->delay_rts_after_send) { in lpc18xx_rs485_config()
52 baud_clk = port->uartclk / up->dl_read(up); in lpc18xx_rs485_config()
53 rs485_dly_reg = DIV_ROUND_UP(rs485->delay_rts_after_send in lpc18xx_rs485_config()
60 rs485->delay_rts_after_send = (rs485_dly_reg * MSEC_PER_SEC) in lpc18xx_rs485_config()
80 offset = offset << p->regshift; in lpc18xx_uart_serial_out()
81 writel(value, p->membase + offset); in lpc18xx_uart_serial_out()
[all …]
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| H A D | 8250_ingenic.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
6 * Ingenic SoC UART support
46 return readl(port->membase + (offset << 2)); in early_in()
51 writel(value, port->membase + (offset << 2)); in early_out()
68 uart_console_write(&early_device->port, s, count, in ingenic_early_console_write()
82 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); in ingenic_early_console_setup_clock()
86 dev->port.uartclk = be32_to_cpup(prop); in ingenic_early_console_setup_clock()
92 struct uart_port *port = &dev->port; in ingenic_earlycon_setup_tail()
96 if (!dev->port.membase) in ingenic_earlycon_setup_tail()
[all …]
|
| H A D | 8250_pxa.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
37 serial8250_suspend_port(data->line); in serial_pxa_suspend()
46 serial8250_resume_port(data->line); in serial_pxa_resume()
56 { .compatible = "mrvl,pxa-uart", },
57 { .compatible = "mrvl,mmp-uart", },
62 /* Uart divisor latch write */
82 struct pxa8250_data *data = port->private_data; in serial_pxa_pm()
85 clk_prepare_enable(data->clk); in serial_pxa_pm()
87 clk_disable_unprepare(data->clk); in serial_pxa_pm()
[all …]
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| H A D | 8250_dfl.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA UART
45 return -EINVAL; in dfh_get_u64_param_val()
52 static int dfl_uart_get_params(struct dfl_device *dfl_dev, struct uart_8250_port *uart) in dfl_uart_get_params() argument
54 struct device *dev = &dfl_dev->dev; in dfl_uart_get_params()
63 uart->port.uartclk = clk_freq; in dfl_uart_get_params()
71 uart->port.type = PORT_ALTR_16550_F32; in dfl_uart_get_params()
75 uart->port.type = PORT_ALTR_16550_F64; in dfl_uart_get_params()
79 uart->port.type = PORT_ALTR_16550_F128; in dfl_uart_get_params()
83 return dev_err_probe(dev, -EINVAL, "unsupported FIFO_LEN %llu\n", fifo_len); in dfl_uart_get_params()
[all …]
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| H A D | 8250_hp300.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * by Kars de Jong <jongk@linux-m68k.org>, May 2004.
63 /* Offset to UART registers from base of DCA */
78 * Where we find the 8250-like APCI ports, and how far apart they are.
139 /* Enable board-interrupts */ in hp300_setup_serial_console()
160 struct uart_8250_port uart; in hpdca_init_one() local
164 if (hp300_uart_scode == d->scode) { in hpdca_init_one()
169 memset(&uart, 0, sizeof(uart)); in hpdca_init_one()
172 uart.port.iotype = UPIO_MEM; in hpdca_init_one()
173 uart.port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF; in hpdca_init_one()
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| H A D | 8250_ni.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * NI 16550 UART Driver
5 * The National Instruments (NI) 16550 is a UART that is compatible with the
7 * for RS-485 transceiver control. This driver implements support for the
10 * Copyright 2012-2023 National Instruments Corporation
31 /* TFS - TX FIFO Size */
33 /* RFS - RX FIFO Size */
36 /* PMR - Port Mode Register */
38 /* PMR[1:0] - Port Capabilities */
41 #define NI16550_PMR_CAP_RS232 FIELD_PREP(NI16550_PMR_CAP_MASK, 1) /* RS-232 capable */
[all …]
|
| /linux/include/uapi/linux/ |
| H A D | serial_core.h | 1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
19 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
20 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
21 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
22 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
23 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
24 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
25 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
29 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
30 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
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| /linux/arch/mips/kernel/ |
| H A D | cps-vec-ns16550.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #include <asm/asm-offsets.h>
32 * _mips_cps_putc() - write a character to the UART
34 * @t9: UART base address
45 * _mips_cps_puts() - write a string to the UART
46 * @a0: pointer to NULL-terminated ASCII string
47 * @t9: UART base address
49 * Write a null-terminated ASCII string to the UART.
65 * _mips_cps_putx4 - write a 4b hex value to the UART
66 * @a0: the 4b value to write to the UART
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| /linux/arch/arm/include/debug/ |
| H A D | tegra.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
12 * Portions based on mach-omap2's debug-macro.S
13 * Copyright (C) 1994-1999 Russell King
40 * Must be section-aligned since a section mapping is used early on.
41 * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
50 /* Test UART's reset bit */ \
52 /* If set, can't use UART; jump to save no UART */ \
58 /* Test UART's clock enable bit */ \
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| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | mediatek,uart-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek UART APDMA controller
10 - Long Cheng <long.cheng@mediatek.com>
13 The MediaTek UART APDMA controller provides DMA capabilities
14 for the UART peripheral bus.
17 - $ref: dma-controller.yaml#
22 - items:
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|
| /linux/tools/arch/x86/dell-uart-backlight-emulator/ |
| H A D | README | 1 Emulator for DELL0501 UART attached backlight controller
2 --------------------------------------------------------
5 board connected to an UART.
7 In DSDT this uart port will be defined as:
12 With the DELL0501 indicating that we are dealing with an UART with
16 the drivers/platform/x86/dell/dell-uart-backlight.c driver without access
20 1. A (desktop) PC with a 16550 UART on the motherboard and a standard DB9
21 connector connected to this UART.
25 4. A DSDT overlay for the desktop PC replacing the _HID of the 16550 UART
32 ./dell-uart-backlight-emulator <path-to-/dev/tty*S#-for-second-port>
[all …]
|