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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
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H A Dmediatek,mt8192-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8192-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
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H A Dmediatek,mt8188-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hui Liu <hui.liu@mediatek.com>
17 const: mediatek,mt8188-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
25 are defined in <dt-bindings/gpio/gpio.h>.
28 gpio-ranges:
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H A Dmediatek,mt6779-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Teng <andy.teng@mediatek.com>
11 - Sean Wang <sean.wang@kernel.org>
20 - mediatek,mt6779-pinctrl
21 - mediatek,mt6797-pinctrl
26 reg-names: true
28 gpio-controller: true
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H A Dmediatek,mt6795-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Sean Wang <sean.wang@kernel.org>
18 const: mediatek,mt6795-pinctrl
20 gpio-controller: true
22 '#gpio-cells':
29 gpio-ranges:
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H A Dfsl,imx25-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
22 Refer to imx25-pinfunc.h in device tree source folder for all available
H A Dmediatek,mt8186-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
31 gpio-line-names: true
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H A Dmediatek,mt8195-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
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H A Dmediatek,mt8365-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Zhiyong Tao <zhiyong.tao@mediatek.com>
11 - Bernhard Rosenkränzer <bero@baylibre.com>
18 const: mediatek,mt8365-pinctrl
23 mediatek,pctl-regmap:
24 $ref: /schemas/types.yaml#/definitions/phandle-array
32 gpio-controller: true
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-phygate-tauri-l-rs232-rts-cts.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * Tauri-L RS232 with RTS/CTS hardware flow control:
7 * - UART4_TX becomes RTS
8 * - UART4_RX becomes CTS
11 #include <dt-bindings/clock/imx8mm-clock.h>
12 #include "imx8mm-pinfunc.h"
14 /dts-v1/;
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_uart2>;
20 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
[all …]
H A Dimx8mm-venice-gw72xx-0x-rs232-rts.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * - GPIO4_0 rs485_en needs to be driven low (in-active)
7 * - UART4_TX becomes RTS
8 * - UART4_RX becomes CTS
11 #include <dt-bindings/gpio/gpio.h>
13 #include "imx8mm-pinfunc.h"
15 /dts-v1/;
19 rs485-en-hog {
20 gpio-hog;
22 output-low;
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H A Dimx8mm-venice-gw73xx-0x-rs232-rts.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * - GPIO4_0 rs485_en needs to be driven low (in-active)
7 * - UART4_TX becomes RTS
8 * - UART4_RX becomes CTS
11 #include <dt-bindings/gpio/gpio.h>
13 #include "imx8mm-pinfunc.h"
15 /dts-v1/;
19 rs485-en-hog {
20 gpio-hog;
22 output-low;
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H A Dimx93-phyboard-segin-peb-eval-01.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include "imx93-pinfunc.h"
15 gpio-keys {
16 compatible = "gpio-keys";
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_gpio_keys>;
20 button-s2 {
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H A Dimx8mm-venice-gw72xx-0x-rs422.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * - GPIO1_0 rs485_term selects on-chip termination
7 * - GPIO4_0 rs485_en needs to be driven high (active)
8 * - GPIO4_2 rs485_hd needs to be driven low (in-active)
9 * - UART4_TX is DE for RS485 transmitter
10 * - RS485_EN needs to be pulled high
11 * - RS485_HALF needs to be low
14 #include <dt-bindings/gpio/gpio.h>
16 #include "imx8mm-pinfunc.h"
18 /dts-v1/;
[all …]
H A Dimx8mm-venice-gw73xx-0x-rs422.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * - GPIO1_0 rs485_term selects on-chip termination
7 * - GPIO4_0 rs485_en needs to be driven high (active)
8 * - GPIO4_2 rs485_hd needs to be driven low (in-active)
9 * - UART4_TX is DE for RS485 transmitter
10 * - RS485_EN needs to be pulled high
11 * - RS485_HALF needs to be low
14 #include <dt-bindings/gpio/gpio.h>
16 #include "imx8mm-pinfunc.h"
18 /dts-v1/;
[all …]
H A Dimx8mm-venice-gw72xx-0x-rs485.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * - GPIO1_0 rs485_term selects on-chip termination
7 * - GPIO4_0 rs485_en needs to be driven high (active)
8 * - GPIO4_2 rs485_hd needs to be driven high (active)
9 * - UART4_TX is DE for RS485 transmitter
10 * - RS485_EN needs to be pulled high
11 * - RS485_HALF needs to be pulled high
14 #include <dt-bindings/gpio/gpio.h>
16 #include "imx8mm-pinfunc.h"
18 /dts-v1/;
[all …]
H A Dimx8mm-venice-gw73xx-0x-rs485.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * - GPIO1_0 rs485_term selects on-chip termination
7 * - GPIO4_0 rs485_en needs to be driven high (active)
8 * - GPIO4_2 rs485_hd needs to be driven high (active)
9 * - UART4_TX is DE for RS485 transmitter
10 * - RS485_EN needs to be pulled high
11 * - RS485_HALF needs to be pulled high
14 #include <dt-bindings/gpio/gpio.h>
16 #include "imx8mm-pinfunc.h"
18 /dts-v1/;
[all …]
H A Dimx8mm-phygate-tauri-l-rs232-rs232.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * Tauri-L 2 x RS232:
7 * - GPIO3_20 uart4_rs485_en needs to be driven low (inactive)
10 #include <dt-bindings/clock/imx8mm-clock.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "imx8mm-pinfunc.h"
14 /dts-v1/;
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_gpio3_hog>;
21 uart4-rs485-en-hog {
[all …]
H A Dimx8mm-phyboard-polis-peb-eval-01.dtso1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/linux-event-codes.h>
12 #include "imx8mm-pinfunc.h"
15 gpio-keys {
16 compatible = "gpio-keys";
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_gpio_keys>;
20 button-0 {
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H A Dimx8mm-phygate-tauri-l-rs232-rs485.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * Tauri-L RS232 + RS485:
7 * - GPIO3_20 uart4_rs485_en needs to be driven high (active)
8 * - GPIO3_25 RS485_DE Driver enable
11 #include <dt-bindings/clock/imx8mm-clock.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include "imx8mm-pinfunc.h"
15 /dts-v1/;
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio3_hog>;
[all …]
H A Dimx8mm-venice-gw72xx-0x-rpidsi.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
8 #include "imx8mm-pinfunc.h"
10 /dts-v1/;
14 compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";
17 compatible = "powertip,ph800480t013-idf02";
18 power-supply = <&attiny>;
23 remote-endpoint = <&bridge_out>;
30 #address-cells = <1>;
31 #size-cells = <0>;
[all …]
H A Dimx8mm-venice-gw73xx-0x-rpidsi.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
8 #include "imx8mm-pinfunc.h"
10 /dts-v1/;
14 compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";
17 compatible = "powertip,ph800480t013-idf02";
18 power-supply = <&attiny>;
23 remote-endpoint = <&bridge_out>;
30 #address-cells = <1>;
31 #size-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-phycore-stm32mp1-3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
7 /dts-v1/;
9 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
12 #include "stm32mp15xxac-pinctrl.dtsi"
13 #include "stm32mp157c-phycore-stm32mp15-som.dtsi"
16 model = "PHYTEC phyCORE-STM32MP1-3 Dev Board";
17 compatible = "phytec,phycore-stm32mp1-3",
18 "phytec,phycore-stm32mp157c-som", "st,stm32mp157";
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imxrt1050-pinfunc.h"
12 model = "NXP IMXRT1050-evk board";
13 compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
16 stdout-path = &lpuart1;
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_lpuart1>;
42 pinctrl-names = "default";
65 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
[all …]
/linux/Documentation/devicetree/bindings/firmware/
H A Dnxp,imx95-scmi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/nxp,imx95-scmi-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Peng Fan <peng.fan@nxp.com>
14 - $ref: /schemas/pinctrl/pinctrl.yaml
31 be found in <arch/arm64/boot/dts/freescale/imx95-pinfunc.h>. The last
32 integer CONFIG is the pad setting value like pull-up on this pin.
34 $ref: /schemas/types.yaml#/definitions/uint32-matrix
37 - description: |
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