1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) 2019 4*724ba675SRob Herring * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring/dts-v1/; 8*724ba675SRob Herring#include "imxrt1050.dtsi" 9*724ba675SRob Herring#include "imxrt1050-pinfunc.h" 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring model = "NXP IMXRT1050-evk board"; 13*724ba675SRob Herring compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050"; 14*724ba675SRob Herring 15*724ba675SRob Herring chosen { 16*724ba675SRob Herring stdout-path = &lpuart1; 17*724ba675SRob Herring }; 18*724ba675SRob Herring 19*724ba675SRob Herring aliases { 20*724ba675SRob Herring gpio0 = &gpio1; 21*724ba675SRob Herring gpio1 = &gpio2; 22*724ba675SRob Herring gpio2 = &gpio3; 23*724ba675SRob Herring gpio3 = &gpio4; 24*724ba675SRob Herring gpio4 = &gpio5; 25*724ba675SRob Herring mmc0 = &usdhc1; 26*724ba675SRob Herring serial0 = &lpuart1; 27*724ba675SRob Herring }; 28*724ba675SRob Herring 29*724ba675SRob Herring memory@80000000 { 30*724ba675SRob Herring device_type = "memory"; 31*724ba675SRob Herring reg = <0x80000000 0x2000000>; 32*724ba675SRob Herring }; 33*724ba675SRob Herring}; 34*724ba675SRob Herring 35*724ba675SRob Herring&lpuart1 { 36*724ba675SRob Herring pinctrl-names = "default"; 37*724ba675SRob Herring pinctrl-0 = <&pinctrl_lpuart1>; 38*724ba675SRob Herring status = "okay"; 39*724ba675SRob Herring}; 40*724ba675SRob Herring 41*724ba675SRob Herring&iomuxc { 42*724ba675SRob Herring pinctrl-names = "default"; 43*724ba675SRob Herring pinctrl_lpuart1: lpuart1grp { 44*724ba675SRob Herring fsl,pins = < 45*724ba675SRob Herring MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1 46*724ba675SRob Herring MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1 47*724ba675SRob Herring >; 48*724ba675SRob Herring }; 49*724ba675SRob Herring 50*724ba675SRob Herring pinctrl_usdhc0: usdhc0grp { 51*724ba675SRob Herring fsl,pins = < 52*724ba675SRob Herring MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000 53*724ba675SRob Herring MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069 54*724ba675SRob Herring MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061 55*724ba675SRob Herring MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061 56*724ba675SRob Herring MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061 57*724ba675SRob Herring MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061 58*724ba675SRob Herring MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061 59*724ba675SRob Herring MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061 60*724ba675SRob Herring >; 61*724ba675SRob Herring }; 62*724ba675SRob Herring}; 63*724ba675SRob Herring 64*724ba675SRob Herring&usdhc1 { 65*724ba675SRob Herring pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 66*724ba675SRob Herring pinctrl-0 = <&pinctrl_usdhc0>; 67*724ba675SRob Herring pinctrl-1 = <&pinctrl_usdhc0>; 68*724ba675SRob Herring pinctrl-2 = <&pinctrl_usdhc0>; 69*724ba675SRob Herring pinctrl-3 = <&pinctrl_usdhc0>; 70*724ba675SRob Herring cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; 71*724ba675SRob Herring status = "okay"; 72*724ba675SRob Herring}; 73