Home
last modified time | relevance | path

Searched +full:- +full:phy (Results 1 – 25 of 1063) sorted by relevance

12345678910>>...43

/linux/drivers/phy/
H A Dphy-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-core.c -- Generic Phy framework.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
18 #include <linux/phy/phy.h>
25 .name = "phy",
37 struct phy *phy = *(struct phy **)res; in devm_phy_release() local
39 phy_put(dev, phy); in devm_phy_release()
51 struct phy *phy = *(struct phy **)res; in devm_phy_consume() local
53 phy_destroy(phy); in devm_phy_consume()
58 struct phy **phy = res; in devm_phy_match() local
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # PHY
6 menu "PHY Subsystem"
9 bool "PHY Core"
11 Generic PHY support.
13 This framework is designed to provide a generic interface for PHY
15 API by which phy drivers can create PHY using the phy framework and
16 phy users can obtain reference to the PHY. All the users of this
23 Generic MIPI D-PHY support.
25 Provides a number of helpers a core functions for MIPI D-PHY
[all …]
/linux/include/linux/phy/
H A Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * phy.h -- generic phy header file
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
19 #include <linux/phy/phy-dp.h>
20 #include <linux/phy/phy-lvds.h>
21 #include <linux/phy/phy-mipi-dphy.h>
23 struct phy;
55 * union phy_configure_opts - Opaque generic phy configuration
58 * the MIPI_DPHY phy mode.
62 * the LVDS phy mode.
[all …]
/linux/drivers/scsi/libsas/
H A Dsas_phy.c1 // SPDX-License-Identifier: GPL-2.0
3 * Serial Attached SCSI (SAS) Phy class
15 /* ---------- Phy events ---------- */
20 struct asd_sas_phy *phy = ev->phy; in sas_phye_loss_of_signal() local
22 phy->error = 0; in sas_phye_loss_of_signal()
23 sas_deform_port(phy, 1); in sas_phye_loss_of_signal()
29 struct asd_sas_phy *phy = ev->phy; in sas_phye_oob_done() local
31 phy->error = 0; in sas_phye_oob_done()
37 struct asd_sas_phy *phy = ev->phy; in sas_phye_oob_error() local
38 struct sas_ha_struct *sas_ha = phy->ha; in sas_phye_oob_error()
[all …]
H A Dsas_port.c1 // SPDX-License-Identifier: GPL-2.0
15 static bool phy_is_wideport_member(struct asd_sas_port *port, struct asd_sas_phy *phy) in phy_is_wideport_member() argument
17 struct sas_ha_struct *sas_ha = phy->ha; in phy_is_wideport_member()
19 if (memcmp(port->attached_sas_addr, phy->attached_sas_addr, in phy_is_wideport_member()
20 SAS_ADDR_SIZE) != 0 || (sas_ha->strict_wide_ports && in phy_is_wideport_member()
21 memcmp(port->sas_addr, phy->sas_addr, SAS_ADDR_SIZE) != 0)) in phy_is_wideport_member()
26 static void sas_resume_port(struct asd_sas_phy *phy) in sas_resume_port() argument
29 struct asd_sas_port *port = phy->port; in sas_resume_port()
30 struct sas_ha_struct *sas_ha = phy->ha; in sas_resume_port()
31 struct sas_internal *si = to_sas_internal(sas_ha->shost->transportt); in sas_resume_port()
[all …]
/linux/drivers/net/
H A Dsungem_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PHY drivers for the sungem ethernet driver.
7 * (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
10 * - Add support for PHYs that provide an IRQ line
11 * - Eventually moved the entire polling state machine in
14 * - On LXT971 & BCM5201, Apple uses some chip specific regs
17 * - Apple has some additional power management code for some
35 /* Link modes of the BCM5400 PHY */
47 static inline int __sungem_phy_read(struct mii_phy* phy, int id, int reg) in __sungem_phy_read() argument
49 return phy->mdio_read(phy->dev, id, reg); in __sungem_phy_read()
[all …]
/linux/Documentation/translations/zh_CN/driver-api/phy/
H A Dphy.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../../disclaimer-zh_CN.rst
4 :Original: Documentation/driver-api/phy/phy.rst
16 本文档解释了 PHY 的通用框架和提供的API，以及使用方法。
21 *PHY* 是物理层的缩写，它被用来把设备连接到一个物理媒介，例如USB控制器
22 有一个提供序列化、反序列化、编码、解码和负责获取所需的数据传输速率的 PHY。
23 注意，有些USB控制器内嵌了 PHY 的功能，其它的则使用了一个外置的PHY，此外
24 使用 PHY 的设备还有无线网、以太网、SATA等（控制器）。
26 创建这个框架的目的是将遍布 Linux 内核的 PHY 驱动程序融入到 drivers/phy，
29 该框架仅适用于使用外部 PHY（PHY 功能未嵌入控制器内）的设备。
[all …]
/linux/drivers/net/ethernet/ibm/emac/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/net/ethernet/ibm/emac/phy.c
5 * Driver for PowerPC 4xx on-chip ethernet controller, PHY support.
18 * (c) 2004-2005, Eugene Surovegin <ebs@ebshome.net>
30 #include "phy.h"
35 static inline int _phy_read(struct mii_phy *phy, int reg) in _phy_read() argument
37 return phy->mdio_read(phy->dev, phy->address, reg); in _phy_read()
40 static inline void _phy_write(struct mii_phy *phy, int reg, int val) in _phy_write() argument
42 phy->mdio_write(phy->dev, phy->address, reg, val); in _phy_write()
45 static inline int gpcs_phy_read(struct mii_phy *phy, int reg) in gpcs_phy_read() argument
[all …]
/linux/drivers/phy/hisilicon/
H A Dphy-hi3670-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe phy driver for Kirin 970
25 #include <linux/phy/phy.h>
44 /* PCIe PHY registers */
168 static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy, u32 val, in hi3670_apb_phy_writel() argument
171 writel(val, phy->base + APB_PHY_START_ADDR + reg); in hi3670_apb_phy_writel()
174 static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg) in hi3670_apb_phy_readl() argument
176 return readl(phy->base + APB_PHY_START_ADDR + reg); in hi3670_apb_phy_readl()
179 static inline void hi3670_apb_phy_updatel(struct hi3670_pcie_phy *phy, in hi3670_apb_phy_updatel() argument
184 regval = hi3670_apb_phy_readl(phy, reg); in hi3670_apb_phy_updatel()
[all …]
/linux/drivers/media/platform/ti/cal/
H A Dcal-camerarx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Camera Access Layer (CAL) - CAMERARX
5 * Copyright (c) 2015-2020 Texas Instruments Inc.
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-subdev.h>
28 /* ------------------------------------------------------------------
30 * ------------------------------------------------------------------
33 static inline u32 camerarx_read(struct cal_camerarx *phy, u32 offset) in camerarx_read() argument
35 return ioread32(phy->base + offset); in camerarx_read()
[all …]
/linux/drivers/phy/ti/
H A Dphy-omap-usb2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * omap-usb2.c - USB PHY, talking to USB controller on TI SoCs.
5 * Copyright (C) 2012-2020 Texas Instruments Incorporated - http://www.ti.com
17 #include <linux/phy/omap_control_phy.h>
18 #include <linux/phy/omap_usb.h>
19 #include <linux/phy/phy.h>
55 struct usb_phy phy; member
71 #define phy_to_omapusb(x) container_of((x), struct omap_usb, phy)
93 * omap_usb2_set_comparator() - links the comparator present in the system with this phy
95 * @comparator: the companion phy(comparator) for this phy
[all …]
H A Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
13 #include <linux/phy/phy.h>
20 #include <linux/phy/omap_control_phy.h>
216 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
242 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
267 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
300 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy) in ti_pipe3_get_dpll_params() argument
303 struct pipe3_dpll_map *dpll_map = phy->dpll_map; in ti_pipe3_get_dpll_params()
[all …]
H A Dphy-dm816x-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/phy/phy.h>
22 * phy as being SR70LX Synopsys USB 2.0 OTG nanoPHY. It also seems at
32 * Finally, the phy on dm814x and am335x is different from dm816x.
35 #define DM816X_USB_CTRL_PHYSLEEP1 BIT(1) /* Enable the first phy */
36 #define DM816X_USB_CTRL_PHYSLEEP0 BIT(0) /* Enable the second phy */
47 struct usb_phy phy; member
54 otg->host = host; in dm816x_usb_phy_set_host()
56 otg->state = OTG_STATE_UNDEFINED; in dm816x_usb_phy_set_host()
64 otg->gadget = gadget; in dm816x_usb_phy_set_peripheral()
[all …]
/linux/drivers/phy/ralink/
H A Dphy-ralink-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/phy/phy.h>
56 struct phy *phy; member
61 static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg) in u2_phy_w32() argument
63 writel(val, phy->base + reg); in u2_phy_w32()
66 static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg) in u2_phy_r32() argument
68 return readl(phy->base + reg); in u2_phy_r32()
71 static void ralink_usb_phy_init(struct ralink_usb_phy *phy) in ralink_usb_phy_init() argument
73 u2_phy_r32(phy, OFS_U2_PHY_AC2); in ralink_usb_phy_init()
74 u2_phy_r32(phy, OFS_U2_PHY_ACR0); in ralink_usb_phy_init()
[all …]
H A Dphy-mt7621-pci.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Mediatek MT7621 PCI PHY Driver
7 #include <dt-bindings/phy/phy.h>
13 #include <linux/phy/phy.h>
66 * struct mt7621_pci_phy - Mt7621 Pcie PHY core
69 * @phy: pointer to the kernel PHY device
72 * @has_dual_port: if the phy has dual ports.
79 struct phy *phy; member
86 static inline void mt7621_phy_rmw(struct mt7621_pci_phy *phy, in mt7621_phy_rmw() argument
98 regmap_read(phy->regmap, reg, &val); in mt7621_phy_rmw()
[all …]
/linux/drivers/net/phy/
H A Dphy_led_triggers.c1 // SPDX-License-Identifier: GPL-2.0+
4 #include <linux/phy.h>
8 static struct phy_led_trigger *phy_speed_to_led_trigger(struct phy_device *phy, in phy_speed_to_led_trigger() argument
13 for (i = 0; i < phy->phy_num_led_triggers; i++) { in phy_speed_to_led_trigger()
14 if (phy->phy_led_triggers[i].speed == speed) in phy_speed_to_led_trigger()
15 return &phy->phy_led_triggers[i]; in phy_speed_to_led_trigger()
20 static void phy_led_trigger_no_link(struct phy_device *phy) in phy_led_trigger_no_link() argument
22 if (phy->last_triggered) { in phy_led_trigger_no_link()
23 led_trigger_event(&phy->last_triggered->trigger, LED_OFF); in phy_led_trigger_no_link()
24 led_trigger_event(&phy->led_link_trigger->trigger, LED_OFF); in phy_led_trigger_no_link()
[all …]
/linux/drivers/nfc/pn544/
H A Di2c.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/crc-ccitt.h>
132 #define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\
136 #define PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN (PN544_FW_I2C_MAX_PAYLOAD -\
183 16, 1, (skb)->data, (skb)->len, 0); \
186 static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy) in pn544_hci_i2c_platform_init() argument
192 nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n"); in pn544_hci_i2c_platform_init()
195 gpiod_set_value_cansleep(phy->gpiod_fw, 0); in pn544_hci_i2c_platform_init()
198 phy->en_polarity = polarity; in pn544_hci_i2c_platform_init()
200 while (retry--) { in pn544_hci_i2c_platform_init()
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_combo_phy.c1 // SPDX-License-Identifier: MIT
17 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
33 .name = "0.85V dot0 (low-voltage)",
55 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in icl_get_procmon_ref_values() argument
59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
78 enum phy phy) in icl_set_procmon_ref_values() argument
82 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_set_procmon_ref_values()
84 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
85 (0xff << 16) | 0xff, procmon->dw1); in icl_set_procmon_ref_values()
87 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_phy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
31 * igb_check_reset_block - Check if PHY reset is blocked
34 * Read the PHY management control register and check whether a PHY reset
48 * igb_get_phy_id - Retrieve the PHY ID and revision
51 * Reads the PHY registers and stores the PHY ID and possibly the PHY
56 struct e1000_phy_info *phy = &hw->phy; in igb_get_phy_id() local
60 /* ensure PHY page selection to fix misconfigured i210 */ in igb_get_phy_id()
61 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) in igb_get_phy_id()
62 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0); in igb_get_phy_id()
[all …]
/linux/drivers/phy/allwinner/
H A Dphy-sun9i-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Allwinner sun9i USB phy driver
5 * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
7 * Based on phy-sun4i-usb.c from
18 #include <linux/phy/phy.h>
36 struct phy *phy; member
44 static void sun9i_usb_phy_passby(struct sun9i_usb_phy *phy, int enable) in sun9i_usb_phy_passby() argument
52 if (phy->type == USBPHY_INTERFACE_MODE_HSIC) in sun9i_usb_phy_passby()
56 reg_value = readl(phy->pmu); in sun9i_usb_phy_passby()
63 writel(reg_value, phy->pmu); in sun9i_usb_phy_passby()
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
[all …]
/linux/Documentation/driver-api/phy/
H A Dphy.rst2 PHY subsystem
7 This document explains the Generic PHY Framework along with the APIs provided,
8 and how-to-use.
13 *PHY* is the abbreviation for physical layer. It is used to connect a device
14 to the physical medium e.g., the USB controller has a PHY to provide functions
15 such as serialization, de-serialization, encoding, decoding and is responsible
17 controllers have PHY functionality embedded into it and others use an external
18 PHY. Other peripherals that use PHY include Wireless LAN, Ethernet,
21 The intention of creating this framework is to bring the PHY drivers spread
22 all over the Linux kernel to drivers/phy to increase code re-use and for
[all …]
/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
16 i2c0_imux: i2c-mux {
17 compatible = "i2c-mux-pinctrl";
18 #address-cells = <1>;
19 #size-cells = <0>;
20 i2c-parent = <&i2c0>;
24 compatible = "gpio-leds";
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dael1002.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
62 /* PHY module I2C device address */
68 /* PHY transceiver type */
84 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv) in set_phy_regs() argument
88 for (err = 0; rv->mmd_addr && !err; rv++) { in set_phy_regs()
89 if (rv->clear_bits == 0xffff) in set_phy_regs()
90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr, in set_phy_regs()
91 rv->set_bits); in set_phy_regs()
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_hdmi_phy.c1 // SPDX-License-Identifier: GPL-2.0+
127 static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy, in sun8i_hdmi_phy_set_polarity() argument
132 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in sun8i_hdmi_phy_set_polarity()
135 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in sun8i_hdmi_phy_set_polarity()
138 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, in sun8i_hdmi_phy_set_polarity()
146 unsigned int clk_rate = mode->crtc_clock * 1000; in sun8i_a83t_hdmi_phy_config()
147 struct sun8i_hdmi_phy *phy = data; in sun8i_a83t_hdmi_phy_config() local
149 sun8i_hdmi_phy_set_polarity(phy, mode); in sun8i_a83t_hdmi_phy_config()
151 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun8i_a83t_hdmi_phy_config()
211 struct sun8i_hdmi_phy *phy = data; in sun8i_a83t_hdmi_phy_disable() local
[all …]

12345678910>>...43