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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dsifive,fu540-c000-pdma.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
26 - $ref: dma-controller.yaml#
31 - items:
[all …]
H A Dmmp-dma.txt7 - compatible: Should be "marvell,pdma-1.0"
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
10 or one irq for pdma device
13 - dma-channels: Number of DMA channels supported by the controller (defaults
15 - #dma-channels: deprecated
16 - dma-requests: Number of DMA requestor lines supported by the controller
18 - #dma-requests: deprecated
20 "marvell,pdma-1.0"
29 * Using this method, interrupt-parent is required as demuxer
[all …]
H A Dmarvell,mmp-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/marvell,mmp-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Duje Mihanović <duje.mihanovic@skole.hr>
18 - marvell,pdma-1.0
19 - marvell,adma-1.0
20 - marvell,pxa910-squ
35 '#dma-channels':
38 '#dma-requests':
[all …]
/freebsd/sys/contrib/device-tree/src/mips/ingenic/
H A Dx1830.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
4 #include <dt-bindings/dma/x1830-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
21 clock-names = "cpu";
[all …]
H A Dx1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
21 clock-names = "cpu";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/pxa/
H A Dpxa3xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
33 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
[all …]
H A Dpxa27x.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "dt-bindings/clock/pxa-clock.h"
11 pdma: dma-controller@40000000 { label
12 compatible = "marvell,pdma-1.0";
15 #dma-cells = <2>;
17 #dma-channels = <32>;
18 dma-channels = <32>;
19 #dma-requests = <75>;
20 dma-requests = <75>;
24 pxairq: interrupt-controller@40d00000 {
[all …]
H A Dpxa300-raumfeld-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 hw-revision = <0>;
14 stdout-path = &ffuart;
22 reg_3v3: regulator-3v3 {
23 compatible = "regulator-fixed";
24 regulator-name = "3v3-fixed-supply";
25 regulator-min-microvolt = <3300000>;
[all …]
H A Dpxa25x.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "dt-bindings/clock/pxa-clock.h"
17 #address-cells = <1>;
18 #size-cells = <1>;
22 compatible = "marvell,pxa250-core-clocks";
23 #clock-cells = <1>;
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <3686400>;
32 clock-output-names = "ostimer";
[all …]
H A Dpxa2xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC
8 #include "dt-bindings/clock/pxa-clock.h"
12 mux- ## func { \
17 mux- ## func { \
20 low-power-disable; \
23 mux- ## func { \
26 low-power-enable; \
30 #address-cells = <1>;
31 #size-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Dartpec6-crypto.txt1 Axis crypto engine with PDMA interface.
4 - compatible : Should be one of the following strings:
5 "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
6 "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
7 - reg: Base address and size for the PDMA register area.
8 - interrupts: Interrupt handle for the PDMA interrupt line.
13 compatible = "axis,artpec6-crypto";
H A Daxis,artpec6-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/axis,artpec6-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Axis ARTPEC6 crypto engine with PDMA interface
10 - Lars Persson <lars.persson@axis.com>
15 - axis,artpec6-crypto
16 - axis,artpec7-crypto
25 - compatible
26 - reg
[all …]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
[all …]
H A Drv1108.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
[all …]
H A Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Drk322x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
9 #include <dt-bindings/power/rk3228-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dairoha,en7581-eth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/airoha,en7581-eth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
14 These SoCs have multi-GMAC ports.
19 - airoha,en7581-eth
23 - description: Frame engine base address
24 - description: QDMA0 base address
25 - description: QDMA1 base address
[all …]
/freebsd/sys/dts/arm/
H A Dsocfpga_arria10_socdk_sdmmc.dts1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
31 /dts-v1/;
36 compatible = "altr,socfpga-arria10", "altr,socfpga";
44 clock-frequency = <200000000>;
49 compatible = "arm,cortex-a9-global-timer";
52 clock-frequency = <200000000>;
63 clock-frequency = < 50000000 >;
68 num-slots = <1>;
69 cap-sd-highspeed;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Ddma.c1 // SPDX-License-Identifier: ISC
27 ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i], in mt7622_init_tx_queues_multi()
34 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT7622_TXQ_MGMT, in mt7622_init_tx_queues_multi()
40 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7622_TXQ_MCU, in mt7622_init_tx_queues_multi()
49 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7615_TXQ_FWDL, in mt7615_init_tx_queues()
54 if (!is_mt7615(&dev->mt76)) in mt7615_init_tx_queues()
57 ret = mt76_connac_init_tx_queues(&dev->mphy, 0, MT7615_TX_RING_SIZE, in mt7615_init_tx_queues()
62 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7615_TXQ_MCU, in mt7615_init_tx_queues()
70 dev = mt76_priv(napi->dev); in mt7615_poll_tx()
71 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) { in mt7615_poll_tx()
[all …]
H A Dpci.c1 // SPDX-License-Identifier: ISC
42 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); in mt7615_pci_probe()
48 map = id->device == 0x7663 ? mt7663e_reg_map : mt7615e_reg_map; in mt7615_pci_probe()
49 ret = mt7615_mmio_probe(&pdev->dev, pcim_iomap_table(pdev)[0], in mt7615_pci_probe()
50 pdev->irq, map); in mt7615_pci_probe()
67 devm_free_irq(&pdev->dev, pdev->irq, dev); in mt7615_pci_remove()
79 err = mt76_connac_pm_wake(&dev->mphy, &dev->pm); in mt7615_pci_suspend()
83 hif_suspend = !test_bit(MT76_STATE_SUSPEND, &dev->mphy.state) && in mt7615_pci_suspend()
91 napi_disable(&mdev->tx_napi); in mt7615_pci_suspend()
92 mt76_worker_disable(&mdev->tx_worker); in mt7615_pci_suspend()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-metho
71 pdma: pdma@ffe01000 { global() label
[all...]
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt76x2/
H A Dusb_mcu.c1 // SPDX-License-Identifier: ISC
23 mt76u_vendor_request(&dev->mt76, MT_VEND_DEV_MODE, in mt76x2u_mcu_load_ivb()
30 struct mt76_usb *usb = &dev->mt76.usb; in mt76x2u_mcu_enable_patch()
37 memcpy(usb->data, data, sizeof(data)); in mt76x2u_mcu_enable_patch()
38 mt76u_vendor_request(&dev->mt76, MT_VEND_DEV_MODE, in mt76x2u_mcu_enable_patch()
40 0x12, 0, usb->data, sizeof(data)); in mt76x2u_mcu_enable_patch()
45 struct mt76_usb *usb = &dev->mt76.usb; in mt76x2u_mcu_reset_wmt()
51 memcpy(usb->data, data, sizeof(data)); in mt76x2u_mcu_reset_wmt()
52 mt76u_vendor_request(&dev->mt76, MT_VEND_DEV_MODE, in mt76x2u_mcu_reset_wmt()
54 0x12, 0, usb->data, sizeof(data)); in mt76x2u_mcu_reset_wmt()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Drockchip,pdm.txt5 - compatible: "rockchip,pdm"
6 - "rockchip,px30-pdm"
7 - "rockchip,rk1808-pdm"
8 - "rockchip,rk3308-pdm"
9 - reg: physical base address of the controller and length of memory mapped
11 - dmas: DMA specifiers for rx dma. See the DMA client binding,
13 - dma-names: should include "rx".
14 - clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
15 - clock-names: should contain following:
16 - "pdm_hclk": clock for PDM BUS
[all …]

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