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/linux/drivers/mtd/nand/
H A Decc-mtk.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * MTK ECC controller driver.
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-ecc-mtk.h>
71 /* ecc strength that each IP supports */
126 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, in mtk_ecc_wait_idle() argument
129 struct device *dev = ecc->dev; in mtk_ecc_wait_idle()
133 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, in mtk_ecc_wait_idle()
143 struct mtk_ecc *ecc = id; in mtk_ecc_irq() local
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H A Decc-sw-bch.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file provides ECC correction for more than 1 bit per block of data,
15 #include <linux/mtd/nand-ecc-sw-bch.h>
18 * nand_ecc_sw_bch_calculate - Calculate the ECC corresponding to a data block
21 * @code: Output buffer with ECC
26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
29 memset(code, 0, engine_conf->code_size); in nand_ecc_sw_bch_calculate()
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
33 for (i = 0; i < engine_conf->code_size; i++) in nand_ecc_sw_bch_calculate()
34 code[i] ^= engine_conf->eccmask[i]; in nand_ecc_sw_bch_calculate()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 menu "ECC engine support"
19 bool "Software Hamming ECC engine"
31 bool "NAND ECC Smart Media byte order"
35 Software ECC according to the Smart Media Specification.
39 bool "Software BCH ECC engine"
46 ECC codes. They are used with NAND devices requiring more than 1 bit
50 bool "Macronix external hardware ECC engine"
54 This enables support for the hardware ECC engine from Macronix.
57 tristate "Mediatek hardware ECC engine"
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H A Decc-realtek.c1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Realtek hardware ECC engine in RTL93xx SoCs
7 #include <linux/dma-mapping.h>
14 * The Realtek ECC engine has two operation modes.
16 * - BCH6 : Generate 10 ECC bytes from 512 data bytes plus 6 free bytes
17 * - BCH12 : Generate 20 ECC bytes from 512 data bytes plus 6 free bytes
20 * are only two known devices in the wild that have NAND flash and make use of this ECC engine
25 * This driver aligns with kernel ECC naming conventions. Neverthless a short notice on the
28 * - BBI : Bad block indicator. The first two bytes of OOB. Protected by ECC!
29 * - tag : 6 User/free bytes. First tag "contains" 2 bytes BBI. Protected by ECC!
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/linux/drivers/mtd/nand/raw/ingenic/
H A Dingenic_ecc.c1 // SPDX-License-Identifier: GPL-2.0
3 * JZ47xx ECC common code
19 * ingenic_ecc_calculate() - calculate ECC for a data buffer
20 * @ecc: ECC device.
21 * @params: ECC parameters.
23 * @ecc_code: output buffer with ECC.
25 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for ECC
28 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
32 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
36 * ingenic_ecc_correct() - detect and correct bit errors
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H A Dingenic_nand_drv.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/jz4780-nemc.h>
27 #define DRV_NAME "ingenic-nand"
44 struct ingenic_ecc *ecc; member
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() local
77 if (section || !ecc->total) in qi_lb60_ooblayout_ecc()
78 return -ERANGE; in qi_lb60_ooblayout_ecc()
80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc()
81 oobregion->offset = 12; in qi_lb60_ooblayout_ecc()
90 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_free() local
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H A Djz4740_ecc.c1 // SPDX-License-Identifier: GPL-2.0
3 * JZ4740 ECC controller driver
7 * based on jz4740-nand.c
45 static void jz4740_ecc_reset(struct ingenic_ecc *ecc, bool calc_ecc) in jz4740_ecc_reset() argument
50 writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT); in jz4740_ecc_reset()
52 /* Initialize and enable ECC hardware */ in jz4740_ecc_reset()
53 reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
57 if (calc_ecc) /* calculate ECC from data */ in jz4740_ecc_reset()
59 else /* correct data from ECC */ in jz4740_ecc_reset()
62 writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
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H A Dingenic_ecc.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include <uapi/asm-generic/errno-base.h>
17 * struct ingenic_ecc_params - ECC parameters
18 * @size: data bytes per ECC step.
19 * @bytes: ECC bytes per step.
20 * @strength: number of correctable bits per ECC step.
29 int ingenic_ecc_calculate(struct ingenic_ecc *ecc,
32 int ingenic_ecc_correct(struct ingenic_ecc *ecc,
36 void ingenic_ecc_release(struct ingenic_ecc *ecc);
39 static inline int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
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/linux/drivers/dma/ti/
H A Dedma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
29 #include "../virt-dma.h"
71 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
101 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
102 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
103 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
104 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
105 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
115 * fail. Today davinci-pcm is the only user of this driver and
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/linux/drivers/mtd/nand/raw/
H A Dnand_micron.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
15 * corrected by on-die ECC and should be rewritten.
20 * On chips with 8-bit ECC and additional bit can be used to distinguish
24 * ----- ----- ----- -----------
27 * 0 1 0 4 - 6 errors corrected, recommend rewrite
29 * 1 0 0 1 - 3 errors corrected
31 * 1 1 0 7 - 8 errors corrected, recommend rewrite
66 struct micron_on_die_ecc ecc; member
77 * Configure chip properties from Micron vendor-specific ONFI table
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H A Dqcom_nandc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-qpic-common.h>
24 * by ECC (value in pages)
26 * by ECC (value in pages)
67 * protected by ECC
71 * of a page, consisting of all data, ecc, spare
74 * by ECC
75 * @ecc_bytes_hw: ECC bytes used by controller hardware for this
82 * ecc/non-ecc mode for the current nand flash
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H A Dlpc32xx_slc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include <linux/dma-mapping.h>
30 #define LPC32XX_MODNAME "lpc32xx-nand"
56 #define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
63 #define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
64 #define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */
86 #define SLCTAC_CLOCKS(c, n, s) (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s)
108 /* ECC line party fetch macro */
113 * DMA requires storage space for the DMA local buffer and the hardware ECC
120 /* Number of bytes used for ECC stored in NAND per 256 bytes */
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H A Dnand_toshiba.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
17 /* ECC Status Read Command for BENAND */
20 /* ECC Status Mask for BENAND */
26 /* Max ECC Steps for BENAND */
39 PSEC_TO_NSEC(sdr->tADL_min)), in toshiba_nand_benand_read_eccstatus_op()
40 NAND_OP_8BIT_DATA_IN(chip->ecc.steps, ecc_status, 0), in toshiba_nand_benand_read_eccstatus_op()
42 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in toshiba_nand_benand_read_eccstatus_op()
47 return -ENOTSUPP; in toshiba_nand_benand_read_eccstatus_op()
62 for (i = 0; i < chip->ecc.steps; i++) { in toshiba_nand_benand_eccstatus()
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H A Domap_elm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #define DRIVER_NAME "omap-elm"
50 /* ELM_ERROR_LOCATION_0-15 Registers */
87 writel(val, info->elm_base + offset); in elm_write_reg()
92 return readl(info->elm_base + offset); in elm_read_reg()
96 * elm_config - Configure ELM module
98 * @bch_type: Type of BCH ecc
99 * @ecc_steps: ECC steps to assign to config
100 * @ecc_step_size: ECC step size to assign to config
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H A Dmtk_nand.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mtk.h>
89 #define MTK_NAME "mtk-nand"
146 struct mtk_ecc *ecc; member
185 return (u8 *)p + i * chip->ecc.size; in data_ptr()
197 if (i < mtk_nand->bad_mark.sec) in oob_ptr()
198 poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size; in oob_ptr()
199 else if (i == mtk_nand->bad_mark.sec) in oob_ptr()
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H A Dstm32_fmc2_nand.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
28 /* ECC step size */
43 /* Max ECC buffer length */
295 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); in stm32_fmc2_nfc_timings_init()
297 struct stm32_fmc2_timings *timings = &nand->timings; in stm32_fmc2_nfc_timings_init()
301 regmap_update_bits(nfc->regmap, FMC2_PCR, in stm32_fmc2_nfc_timings_init()
303 FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) | in stm32_fmc2_nfc_timings_init()
304 FIELD_PREP(FMC2_PCR_TAR, timings->tar)); in stm32_fmc2_nfc_timings_init()
307 pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem); in stm32_fmc2_nfc_timings_init()
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/linux/Documentation/devicetree/bindings/mtd/
H A Dnand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
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H A Drockchip,nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: nand-controller.yaml#
13 - Heiko Stuebner <heiko@sntech.de>
18 - const: rockchip,px30-nfc
19 - const: rockchip,rk2928-nfc
20 - const: rockchip,rv1108-nfc
21 - items:
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H A Dhisi504-nand.txt5 - compatible: Should be "hisilicon,504-nfc".
6 - reg: The first contains base physical address and size of
9 - interrupts: Interrupt number for nfc.
10 - nand-bus-width: See nand-controller.yaml.
11 - nand-ecc-mode: Support none and hw ecc mode.
12 - #address-cells: Partition address, should be set 1.
13 - #size-cells: Partition size, should be set 1.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
20 The following ECC strength and step size are currently supported:
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H A Draw-nand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
16 The ECC strength and ECC step size properties define the user
18 they request the ECC engine to correct {strength} bit errors per
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
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H A Dmediatek,nand-ecc-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek(MTK) SoCs NAND ECC engine
10 - Xiangsheng Hou <xiangsheng.hou@mediatek.com>
13 MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
18 - mediatek,mt2701-ecc
19 - mediatek,mt2712-ecc
20 - mediatek,mt7622-ecc
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H A Dnvidia-tegra20-nand.txt4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
14 - reset-names: Must include the following entries:
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/linux/Documentation/driver-api/
H A Dmtdnand.rst10 The generic NAND driver supports almost all NAND and AG-AND based chips
31 --------------------------
37 - [MTD Interface]
43 - [NAND Interface]
48 - [GENERIC]
53 - [DEFAULT]
65 -------------------------------
71 - [INTERN]
77 - [REPLACEABLE]
86 - [BOARDSPECIFIC]
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/linux/arch/arm/mach-socfpga/
H A Docram.c1 // SPDX-License-Identifier: GPL-2.0-only
21 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); in socfpga_init_ocram_ecc()
23 pr_err("Unable to find socfpga-ocram-ecc\n"); in socfpga_init_ocram_ecc()
30 pr_err("Unable to map OCRAM ecc regs.\n"); in socfpga_init_ocram_ecc()
34 /* Clear any pending OCRAM ECC interrupts, then enable ECC */ in socfpga_init_ocram_ecc()
58 /* ECC Manager Defines */
89 * This function uses the memory initialization block in the Arria10 ECC
90 * controller to initialize/clear the entire memory data and ECC data.
97 while (limit--) { in altr_init_memory_port()
104 return -EBUSY; in altr_init_memory_port()
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/linux/arch/sparc/include/asm/
H A Dchafsr.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * ch --> cheetah
10 * ch+ --> cheetah plus
11 * jp --> jalapeno
15 * read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only.
33 /* Hardware corrected E-cache Tag ECC error */
38 /* SW handled correctable E-cache Tag ECC error */
43 /* Uncorrectable E-cache Tag ECC error */
48 /* Uncorrectable system bus data ECC error due to prefetch
64 * This bit is not set when multiple ECC errors happen within a single
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