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Searched +full:- +full:clint (Results 1 – 14 of 14) sorted by relevance

/linux/Documentation/devicetree/bindings/timer/
H A Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
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H A Dthead,c900-aclint-mtimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo CLINT Timer
10 - Inochi Amaoto <inochiama@outlook.com>
15 - enum:
16 - sophgo,sg2042-aclint-mtimer
17 - sophgo,sg2044-aclint-mtimer
18 - const: thead,c900-aclint-mtimer
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/linux/arch/riscv/boot/dts/sophgo/
H A Dcv1800b.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
9 #include "cv180x-cpus.dtsi"
21 interrupt-parent = <&plic>;
22 dma-noncoherent;
25 compatible = "sophgo,cv1800b-pinctrl";
28 reg-names = "sys", "rtc";
31 clk: clock-controller@3002000 {
32 compatible = "sophgo,cv1800b-clk";
35 #clock-cells = <1>;
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H A Dsg2002.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pinctrl/pinctrl-sg2002.h>
10 #include "cv180x-cpus.dtsi"
23 interrupt-parent = <&plic>;
24 dma-noncoherent;
27 compatible = "sophgo,sg2002-pinctrl";
30 reg-names = "sys", "rtc";
33 clk: clock-controller@3002000 {
34 compatible = "sophgo,sg2002-clk", "sophgo,sg2000-clk";
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H A Dcv1812h.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
10 #include "cv180x-cpus.dtsi"
23 interrupt-parent = <&plic>;
24 dma-noncoherent;
27 compatible = "sophgo,cv1812h-pinctrl";
30 reg-names = "sys", "rtc";
33 clk: clock-controller@3002000 {
34 compatible = "sophgo,cv1812h-clk";
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/linux/arch/riscv/include/asm/
H A Dclint.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * This lives in the CLINT driver, but is accessed directly by timex.h to avoid
17 * The ISA defines mtime as a 64-bit memory-mapped register that increments at
21 * like "riscv_mtime", to signify that these non-ISA assumptions must hold.
H A Dtimex.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <asm/clint.h>
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dthead,c900-aclint-mswi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
10 - Inochi Amaoto <inochiama@outlook.com>
15 - enum:
16 - sophgo,sg2042-aclint-mswi
17 - sophgo,sg2044-aclint-mswi
18 - const: thead,c900-aclint-mswi
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/linux/drivers/clocksource/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
198 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
221 32-bit free running decrementing counters.
256 bool "Integrator-AP timer driver" if COMPILE_TEST
259 Enables support for the Integrator-AP timer.
284 available on many OMAP-like platforms.
303 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
307 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_TIMER_OF) += timer-of.o
3 obj-$(CONFIG_TIMER_PROBE) += timer-probe.o
4 obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o
5 obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o
6 obj-$(CONFIG_ATMEL_TCB_CLKSRC) += timer-atmel-tcb.o
7 obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
8 obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
9 obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += timer-cs5535.o
10 obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o
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/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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/linux/arch/riscv/mm/
H A Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0-only
30 * the IPI. The RISC-V spec states that a hart must execute a data fence in flush_icache_all()
34 * IPIs on RISC-V are triggered by MMIO writes to either CLINT or in flush_icache_all()
35 * S-IMSIC, so the fence ensures previous data writes "happen before" in flush_icache_all()
48 * Performs an icache flush for the given MM context. RISC-V has no direct
52 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
65 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
78 if (mm == current->active_mm && local) { in flush_icache_mm()
104 if (!test_bit(PG_dcache_clean, &folio->flags.f)) { in flush_icache_pte()
106 set_bit(PG_dcache_clean, &folio->flags.f); in flush_icache_pte()
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/linux/drivers/irqchip/
H A Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
31 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
46 * On RISC-V systems local interrupts are masked or unmasked by writing
54 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_mask()
55 csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_mask()
57 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
62 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_unmask()
63 csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_unmask()
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/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
21 * Since this is a non-ratified draft specification, the kernel does not
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