1 // SPDX-License-Identifier: GPL-2.0
4  * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
31 	unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;  in riscv_intc_irq()
46  * On RISC-V systems local interrupts are masked or unmasked by writing
54 	if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG)  in riscv_intc_irq_mask()
55 		csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG));  in riscv_intc_irq_mask()
57 		csr_clear(CSR_IE, BIT(d->hwirq));  in riscv_intc_irq_mask()
62 	if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG)  in riscv_intc_irq_unmask()
63 		csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG));  in riscv_intc_irq_unmask()
65 		csr_set(CSR_IE, BIT(d->hwirq));  in riscv_intc_irq_unmask()
71 	 * Andes specific S-mode local interrupt causes (hwirq)  in andes_intc_irq_mask()
72 	 * are defined as (256 + n) and controlled by n-th bit  in andes_intc_irq_mask()
75 	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);  in andes_intc_irq_mask()
77 	if (d->hwirq < ANDES_SLI_CAUSE_BASE)  in andes_intc_irq_mask()
85 	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);  in andes_intc_irq_unmask()
87 	if (d->hwirq < ANDES_SLI_CAUSE_BASE)  in andes_intc_irq_unmask()
96 	 * The RISC-V INTC driver uses handle_percpu_devid_irq() flow  in riscv_intc_irq_eoi()
97 	 * for the per-HART local interrupts and child irqchip drivers  in riscv_intc_irq_eoi()
98 	 * (such as PLIC, SBI IPI, CLINT, APLIC, IMSIC, etc) implement  in riscv_intc_irq_eoi()
99 	 * chained handlers for the per-HART local interrupts.  in riscv_intc_irq_eoi()
103 	 * will do unnecessary mask/unmask of per-HART local interrupts  in riscv_intc_irq_eoi()
105 	 * an empty irq_eoi() callback for RISC-V INTC irqchip.  in riscv_intc_irq_eoi()
110 	.name = "RISC-V INTC",
117 	.name		= "RISC-V INTC",
126 	struct irq_chip *chip = d->host_data;  in riscv_intc_domain_map()
155 		return -EINVAL;  in riscv_intc_domain_alloc()
174 	return intc_domain->fwnode;  in riscv_intc_hwnode()
184 		return -ENXIO;  in riscv_intc_init_common()
232 		 * direct-mode) so we should mark an INTC node as initialized  in riscv_intc_init()
239 	if (of_device_is_compatible(node, "andestech,cpu-intc")) {  in riscv_intc_init()
248 IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
249 IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
274 		if (rintc_acpi_data[_plic]->aplic_plic_id != _plic_id)	\
306 	return data ? data->hart_id : INVALID_HARTID;  in acpi_rintc_ext_parent_to_hartid()
313 	return data ? data->context_id : INVALID_CONTEXT;  in acpi_rintc_get_plic_context()
318 	return index >= nr_rintc ? INVALID_HARTID : rintc_acpi_data[index]->hart_id;  in acpi_rintc_index_to_hartid()
324 		return -1;  in acpi_rintc_get_imsic_mmio_info()
326 	res->start = rintc_acpi_data[index]->imsic_addr;  in acpi_rintc_get_imsic_mmio_info()
327 	res->end = res->start + rintc_acpi_data[index]->imsic_size - 1;  in acpi_rintc_get_imsic_mmio_info()
328 	res->flags = IORESOURCE_MEM;  in acpi_rintc_get_imsic_mmio_info()
349 			return -EINVAL;  in riscv_intc_acpi_init()
353 			return -ENOMEM;  in riscv_intc_acpi_init()
359 		return -ENOMEM;  in riscv_intc_acpi_init()
361 	rintc_acpi_data[nr_rintc]->ext_intc_id = rintc->ext_intc_id;  in riscv_intc_acpi_init()
362 	rintc_acpi_data[nr_rintc]->hart_id = rintc->hart_id;  in riscv_intc_acpi_init()
363 	rintc_acpi_data[nr_rintc]->imsic_addr = rintc->imsic_addr;  in riscv_intc_acpi_init()
364 	rintc_acpi_data[nr_rintc]->imsic_size = rintc->imsic_size;  in riscv_intc_acpi_init()
373 	if (riscv_hartid_to_cpuid(rintc->hart_id) != smp_processor_id())  in riscv_intc_acpi_init()
376 	fn = irq_domain_alloc_named_fwnode("RISCV-INTC");  in riscv_intc_acpi_init()
379 		return -ENOMEM;  in riscv_intc_acpi_init()