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/linux/tools/testing/selftests/drivers/net/
H A Dping.py2 # SPDX-License-Identifier: GPL-2.0
14 def _test_v4(cfg) -> None: argument
15 if not cfg.addr_v["4"]:
18 cmd("ping -c 1 -W0.5 " + cfg.remote_addr_v["4"])
19 cmd("ping -c 1 -W0.5 " + cfg.addr_v["4"], host=cfg.remote)
20 cmd("ping -s 65000 -c 1 -W0.5 " + cfg.remote_addr_v["4"])
21 cmd("ping -s 65000 -c 1 -W0.5 " + cfg.addr_v["4"], host=cfg.remote)
23 def _test_v6(cfg) -> None: argument
24 if not cfg.addr_v["6"]:
27 cmd("ping -c 1 -W5 " + cfg.remote_addr_v["6"])
[all …]
H A Dhds.py2 # SPDX-License-Identifier: GPL-2.0
12 def _get_hds_mode(cfg, netnl) -> str: argument
14 rings = netnl.rings_get({'header': {'dev-index': cfg.ifindex}})
16 raise KsftSkipEx('ring-get not supported by device')
17 if 'tcp-data-split' not in rings:
18 raise KsftSkipEx('tcp-data-split not supported by device')
19 return rings['tcp-data-split']
22 def _xdp_onoff(cfg): argument
23 prog = cfg.net_lib_dir / "xdp_dummy.bpf.o"
25 (cfg.ifname, prog))
[all …]
/linux/tools/testing/selftests/drivers/net/hw/
H A Diou-zcrx.py2 # SPDX-License-Identifier: GPL-2.0
11 def _get_current_settings(cfg): argument
12 output = ethtool(f"-g {cfg.ifname}", json=True, host=cfg.remote)[0]
13 return (output['rx'], output['hds-thresh'])
16 def _get_combined_channels(cfg): argument
17 output = ethtool(f"-l {cfg.ifname}", host=cfg.remote).stdout
22 def _create_rss_ctx(cfg, chan): argument
23 output = ethtool(f"-X {cfg.ifname} context new start {chan} equal 1", host=cfg.remote).stdout
26 return (ctx_id, defer(ethtool, f"-X {cfg.ifname} delete context {ctx_id}", host=cfg.remote))
29 def _set_flow_rule(cfg, port, chan): argument
[all …]
H A Drss_ctx.py2 # SPDX-License-Identifier: GPL-2.0
24 def _rss_key_check(cfg, data=None, context=0): argument
26 data = get_rss(cfg, context=context)
27 if 'rss-hash-key' not in data:
29 non_zero = [x for x in data['rss-hash-key'] if x != 0]
30 ksft_eq(bool(non_zero), True, comment=f"RSS key is all zero {data['rss-hash-key']}")
33 def get_rss(cfg, context=0): argument
34 return ethtool(f"-x {cfg.ifname} context {context}", json=True)[0]
37 def get_drop_err_sum(cfg): argument
38 stats = ip("-s -s link show dev " + cfg.ifname, json=True)[0]
[all …]
H A Dtso.py2 # SPDX-License-Identifier: GPL-2.0
36 def run_one_stream(cfg, ipver, remote_v4, remote_v6, should_lso): argument
37 cfg.require_cmd("socat", remote=True)
40 listen_cmd = f"socat -{ipver} -t 2 -u TCP-LISTEN:{port},reuseport /dev/null,ignoreeof"
42 with bkg(listen_cmd, host=cfg.remote, exit_wait=True) as nc:
43 wait_port_listen(port, host=cfg.remote)
57 qstat_old = cfg.netnl.qstats_get({"ifindex": cfg.ifindex}, dump=True)[0]
61 qstat_new = cfg.netnl.qstats_get({"ifindex": cfg.ifindex}, dump=True)[0]
64 # TCP falls back to non-LSO.
71 total_lso_wire = len(buf) * 0.90 // cfg.dev["mtu"]
[all …]
/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-regs.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
6 * Samsung EXYNOS5 SoC series G-Scaler driver
12 #include "gsc-core.h"
16 writel(GSC_SW_RESET_SRESET, dev->regs + GSC_SW_RESET); in gsc_hw_set_sw_reset()
22 u32 cfg; in gsc_wait_reset() local
25 cfg = readl(dev->regs + GSC_SW_RESET); in gsc_wait_reset()
26 if (!cfg) in gsc_wait_reset()
31 return -EBUSY; in gsc_wait_reset()
36 u32 cfg; in gsc_hw_set_frm_done_irq_mask() local
[all …]
/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-reg.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
13 #include <media/drv-intf/exynos-fimc.h>
14 #include "media-dev.h"
16 #include "fimc-reg.h"
17 #include "fimc-core.h"
21 u32 cfg; in fimc_hw_reset() local
23 cfg = readl(dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
24 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_reset()
25 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
[all …]
H A Dfimc-lite-reg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Register interface file for EXYNOS FIMC-LITE (camera interface) driver
12 #include <media/drv-intf/exynos-fimc.h>
14 #include "fimc-lite-reg.h"
15 #include "fimc-lite.h"
16 #include "fimc-core.h"
23 u32 cfg; in flite_hw_reset() local
25 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
26 cfg |= FLITE_REG_CIGCTRL_SWRST_REQ; in flite_hw_reset()
27 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
[all …]
/linux/drivers/phy/
H A Dphy-core-mipi-dphy.c1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/phy/phy-mipi-dphy.h>
16 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
18 * of the D-PHY specification (v1.2).
24 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_calc_config() argument
28 if (!cfg) in phy_mipi_dphy_calc_config()
29 return -EINVAL; in phy_mipi_dphy_calc_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_calc_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_calc_config()
41 cfg->clk_pre = 8; in phy_mipi_dphy_calc_config()
[all …]
/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-regs.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include "camif-regs.h"
13 #define camif_write(_camif, _off, _val) writel(_val, (_camif)->io_base + (_off))
14 #define camif_read(_camif, _off) readl((_camif)->io_base + (_off))
18 u32 cfg; in camif_hw_reset() local
20 cfg = camif_read(camif, S3C_CAMIF_REG_CISRCFMT); in camif_hw_reset()
21 cfg |= CISRCFMT_ITU601_8BIT; in camif_hw_reset()
22 camif_write(camif, S3C_CAMIF_REG_CISRCFMT, cfg); in camif_hw_reset()
25 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
26 cfg |= CIGCTRL_SWRST; in camif_hw_reset()
[all …]
/linux/tools/testing/selftests/bpf/prog_tests/
H A Dcore_extern.c1 // SPDX-License-Identifier: GPL-2.0
21 #define CFG "CONFIG_BPF_SYSCALL=n\n" macro
25 const char *cfg; member
32 .cfg = "CONFIG_BPF_SYSCALL=n\n"
54 { .name = "tristate (y)", .cfg = CFG"CONFIG_TRISTATE=y\n",
56 { .name = "tristate (n)", .cfg = CFG"CONFIG_TRISTATE=n\n",
58 { .name = "tristate (m)", .cfg = CFG"CONFIG_TRISTATE=m\n",
60 { .name = "tristate (int)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=1" },
61 { .name = "tristate (bad)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=M" },
63 { .name = "bool (y)", .cfg = CFG"CONFIG_BOOL=y\n",
[all …]
/linux/drivers/pci/
H A Decam.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pci-ecam.h>
15 * On 64-bit systems, we do a single ioremap for the whole config space
16 * since we have enough virtual address range available. On 32-bit, we
23 * - reserve mem region
24 * - alloc struct pci_config_window with space for all mappings
25 * - ioremap the config space
31 unsigned int bus_shift = ops->bus_shift; in pci_ecam_create()
32 struct pci_config_window *cfg; in pci_ecam_create() local
37 if (busr->start > busr->end) in pci_ecam_create()
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.c1 // SPDX-License-Identifier: GPL-2.0
85 return (rpm->pdev->device == PCI_DEVID_CN10KB_RPM); in is_dev_rpm2()
133 u64 cfg, last; in rpm_lmac_tx_enable() local
136 return -ENODEV; in rpm_lmac_tx_enable()
138 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_tx_enable()
139 last = cfg; in rpm_lmac_tx_enable()
141 cfg |= RPM_TX_EN; in rpm_lmac_tx_enable()
143 cfg &= ~(RPM_TX_EN); in rpm_lmac_tx_enable()
145 if (cfg != last) in rpm_lmac_tx_enable()
146 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); in rpm_lmac_tx_enable()
[all …]
H A Dcgx.c1 // SPDX-License-Identifier: GPL-2.0
24 #define DRV_NAME "Marvell-CGX/RPM"
90 return (cgx->pdev->device == PCI_DEVID_CN10K_RPM) || in is_dev_rpm()
91 (cgx->pdev->device == PCI_DEVID_CN10KB_RPM); in is_dev_rpm()
96 if (!cgx || lmac_id < 0 || lmac_id >= cgx->max_lmac_per_mac) in is_lmac_valid()
98 return test_bit(lmac_id, &cgx->lmac_bmap); in is_lmac_valid()
108 for_each_set_bit(tmp, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { in get_sequence_id_of_lmac()
122 return ((struct cgx *)cgxd)->mac_ops; in get_mac_ops()
127 return ((struct cgx *)cgxd)->fifo_len; in cgx_get_fifo_len()
132 writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) + in cgx_write()
[all …]
/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_phy_8998.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
82 return platform_get_drvdata(pll->pdev); in pll_get_phy()
88 writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
93 return readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
99 writel(data, pll->mmio_qserdes_tx[channel] + offset); in hdmi_tx_chan_write()
153 return dividend - 1; in pll_get_pll_cmp()
179 optimal_index = -1; in pll_get_post_div()
225 if (optimal_index == -1) { in pll_get_post_div()
230 return -EINVAL; in pll_get_post_div()
[all …]
H A Dhdmi_phy_8996.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
83 return platform_get_drvdata(pll->pdev); in pll_get_phy()
89 writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
94 return readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
100 writel(data, pll->mmio_qserdes_tx[channel] + offset); in hdmi_tx_chan_write()
154 return dividend - 1; in pll_get_pll_cmp()
179 vco_optimal_index = -1; in pll_get_post_div()
201 if (vco_optimal_index == -1) { in pll_get_post_div()
207 pd->vco_freq = vco_optimal; in pll_get_post_div()
[all …]
/linux/sound/pci/hda/
H A Dhda_auto_parser.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * BIOS auto-parser helper functions for HD-audio
38 return (int)(a->seq - b->seq); in compare_seq()
55 /* add the found input-pin to the cfg->inputs[] table */
56 static void add_auto_cfg_input_pin(struct hda_codec *codec, struct auto_pin_cfg *cfg, in add_auto_cfg_input_pin() argument
59 if (cfg->num_inputs < AUTO_CFG_MAX_INS) { in add_auto_cfg_input_pin()
60 cfg->inputs[cfg->num_inputs].pin = nid; in add_auto_cfg_input_pin()
61 cfg->inputs[cfg->num_inputs].type = type; in add_auto_cfg_input_pin()
62 cfg->inputs[cfg->num_inputs].has_boost_on_pin = in add_auto_cfg_input_pin()
64 cfg->num_inputs++; in add_auto_cfg_input_pin()
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_fimc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 #include "regs-fimc.h"
115 return readl(ctx->regs + reg); in fimc_read()
120 writel(val, ctx->regs + reg); in fimc_write()
125 void __iomem *r = ctx->regs + reg; in fimc_set_bits()
132 void __iomem *r = ctx->regs + reg; in fimc_clear_bits()
139 u32 cfg; in fimc_sw_reset() local
142 cfg = fimc_read(ctx, EXYNOS_CISTATUS); in fimc_sw_reset()
143 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) in fimc_sw_reset()
164 u32 cfg; in fimc_set_type_ctrl() local
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_config.h1 /* SPDX-License-Identifier: GPL-2.0 */
60 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
61 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) argument
62 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
63 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) argument
64 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
65 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) argument
67 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) argument
68 #define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size) argument
69 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold) argument
[all …]
/linux/drivers/net/wireless/microchip/wilc1000/
H A Dwlan_cfg.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
142 struct wilc_cfg *cfg = &wl->cfg; in wilc_wlan_parse_response_frame() local
150 while (cfg->b[i].id != WID_NIL && cfg->b[i].id != wid) in wilc_wlan_parse_response_frame()
153 if (cfg->b[i].id == wid) in wilc_wlan_parse_response_frame()
154 cfg->b[i].val = info[4]; in wilc_wlan_parse_response_frame()
160 while (cfg->hw[i].id != WID_NIL && cfg->hw[i].id != wid) in wilc_wlan_parse_response_frame()
163 if (cfg->hw[i].id == wid) in wilc_wlan_parse_response_frame()
164 cfg->hw[i].val = get_unaligned_le16(&info[4]); in wilc_wlan_parse_response_frame()
170 while (cfg->w[i].id != WID_NIL && cfg->w[i].id != wid) in wilc_wlan_parse_response_frame()
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Docteon_config.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
25 /*--------------------------CONFIG VALUES------------------------*/
121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs) argument
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size) argument
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout) argument
128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt) argument
[all …]
/linux/drivers/leds/
H A Dleds-lp55xx-common.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Derived from leds-lp5521.c, leds-lp5523.c
21 #include <linux/platform_data/leds-lp55xx.h>
24 #include <dt-bindings/leds/leds-lp55xx.h>
26 #include "leds-lp55xx-common.h"
48 #define LP55xx_MODE_ENGn_SHIFT(n, shift) ((shift) + (2 * (3 - (n))))
59 #define LP55xx_EXEC_ENGn_SHIFT(n, shift) ((shift) + (2 * (3 - (n))))
65 #define LP55xx_PAGE_OFFSET(n, pages) (((n) - 1) * (pages))
92 const struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_wait_opmode_done() local
101 if (cfg->engine_busy.val) { in lp55xx_wait_opmode_done()
[all …]
/linux/drivers/staging/media/atomisp/pci/runtime/isys/src/
H A Dvirtual_isys.c1 // SPDX-License-Identifier: GPL-2.0
27 isp2401_input_system_cfg_t *cfg,
35 isp2401_input_system_cfg_t *cfg,
95 pixelgen_prbs_cfg_t *cfg);
99 csi_rx_frontend_cfg_t *cfg);
105 csi_rx_backend_cfg_t *cfg);
110 stream2mmio_cfg_t *cfg);
116 ibuf_ctrl_cfg_t *cfg);
121 isys2401_dma_cfg_t *cfg);
127 isys2401_dma_port_cfg_t *cfg);
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_config.h1 /* SPDX-License-Identifier: GPL-2.0 */
51 #define OCTEP_VF_MAX_MTU (10000 - (ETH_HLEN + ETH_FCS_LEN))
56 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
57 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) argument
58 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
59 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) argument
60 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
61 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) argument
63 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) argument
64 #define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size) argument
[all …]
/linux/drivers/iommu/
H A Dio-pgtable-arm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPU-agnostic ARM page table allocator.
10 #define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt
14 #include <linux/io-pgtable.h>
20 #include <linux/dma-mapping.h>
24 #include "io-pgtable-arm.h"
25 #include "iommu-pages.h"
43 (((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level) + \
47 (sizeof(arm_lpae_iopte) << (d)->bits_per_level)
49 (sizeof(arm_lpae_iopte) << (d)->pgd_bits)
[all …]

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