Lines Matching +full:- +full:cfg
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
13 #include <media/drv-intf/exynos-fimc.h>
14 #include "media-dev.h"
16 #include "fimc-reg.h"
17 #include "fimc-core.h"
21 u32 cfg; in fimc_hw_reset() local
23 cfg = readl(dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
24 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_reset()
25 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
28 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
29 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL); in fimc_hw_reset()
30 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
33 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
34 cfg &= ~FIMC_REG_CIGCTRL_SWRST; in fimc_hw_reset()
35 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
37 if (dev->drv_data->out_buf_count > 4) in fimc_hw_reset()
45 if (ctx->hflip) in fimc_hw_get_in_flip()
47 if (ctx->vflip) in fimc_hw_get_in_flip()
50 if (ctx->rotation <= 90) in fimc_hw_get_in_flip()
60 if (ctx->hflip) in fimc_hw_get_target_flip()
62 if (ctx->vflip) in fimc_hw_get_target_flip()
65 if (ctx->rotation <= 90) in fimc_hw_get_target_flip()
73 u32 cfg, flip; in fimc_hw_set_rotation() local
74 struct fimc_dev *dev = ctx->fimc_dev; in fimc_hw_set_rotation()
76 cfg = readl(dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_rotation()
77 cfg &= ~(FIMC_REG_CITRGFMT_INROT90 | FIMC_REG_CITRGFMT_OUTROT90 | in fimc_hw_set_rotation()
85 if (ctx->rotation == 90 || ctx->rotation == 270) { in fimc_hw_set_rotation()
86 if (ctx->out_path == FIMC_IO_LCDFIFO) in fimc_hw_set_rotation()
87 cfg |= FIMC_REG_CITRGFMT_INROT90; in fimc_hw_set_rotation()
89 cfg |= FIMC_REG_CITRGFMT_OUTROT90; in fimc_hw_set_rotation()
92 if (ctx->out_path == FIMC_IO_DMA) { in fimc_hw_set_rotation()
93 cfg |= fimc_hw_get_target_flip(ctx); in fimc_hw_set_rotation()
94 writel(cfg, dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_rotation()
97 flip = readl(dev->regs + FIMC_REG_MSCTRL); in fimc_hw_set_rotation()
100 writel(flip, dev->regs + FIMC_REG_MSCTRL); in fimc_hw_set_rotation()
106 u32 cfg; in fimc_hw_set_target_format() local
107 struct fimc_dev *dev = ctx->fimc_dev; in fimc_hw_set_target_format()
108 const struct fimc_frame *frame = &ctx->d_frame; in fimc_hw_set_target_format()
110 dbg("w= %d, h= %d color: %d", frame->width, in fimc_hw_set_target_format()
111 frame->height, frame->fmt->color); in fimc_hw_set_target_format()
113 cfg = readl(dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_target_format()
114 cfg &= ~(FIMC_REG_CITRGFMT_FMT_MASK | FIMC_REG_CITRGFMT_HSIZE_MASK | in fimc_hw_set_target_format()
117 switch (frame->fmt->color) { in fimc_hw_set_target_format()
119 cfg |= FIMC_REG_CITRGFMT_RGB; in fimc_hw_set_target_format()
122 cfg |= FIMC_REG_CITRGFMT_YCBCR420; in fimc_hw_set_target_format()
125 if (frame->fmt->colplanes == 1) in fimc_hw_set_target_format()
126 cfg |= FIMC_REG_CITRGFMT_YCBCR422_1P; in fimc_hw_set_target_format()
128 cfg |= FIMC_REG_CITRGFMT_YCBCR422; in fimc_hw_set_target_format()
134 if (ctx->rotation == 90 || ctx->rotation == 270) in fimc_hw_set_target_format()
135 cfg |= (frame->height << 16) | frame->width; in fimc_hw_set_target_format()
137 cfg |= (frame->width << 16) | frame->height; in fimc_hw_set_target_format()
139 writel(cfg, dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_target_format()
141 cfg = readl(dev->regs + FIMC_REG_CITAREA); in fimc_hw_set_target_format()
142 cfg &= ~FIMC_REG_CITAREA_MASK; in fimc_hw_set_target_format()
143 cfg |= (frame->width * frame->height); in fimc_hw_set_target_format()
144 writel(cfg, dev->regs + FIMC_REG_CITAREA); in fimc_hw_set_target_format()
149 struct fimc_dev *dev = ctx->fimc_dev; in fimc_hw_set_out_dma_size()
150 const struct fimc_frame *frame = &ctx->d_frame; in fimc_hw_set_out_dma_size()
151 u32 cfg; in fimc_hw_set_out_dma_size() local
153 cfg = (frame->f_height << 16) | frame->f_width; in fimc_hw_set_out_dma_size()
154 writel(cfg, dev->regs + FIMC_REG_ORGOSIZE); in fimc_hw_set_out_dma_size()
157 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_out_dma_size()
158 if (frame->f_width >= 1280) /* HD */ in fimc_hw_set_out_dma_size()
159 cfg |= FIMC_REG_CIGCTRL_CSC_ITU601_709; in fimc_hw_set_out_dma_size()
161 cfg &= ~FIMC_REG_CIGCTRL_CSC_ITU601_709; in fimc_hw_set_out_dma_size()
162 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_out_dma_size()
168 struct fimc_dev *dev = ctx->fimc_dev; in fimc_hw_set_out_dma()
169 const struct fimc_frame *frame = &ctx->d_frame; in fimc_hw_set_out_dma()
170 const struct fimc_dma_offset *offset = &frame->dma_offset; in fimc_hw_set_out_dma()
171 const struct fimc_fmt *fmt = frame->fmt; in fimc_hw_set_out_dma()
172 u32 cfg; in fimc_hw_set_out_dma() local
175 cfg = (offset->y_v << 16) | offset->y_h; in fimc_hw_set_out_dma()
176 writel(cfg, dev->regs + FIMC_REG_CIOYOFF); in fimc_hw_set_out_dma()
178 cfg = (offset->cb_v << 16) | offset->cb_h; in fimc_hw_set_out_dma()
179 writel(cfg, dev->regs + FIMC_REG_CIOCBOFF); in fimc_hw_set_out_dma()
181 cfg = (offset->cr_v << 16) | offset->cr_h; in fimc_hw_set_out_dma()
182 writel(cfg, dev->regs + FIMC_REG_CIOCROFF); in fimc_hw_set_out_dma()
187 cfg = readl(dev->regs + FIMC_REG_CIOCTRL); in fimc_hw_set_out_dma()
189 cfg &= ~(FIMC_REG_CIOCTRL_ORDER2P_MASK | in fimc_hw_set_out_dma()
194 if (fmt->colplanes == 1) in fimc_hw_set_out_dma()
195 cfg |= ctx->out_order_1p; in fimc_hw_set_out_dma()
196 else if (fmt->colplanes == 2) in fimc_hw_set_out_dma()
197 cfg |= ctx->out_order_2p | FIMC_REG_CIOCTRL_YCBCR_2PLANE; in fimc_hw_set_out_dma()
198 else if (fmt->colplanes == 3) in fimc_hw_set_out_dma()
199 cfg |= FIMC_REG_CIOCTRL_YCBCR_3PLANE; in fimc_hw_set_out_dma()
201 if (fmt->color == FIMC_FMT_RGB565) in fimc_hw_set_out_dma()
202 cfg |= FIMC_REG_CIOCTRL_RGB565; in fimc_hw_set_out_dma()
203 else if (fmt->color == FIMC_FMT_RGB555) in fimc_hw_set_out_dma()
204 cfg |= FIMC_REG_CIOCTRL_ARGB1555; in fimc_hw_set_out_dma()
205 else if (fmt->color == FIMC_FMT_RGB444) in fimc_hw_set_out_dma()
206 cfg |= FIMC_REG_CIOCTRL_ARGB4444; in fimc_hw_set_out_dma()
208 writel(cfg, dev->regs + FIMC_REG_CIOCTRL); in fimc_hw_set_out_dma()
213 u32 cfg = readl(dev->regs + FIMC_REG_ORGISIZE); in fimc_hw_en_autoload() local
215 cfg |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN; in fimc_hw_en_autoload()
217 cfg &= ~FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN; in fimc_hw_en_autoload()
218 writel(cfg, dev->regs + FIMC_REG_ORGISIZE); in fimc_hw_en_autoload()
223 u32 cfg = readl(dev->regs + FIMC_REG_CIOCTRL); in fimc_hw_en_lastirq() local
225 cfg |= FIMC_REG_CIOCTRL_LASTIRQ_ENABLE; in fimc_hw_en_lastirq()
227 cfg &= ~FIMC_REG_CIOCTRL_LASTIRQ_ENABLE; in fimc_hw_en_lastirq()
228 writel(cfg, dev->regs + FIMC_REG_CIOCTRL); in fimc_hw_en_lastirq()
233 struct fimc_dev *dev = ctx->fimc_dev; in fimc_hw_set_prescaler()
234 struct fimc_scaler *sc = &ctx->scaler; in fimc_hw_set_prescaler()
235 u32 cfg, shfactor; in fimc_hw_set_prescaler() local
237 shfactor = 10 - (sc->hfactor + sc->vfactor); in fimc_hw_set_prescaler()
238 cfg = shfactor << 28; in fimc_hw_set_prescaler()
240 cfg |= (sc->pre_hratio << 16) | sc->pre_vratio; in fimc_hw_set_prescaler()
241 writel(cfg, dev->regs + FIMC_REG_CISCPRERATIO); in fimc_hw_set_prescaler()
243 cfg = (sc->pre_dst_width << 16) | sc->pre_dst_height; in fimc_hw_set_prescaler()
244 writel(cfg, dev->regs + FIMC_REG_CISCPREDST); in fimc_hw_set_prescaler()
249 struct fimc_dev *dev = ctx->fimc_dev; in fimc_hw_set_scaler()
250 struct fimc_scaler *sc = &ctx->scaler; in fimc_hw_set_scaler()
251 const struct fimc_frame *src_frame = &ctx->s_frame; in fimc_hw_set_scaler()
252 const struct fimc_frame *dst_frame = &ctx->d_frame; in fimc_hw_set_scaler()
254 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_set_scaler() local
256 cfg &= ~(FIMC_REG_CISCCTRL_CSCR2Y_WIDE | FIMC_REG_CISCCTRL_CSCY2R_WIDE | in fimc_hw_set_scaler()
262 if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW)) in fimc_hw_set_scaler()
263 cfg |= (FIMC_REG_CISCCTRL_CSCR2Y_WIDE | in fimc_hw_set_scaler()
266 if (!sc->enabled) in fimc_hw_set_scaler()
267 cfg |= FIMC_REG_CISCCTRL_SCALERBYPASS; in fimc_hw_set_scaler()
269 if (sc->scaleup_h) in fimc_hw_set_scaler()
270 cfg |= FIMC_REG_CISCCTRL_SCALEUP_H; in fimc_hw_set_scaler()
272 if (sc->scaleup_v) in fimc_hw_set_scaler()
273 cfg |= FIMC_REG_CISCCTRL_SCALEUP_V; in fimc_hw_set_scaler()
275 if (sc->copy_mode) in fimc_hw_set_scaler()
276 cfg |= FIMC_REG_CISCCTRL_ONE2ONE; in fimc_hw_set_scaler()
278 if (ctx->in_path == FIMC_IO_DMA) { in fimc_hw_set_scaler()
279 switch (src_frame->fmt->color) { in fimc_hw_set_scaler()
281 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB565; in fimc_hw_set_scaler()
284 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB666; in fimc_hw_set_scaler()
287 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB888; in fimc_hw_set_scaler()
292 if (ctx->out_path == FIMC_IO_DMA) { in fimc_hw_set_scaler()
293 u32 color = dst_frame->fmt->color; in fimc_hw_set_scaler()
296 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565; in fimc_hw_set_scaler()
298 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666; in fimc_hw_set_scaler()
300 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888; in fimc_hw_set_scaler()
302 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888; in fimc_hw_set_scaler()
304 if (ctx->flags & FIMC_SCAN_MODE_INTERLACED) in fimc_hw_set_scaler()
305 cfg |= FIMC_REG_CISCCTRL_INTERLACE; in fimc_hw_set_scaler()
308 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_set_scaler()
313 struct fimc_dev *dev = ctx->fimc_dev; in fimc_hw_set_mainscaler()
314 const struct fimc_variant *variant = dev->variant; in fimc_hw_set_mainscaler()
315 struct fimc_scaler *sc = &ctx->scaler; in fimc_hw_set_mainscaler()
316 u32 cfg; in fimc_hw_set_mainscaler() local
319 sc->main_hratio, sc->main_vratio); in fimc_hw_set_mainscaler()
323 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_set_mainscaler()
324 cfg &= ~(FIMC_REG_CISCCTRL_MHRATIO_MASK | in fimc_hw_set_mainscaler()
327 if (variant->has_mainscaler_ext) { in fimc_hw_set_mainscaler()
328 cfg |= FIMC_REG_CISCCTRL_MHRATIO_EXT(sc->main_hratio); in fimc_hw_set_mainscaler()
329 cfg |= FIMC_REG_CISCCTRL_MVRATIO_EXT(sc->main_vratio); in fimc_hw_set_mainscaler()
330 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_set_mainscaler()
332 cfg = readl(dev->regs + FIMC_REG_CIEXTEN); in fimc_hw_set_mainscaler()
334 cfg &= ~(FIMC_REG_CIEXTEN_MVRATIO_EXT_MASK | in fimc_hw_set_mainscaler()
336 cfg |= FIMC_REG_CIEXTEN_MHRATIO_EXT(sc->main_hratio); in fimc_hw_set_mainscaler()
337 cfg |= FIMC_REG_CIEXTEN_MVRATIO_EXT(sc->main_vratio); in fimc_hw_set_mainscaler()
338 writel(cfg, dev->regs + FIMC_REG_CIEXTEN); in fimc_hw_set_mainscaler()
340 cfg |= FIMC_REG_CISCCTRL_MHRATIO(sc->main_hratio); in fimc_hw_set_mainscaler()
341 cfg |= FIMC_REG_CISCCTRL_MVRATIO(sc->main_vratio); in fimc_hw_set_mainscaler()
342 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_set_mainscaler()
348 struct fimc_dev *dev = ctx->fimc_dev; in fimc_hw_enable_capture()
349 u32 cfg; in fimc_hw_enable_capture() local
351 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT); in fimc_hw_enable_capture()
352 cfg |= FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE; in fimc_hw_enable_capture()
354 if (ctx->scaler.enabled) in fimc_hw_enable_capture()
355 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN_SC; in fimc_hw_enable_capture()
357 cfg &= FIMC_REG_CIIMGCPT_IMGCPTEN_SC; in fimc_hw_enable_capture()
359 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN; in fimc_hw_enable_capture()
360 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT); in fimc_hw_enable_capture()
365 u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT); in fimc_hw_disable_capture() local
366 cfg &= ~(FIMC_REG_CIIMGCPT_IMGCPTEN | in fimc_hw_disable_capture()
368 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT); in fimc_hw_disable_capture()
373 struct fimc_dev *dev = ctx->fimc_dev; in fimc_hw_set_effect()
374 struct fimc_effect *effect = &ctx->effect; in fimc_hw_set_effect()
375 u32 cfg = 0; in fimc_hw_set_effect() local
377 if (effect->type != FIMC_REG_CIIMGEFF_FIN_BYPASS) { in fimc_hw_set_effect()
378 cfg |= FIMC_REG_CIIMGEFF_IE_SC_AFTER | in fimc_hw_set_effect()
380 cfg |= effect->type; in fimc_hw_set_effect()
381 if (effect->type == FIMC_REG_CIIMGEFF_FIN_ARBITRARY) in fimc_hw_set_effect()
382 cfg |= (effect->pat_cb << 13) | effect->pat_cr; in fimc_hw_set_effect()
385 writel(cfg, dev->regs + FIMC_REG_CIIMGEFF); in fimc_hw_set_effect()
390 struct fimc_dev *dev = ctx->fimc_dev; in fimc_hw_set_rgb_alpha()
391 const struct fimc_frame *frame = &ctx->d_frame; in fimc_hw_set_rgb_alpha()
392 u32 cfg; in fimc_hw_set_rgb_alpha() local
394 if (!(frame->fmt->flags & FMT_HAS_ALPHA)) in fimc_hw_set_rgb_alpha()
397 cfg = readl(dev->regs + FIMC_REG_CIOCTRL); in fimc_hw_set_rgb_alpha()
398 cfg &= ~FIMC_REG_CIOCTRL_ALPHA_OUT_MASK; in fimc_hw_set_rgb_alpha()
399 cfg |= (frame->alpha << 4); in fimc_hw_set_rgb_alpha()
400 writel(cfg, dev->regs + FIMC_REG_CIOCTRL); in fimc_hw_set_rgb_alpha()
405 struct fimc_dev *dev = ctx->fimc_dev; in fimc_hw_set_in_dma_size()
406 const struct fimc_frame *frame = &ctx->s_frame; in fimc_hw_set_in_dma_size()
410 if (FIMC_IO_LCDFIFO == ctx->out_path) in fimc_hw_set_in_dma_size()
413 cfg_o |= (frame->f_height << 16) | frame->f_width; in fimc_hw_set_in_dma_size()
414 cfg_r |= (frame->height << 16) | frame->width; in fimc_hw_set_in_dma_size()
416 writel(cfg_o, dev->regs + FIMC_REG_ORGISIZE); in fimc_hw_set_in_dma_size()
417 writel(cfg_r, dev->regs + FIMC_REG_CIREAL_ISIZE); in fimc_hw_set_in_dma_size()
422 struct fimc_dev *dev = ctx->fimc_dev; in fimc_hw_set_in_dma()
423 const struct fimc_frame *frame = &ctx->s_frame; in fimc_hw_set_in_dma()
424 const struct fimc_dma_offset *offset = &frame->dma_offset; in fimc_hw_set_in_dma()
425 u32 cfg; in fimc_hw_set_in_dma() local
428 cfg = (offset->y_v << 16) | offset->y_h; in fimc_hw_set_in_dma()
429 writel(cfg, dev->regs + FIMC_REG_CIIYOFF); in fimc_hw_set_in_dma()
431 cfg = (offset->cb_v << 16) | offset->cb_h; in fimc_hw_set_in_dma()
432 writel(cfg, dev->regs + FIMC_REG_CIICBOFF); in fimc_hw_set_in_dma()
434 cfg = (offset->cr_v << 16) | offset->cr_h; in fimc_hw_set_in_dma()
435 writel(cfg, dev->regs + FIMC_REG_CIICROFF); in fimc_hw_set_in_dma()
441 fimc_hw_en_autoload(dev, ctx->out_path == FIMC_IO_LCDFIFO); in fimc_hw_set_in_dma()
444 cfg = readl(dev->regs + FIMC_REG_MSCTRL); in fimc_hw_set_in_dma()
445 cfg &= ~(FIMC_REG_MSCTRL_INFORMAT_MASK in fimc_hw_set_in_dma()
452 cfg |= (FIMC_REG_MSCTRL_IN_BURST_COUNT(4) in fimc_hw_set_in_dma()
456 switch (frame->fmt->color) { in fimc_hw_set_in_dma()
458 cfg |= FIMC_REG_MSCTRL_INFORMAT_RGB; in fimc_hw_set_in_dma()
461 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR420; in fimc_hw_set_in_dma()
463 if (frame->fmt->colplanes == 2) in fimc_hw_set_in_dma()
464 cfg |= ctx->in_order_2p | FIMC_REG_MSCTRL_C_INT_IN_2PLANE; in fimc_hw_set_in_dma()
466 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE; in fimc_hw_set_in_dma()
470 if (frame->fmt->colplanes == 1) { in fimc_hw_set_in_dma()
471 cfg |= ctx->in_order_1p in fimc_hw_set_in_dma()
474 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR422; in fimc_hw_set_in_dma()
476 if (frame->fmt->colplanes == 2) in fimc_hw_set_in_dma()
477 cfg |= ctx->in_order_2p in fimc_hw_set_in_dma()
480 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE; in fimc_hw_set_in_dma()
487 writel(cfg, dev->regs + FIMC_REG_MSCTRL); in fimc_hw_set_in_dma()
490 cfg = readl(dev->regs + FIMC_REG_CIDMAPARAM); in fimc_hw_set_in_dma()
491 cfg &= ~FIMC_REG_CIDMAPARAM_TILE_MASK; in fimc_hw_set_in_dma()
493 if (tiled_fmt(ctx->s_frame.fmt)) in fimc_hw_set_in_dma()
494 cfg |= FIMC_REG_CIDMAPARAM_R_64X32; in fimc_hw_set_in_dma()
496 if (tiled_fmt(ctx->d_frame.fmt)) in fimc_hw_set_in_dma()
497 cfg |= FIMC_REG_CIDMAPARAM_W_64X32; in fimc_hw_set_in_dma()
499 writel(cfg, dev->regs + FIMC_REG_CIDMAPARAM); in fimc_hw_set_in_dma()
505 struct fimc_dev *dev = ctx->fimc_dev; in fimc_hw_set_input_path()
507 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL); in fimc_hw_set_input_path() local
508 cfg &= ~FIMC_REG_MSCTRL_INPUT_MASK; in fimc_hw_set_input_path()
510 if (ctx->in_path == FIMC_IO_DMA) in fimc_hw_set_input_path()
511 cfg |= FIMC_REG_MSCTRL_INPUT_MEMORY; in fimc_hw_set_input_path()
513 cfg |= FIMC_REG_MSCTRL_INPUT_EXTCAM; in fimc_hw_set_input_path()
515 writel(cfg, dev->regs + FIMC_REG_MSCTRL); in fimc_hw_set_input_path()
520 struct fimc_dev *dev = ctx->fimc_dev; in fimc_hw_set_output_path()
522 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_set_output_path() local
523 cfg &= ~FIMC_REG_CISCCTRL_LCDPATHEN_FIFO; in fimc_hw_set_output_path()
524 if (ctx->out_path == FIMC_IO_LCDFIFO) in fimc_hw_set_output_path()
525 cfg |= FIMC_REG_CISCCTRL_LCDPATHEN_FIFO; in fimc_hw_set_output_path()
526 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_set_output_path()
531 u32 cfg = readl(dev->regs + FIMC_REG_CIREAL_ISIZE); in fimc_hw_set_input_addr() local
532 cfg |= FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS; in fimc_hw_set_input_addr()
533 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE); in fimc_hw_set_input_addr()
535 writel(addr->y, dev->regs + FIMC_REG_CIIYSA(0)); in fimc_hw_set_input_addr()
536 writel(addr->cb, dev->regs + FIMC_REG_CIICBSA(0)); in fimc_hw_set_input_addr()
537 writel(addr->cr, dev->regs + FIMC_REG_CIICRSA(0)); in fimc_hw_set_input_addr()
539 cfg &= ~FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS; in fimc_hw_set_input_addr()
540 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE); in fimc_hw_set_input_addr()
546 int i = (index == -1) ? 0 : index; in fimc_hw_set_output_addr()
548 writel(addr->y, dev->regs + FIMC_REG_CIOYSA(i)); in fimc_hw_set_output_addr()
549 writel(addr->cb, dev->regs + FIMC_REG_CIOCBSA(i)); in fimc_hw_set_output_addr()
550 writel(addr->cr, dev->regs + FIMC_REG_CIOCRSA(i)); in fimc_hw_set_output_addr()
552 i, addr->y, addr->cb, addr->cr); in fimc_hw_set_output_addr()
553 } while (index == -1 && ++i < FIMC_MAX_OUT_BUFS); in fimc_hw_set_output_addr()
559 u32 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_camera_polarity() local
561 cfg &= ~(FIMC_REG_CIGCTRL_INVPOLPCLK | FIMC_REG_CIGCTRL_INVPOLVSYNC | in fimc_hw_set_camera_polarity()
565 if (cam->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) in fimc_hw_set_camera_polarity()
566 cfg |= FIMC_REG_CIGCTRL_INVPOLPCLK; in fimc_hw_set_camera_polarity()
568 if (cam->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) in fimc_hw_set_camera_polarity()
569 cfg |= FIMC_REG_CIGCTRL_INVPOLVSYNC; in fimc_hw_set_camera_polarity()
571 if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) in fimc_hw_set_camera_polarity()
572 cfg |= FIMC_REG_CIGCTRL_INVPOLHREF; in fimc_hw_set_camera_polarity()
574 if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) in fimc_hw_set_camera_polarity()
575 cfg |= FIMC_REG_CIGCTRL_INVPOLHSYNC; in fimc_hw_set_camera_polarity()
577 if (cam->flags & V4L2_MBUS_FIELD_EVEN_LOW) in fimc_hw_set_camera_polarity()
578 cfg |= FIMC_REG_CIGCTRL_INVPOLFIELD; in fimc_hw_set_camera_polarity()
580 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_camera_polarity()
601 const struct fimc_vid_cap *vc = &fimc->vid_cap; in fimc_hw_set_camera_source()
602 const struct fimc_frame *f = &vc->ctx->s_frame; in fimc_hw_set_camera_source()
603 u32 bus_width, cfg = 0; in fimc_hw_set_camera_source() local
606 switch (source->fimc_bus_type) { in fimc_hw_set_camera_source()
609 if (fimc_fmt_is_user_defined(f->fmt->color)) { in fimc_hw_set_camera_source()
610 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_set_camera_source()
615 if (vc->ci_fmt.code == pix_desc[i].pixelcode) { in fimc_hw_set_camera_source()
616 cfg = pix_desc[i].cisrcfmt; in fimc_hw_set_camera_source()
623 v4l2_err(&vc->ve.vdev, in fimc_hw_set_camera_source()
625 vc->ci_fmt.code); in fimc_hw_set_camera_source()
626 return -EINVAL; in fimc_hw_set_camera_source()
629 if (source->fimc_bus_type == FIMC_BUS_TYPE_ITU_601) { in fimc_hw_set_camera_source()
631 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_set_camera_source()
633 cfg |= FIMC_REG_CISRCFMT_ITU601_16BIT; in fimc_hw_set_camera_source()
634 } /* else defaults to ITU-R BT.656 8-bit */ in fimc_hw_set_camera_source()
637 if (fimc_fmt_is_user_defined(f->fmt->color)) in fimc_hw_set_camera_source()
638 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_set_camera_source()
646 cfg |= (f->o_width << 16) | f->o_height; in fimc_hw_set_camera_source()
647 writel(cfg, fimc->regs + FIMC_REG_CISRCFMT); in fimc_hw_set_camera_source()
655 u32 cfg = readl(fimc->regs + FIMC_REG_CIWDOFST); in fimc_hw_set_camera_offset() local
657 cfg &= ~(FIMC_REG_CIWDOFST_HOROFF_MASK | FIMC_REG_CIWDOFST_VEROFF_MASK); in fimc_hw_set_camera_offset()
658 cfg |= FIMC_REG_CIWDOFST_OFF_EN | in fimc_hw_set_camera_offset()
659 (f->offs_h << 16) | f->offs_v; in fimc_hw_set_camera_offset()
661 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST); in fimc_hw_set_camera_offset()
664 hoff2 = f->o_width - f->width - f->offs_h; in fimc_hw_set_camera_offset()
665 voff2 = f->o_height - f->height - f->offs_v; in fimc_hw_set_camera_offset()
666 cfg = (hoff2 << 16) | voff2; in fimc_hw_set_camera_offset()
667 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST2); in fimc_hw_set_camera_offset()
673 const struct fimc_vid_cap *vid_cap = &fimc->vid_cap; in fimc_hw_set_camera_type()
675 u32 cfg, tmp; in fimc_hw_set_camera_type() local
677 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_camera_type()
680 cfg &= ~(FIMC_REG_CIGCTRL_TESTPAT_MASK | FIMC_REG_CIGCTRL_SELCAM_ITU_A | in fimc_hw_set_camera_type()
685 switch (source->fimc_bus_type) { in fimc_hw_set_camera_type()
687 cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI; in fimc_hw_set_camera_type()
689 if (source->mux_id == 0) in fimc_hw_set_camera_type()
690 cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI_A; in fimc_hw_set_camera_type()
693 switch (vid_cap->ci_fmt.code) { in fimc_hw_set_camera_type()
700 cfg |= FIMC_REG_CIGCTRL_CAM_JPEG; in fimc_hw_set_camera_type()
703 v4l2_err(&vid_cap->ve.vdev, in fimc_hw_set_camera_type()
705 vid_cap->ci_fmt.code); in fimc_hw_set_camera_type()
706 return -EINVAL; in fimc_hw_set_camera_type()
710 writel(tmp, fimc->regs + FIMC_REG_CSIIMGFMT); in fimc_hw_set_camera_type()
713 if (source->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */ in fimc_hw_set_camera_type()
714 cfg |= FIMC_REG_CIGCTRL_SELCAM_ITU_A; in fimc_hw_set_camera_type()
715 if (vid_cap->ci_fmt.code == MEDIA_BUS_FMT_JPEG_1X8) in fimc_hw_set_camera_type()
716 cfg |= FIMC_REG_CIGCTRL_CAM_JPEG; in fimc_hw_set_camera_type()
719 cfg |= FIMC_REG_CIGCTRL_CAMIF_SELWB; in fimc_hw_set_camera_type()
722 if (fimc->variant->has_isp_wb) in fimc_hw_set_camera_type()
723 cfg |= FIMC_REG_CIGCTRL_CAMIF_SELWB; in fimc_hw_set_camera_type()
728 v4l2_err(&vid_cap->ve.vdev, in fimc_hw_set_camera_type()
730 source->fimc_bus_type); in fimc_hw_set_camera_type()
731 return -EINVAL; in fimc_hw_set_camera_type()
733 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_camera_type()
740 u32 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_clear_irq() local
741 cfg |= FIMC_REG_CIGCTRL_IRQ_CLR; in fimc_hw_clear_irq()
742 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_clear_irq()
747 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_enable_scaler() local
749 cfg |= FIMC_REG_CISCCTRL_SCALERSTART; in fimc_hw_enable_scaler()
751 cfg &= ~FIMC_REG_CISCCTRL_SCALERSTART; in fimc_hw_enable_scaler()
752 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); in fimc_hw_enable_scaler()
757 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL); in fimc_hw_activate_input_dma() local
759 cfg |= FIMC_REG_MSCTRL_ENVID; in fimc_hw_activate_input_dma()
761 cfg &= ~FIMC_REG_MSCTRL_ENVID; in fimc_hw_activate_input_dma()
762 writel(cfg, dev->regs + FIMC_REG_MSCTRL); in fimc_hw_activate_input_dma()
770 if (dev->drv_data->cistatus2) { in fimc_hw_get_frame_index()
771 reg = readl(dev->regs + FIMC_REG_CISTATUS2) & 0x3f; in fimc_hw_get_frame_index()
772 return reg - 1; in fimc_hw_get_frame_index()
775 reg = readl(dev->regs + FIMC_REG_CISTATUS); in fimc_hw_get_frame_index()
786 if (!dev->drv_data->cistatus2) in fimc_hw_get_prev_frame_index()
787 return -1; in fimc_hw_get_prev_frame_index()
789 reg = readl(dev->regs + FIMC_REG_CISTATUS2); in fimc_hw_get_prev_frame_index()
790 return ((reg >> 7) & 0x3f) - 1; in fimc_hw_get_prev_frame_index()
793 /* Locking: the caller holds fimc->slock */
796 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled); in fimc_activate_capture()
810 struct regmap *map = fimc->sysreg; in fimc_hw_camblk_cfg_writeback()
821 if (!WARN(fimc->id >= 3, "not supported id: %d\n", fimc->id)) in fimc_hw_camblk_cfg_writeback()
822 val = 0x1 << (fimc->id + 20); in fimc_hw_camblk_cfg_writeback()