Home
last modified time | relevance | path

Searched +full:- +full:bit (Results 1 – 25 of 1112) sorted by relevance

12345678910>>...45

/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DMSP430Target.def1 //===--- MSP430Target.def - MSP430 Feature/Processor Database----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // Target/MSP430/gen-msp430-def.py - use this tool rather than adding
15 //===----------------------------------------------------------------------===//
203 // With 16-bit hardware multiplier
204 MSP430_MCU_FEAT("msp430c336", "16bit")
205 MSP430_MCU_FEAT("msp430c337", "16bit")
206 MSP430_MCU_FEAT("msp430cg4616", "16bit")
207 MSP430_MCU_FEAT("msp430cg4617", "16bit")
[all …]
/freebsd/sys/dev/dpaa2/
H A Ddpaa2_ni_dpkg.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause
4 * Copyright © 2013-2015 Freescale Semiconductor, Inc.
41 * Copyright © 2021-2022 Dmitry Salychev
68 #define BIT(x) (1ul << (x)) macro
71 * DPKG_NUM_OF_MASKS - Number of masks per key extraction
76 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
81 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
93 * enum dpkg_extract_type - Enumeration for selecting extraction type
96 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
18 #define BAC_OOBS_SEL BIT(4)
20 #define B_BAC_EQ_SEL BIT(5)
24 #define B_PCIE_BIT_PSAVE BIT(15)
26 #define OFFSET_CAL_MODE BIT(13)
27 #define BAC_RX_TEST_EN BIT(6)
32 #define B_PCIE_BIT_PINOUT_DIS BIT(3)
37 #define B_PCIE_BIT_RD_SEL BIT(2)
54 #define B_AX_CLK_CALIB_EN BIT(12)
55 #define B_AX_CALIB_EN BIT(13)
[all …]
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_mcs()
62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_nss()
71 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
72 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
73 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
76 #define RTW89_TXWD_BODY0_STF_MODE BIT(10)
77 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
[all …]
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dmmintrin.h1 /*===---- mmintrin.h - MMX intrinsics --------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 __attribute__((__always_inline__, __nodebug__, __target__("mmx,no-evex512"), \
37 __target__("mmx,no-evex512")))
42 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
43 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
50 /// A 32-bit integer value.
51 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
59 /// Returns the lower 32 bits of a 64-bit integer vector as a 32-bit
[all …]
H A Dsmmintrin.h1 /*===---- smmintrin.h - SSE4 intrinsics ------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
22 __target__("sse4.1,no-evex512"), __min_vector_width__(128)))
41 /// Rounds up each element of the 128-bit vector of [4 x float] to an
42 /// integer and returns the rounded values in a 128-bit vector of
54 /// A 128-bit vector of [4 x float] values to be rounded up.
55 /// \returns A 128-bit vector of [4 x float] containing the rounded values.
58 /// Rounds up each element of the 128-bit vector of [2 x double] to an
59 /// integer and returns the rounded values in a 128-bit vector of
[all …]
H A Demmintrin.h1 /*===---- emmintrin.h - SSE2 intrinsics ------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
54 __target__("sse2,no-evex512"), __min_vector_width__(128)))
57 __target__("mmx,sse2,no-evex512"), __min_vector_width__(64)))
59 /// Adds lower double-precision values in both operands and returns the
61 /// are copied from the upper double-precision value of the first operand.
68 /// A 128-bit vector of [2 x double] containing one of the source operands.
70 /// A 128-bit vector of [2 x double] containing one of the source operands.
71 /// \returns A 128-bit vector of [2 x double] whose lower 64 bits contain the
[all …]
H A Davxvnniint16intrin.h1 /*===----------- avxvnniint16intrin.h - AVXVNNIINT16 intrinsics-------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
27 /// corresponding unsigned 16-bit integers in \a __B, producing 2 intermediate
28 /// signed 16-bit results. Sum these 2 results with the corresponding
29 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
40 /// A 128-bit vector of [4 x int].
42 /// A 128-bit vector of [8 x short].
44 /// A 128-bit vector of [8 x unsigned short].
[all …]
/freebsd/secure/lib/libcrypto/man/man3/
H A DOPENSSL_ia32cap.31 .\" -*- mode: troff; coding: utf-8 -*-
58 .TH OPENSSL_IA32CAP 3ossl 2025-09-30 3.5.4 OpenSSL
64 OPENSSL_ia32cap \- the x86[_64] processor capabilities vector
74 stored internally as ten 32\-bit capability vectors and for simplicity
75 represented logically below as five 64\-bit vectors. This logical
81 environment variable capability bit modifications are applied. After toolkit
94 .IP "bit #0+4 denoting presence of Time-Stamp Counter;" 4
95 .IX Item "bit #0+4 denoting presence of Time-Stamp Counter;"
97 .IP "bit #0+19 denoting availability of CLFLUSH instruction;" 4
98 .IX Item "bit #0+19 denoting availability of CLFLUSH instruction;"
[all …]
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Drenesas,cmt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
26 - items:
27 - enum:
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
[all …]
/freebsd/contrib/wpa/src/common/
H A Dieee802_11_defs.h3 * Copyright (c) 2002-2019, Jouni Malinen <j@w1.fi>
4 * Copyright (c) 2007-2008 Intel Corporation
39 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
41 (((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4)
105 #define WLAN_CAPABILITY_ESS BIT(0)
106 #define WLAN_CAPABILITY_IBSS BIT(1)
107 #define WLAN_CAPABILITY_CF_POLLABLE BIT(2)
108 #define WLAN_CAPABILITY_CF_POLL_REQUEST BIT(3)
109 #define WLAN_CAPABILITY_PRIVACY BIT(4)
110 #define WLAN_CAPABILITY_SHORT_PREAMBLE BIT(5)
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
18 #define BIT_RST_TRXDMA_INTF BIT(20)
19 #define BIT_RX_TAG_EN BIT(15)
23 #define BIT_DBI_RFLAG BIT(17)
24 #define BIT_DBI_WFLAG BIT(16)
31 #define BIT_MDIO_WFLAG_V1 BIT(5)
32 #define RTW_PCI_MDIO_PG_SZ BIT(5)
38 #define BIT_CLKREQ_SW_EN BIT(4)
39 #define BIT_L1_SW_EN BIT(3)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmc13xxx.txt4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892"
7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used
8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
12 Sub-nodes:
13 - codec: Contain the Audio Codec node.
14 - adc-port: Contain PMIC SSI port number used for ADC.
15 - dac-port: Contain PMIC SSI port number used for DAC.
16 - leds : Contain the led nodes and initial register values in property
[all …]
/freebsd/sys/contrib/dev/athk/ath11k/
H A Drx_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
88 #define RX_ATTENTION_INFO1_FIRST_MPDU BIT(0)
89 #define RX_ATTENTION_INFO1_RSVD_1A BIT(1)
90 #define RX_ATTENTION_INFO1_MCAST_BCAST BIT(2)
91 #define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND BIT(3)
92 #define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT BIT(4)
93 #define RX_ATTENTION_INFO1_POWER_MGMT BIT(5)
94 #define RX_ATTENTION_INFO1_NON_QOS BIT(6)
95 #define RX_ATTENTION_INFO1_NULL_DATA BIT(7)
[all …]
/freebsd/sys/dev/flash/flexspi/
H A Dflex_spi.h1 /*-
29 #define BIT(x) (1 << (x)) macro
35 #define FSPI_MCR0_LEARN_EN BIT(15)
36 #define FSPI_MCR0_SCRFRUN_EN BIT(14)
37 #define FSPI_MCR0_OCTCOMB_EN BIT(13)
38 #define FSPI_MCR0_DOZE_EN BIT(12)
39 #define FSPI_MCR0_HSEN BIT(11)
40 #define FSPI_MCR0_SERCLKDIV BIT(8)
41 #define FSPI_MCR0_ATDF_EN BIT(7)
42 #define FSPI_MCR0_ARDF_EN BIT(6)
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_dh895xcc/
H A Dadf_dh895xcc_hw_data.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
31 #define ADF_DH895XCC_ENABLE_AE_ECC_ERR BIT(28)
32 #define ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
35 #define ADF_DH895XCC_ERRSSMSH_EN BIT(3)
38 /* BIT(2) enables the logging of push/pull data errors. */
39 #define ADF_DH895XCC_PPERR_EN (BIT(2))
50 #define ADF_DH895XCC_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
51 #define ADF_DH895XCC_ERRMSK1_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
52 #define ADF_DH895XCC_ERRMSK3_CERR (BIT(7))
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchFixupKinds.h1 //===- LoongArchFixupKinds.h - LoongArch Specific Fixup Entries -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
26 // 16-bit fixup corresponding to %b16(foo) for instructions like bne.
28 // 21-bit fixup corresponding to %b21(foo) for instructions like bnez.
30 // 26-bit fixup corresponding to %b26(foo)/%plt(foo) for instructions b/bl.
32 // 20-bit fixup corresponding to %abs_hi20(foo) for instruction lu12i.w.
34 // 12-bit fixup corresponding to %abs_lo12(foo) for instruction ori.
36 // 20-bit fixup corresponding to %abs64_lo20(foo) for instruction lu32i.d.
38 // 12-bit fixup corresponding to %abs_hi12(foo) for instruction lu52i.d.
[all …]
/freebsd/sys/compat/linuxkpi/common/include/linux/
H A Dbitops.h1 /*-
5 * Copyright (c) 2013-2017 Mellanox Technologies, Ltd.
38 #define BIT(nr) (1UL << (nr)) macro
44 #define BITMAP_LAST_WORD_MASK(n) (~0UL >> (BITS_PER_LONG - (n)))
46 #define BIT_MASK(nr) (1UL << ((nr) & (BITS_PER_LONG - 1)))
48 #define GENMASK(h, l) (((~0UL) >> (BITS_PER_LONG - (h) - 1)) & ((~0UL) << (l)))
49 #define GENMASK_ULL(h, l) (((~0ULL) >> (BITS_PER_LONG_LONG - (h) - 1)) & ((~0ULL) << (l)))
68 return (ffs(mask) - 1); in __ffs()
74 return (fls(mask) - 1); in __fls()
80 return (ffsl(mask) - 1); in __ffsl()
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
35 #define MT_HW_INFO_BASE ((dev)->reg_map[MT_HW_BASE])
40 #define MT_TOP_3NSS BIT(24)
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
49 #define MT_TOP_MISC2_FW_PWR_ON BIT(1)
59 #define MT_MCU_PCIE_REMAP_2 ((dev)->reg_map[MT_PCIE_REMAP_2])
62 #define MT_PCIE_REMAP_BASE_2 ((dev)->reg_map[MT_PCIE_REMAP_BASE2])
69 #define MT_HIF(ofs) ((dev)->reg_map[MT_HIF_BASE] + (ofs))
71 #define MT_HIF_LOGIC_RST_N BIT(4)
74 #define MT_PDMA_AXI_SLPPROT_ENABLE BIT(0)
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
46 #define MT_TX_FREE_PAIR BIT(31)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
58 #define MT_TXD1_AMSDU BIT(23)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD2_FIXED_RATE BIT(30)
72 #define MT_TXD2_HTC_VLD BIT(13)
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_inline.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
19 #define ADF_C4XXX_SADB_SIZE_BIT BIT(24)
21 ((accel_dev)->aram_info->sadb_region_size / 32)
24 /* SADB CTRL register bit offsets */
39 #define ADF_C4XXX_STATS_REQUEST_ENABLED BIT(16)
40 #define ADF_C4XXX_STATS_REQUEST_DISABLED ~BIT(16)
45 #define ADF_C4XXX_MAC_STATS_READY BIT(0)
48 #define ADF_C4XXX_MAC_ERROR_TX_UNDERRUN BIT(6)
49 #define ADF_C4XXX_MAC_ERROR_TX_FCS BIT(7)
[all …]
/freebsd/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_c3xxx/
H A Dadf_c3xxx_hw_data.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2025 Intel Corporation */
22 #define ADF_C3XXX_POWERGATE_PKE BIT(24)
23 #define ADF_C3XXX_POWERGATE_CY BIT(23)
28 #define ADF_C3XXX_ENABLE_AE_ECC_ERR BIT(28)
29 #define ADF_C3XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
32 #define ADF_C3XXX_ERRSSMSH_EN BIT(3)
36 /* BIT(2) enables the logging of push/pull data errors. */
37 #define ADF_C3XXX_PPERR_EN (BIT(2))
45 #define ADF_C3XXX_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_200xx/
H A Dadf_200xx_hw_data.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2025 Intel Corporation */
22 #define ADF_200XX_POWERGATE_PKE BIT(24)
23 #define ADF_200XX_POWERGATE_CY BIT(23)
30 #define ADF_200XX_ENABLE_AE_ECC_ERR BIT(28)
31 #define ADF_200XX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
34 #define ADF_200XX_ERRSSMSH_EN BIT(3)
38 /* BIT(2) enables the logging of push/pull data errors. */
39 #define ADF_200XX_PPERR_EN (BIT(2))
47 #define ADF_200XX_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_c62x/
H A Dadf_c62x_hw_data.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
23 #define ADF_C62X_POWERGATE_PKE BIT(24)
24 #define ADF_C62X_POWERGATE_DC BIT(23)
29 #define ADF_C62X_ENABLE_AE_ECC_ERR BIT(28)
30 #define ADF_C62X_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
35 #define ADF_C62X_ERRSSMSH_EN (BIT(3))
36 /* BIT(2) enables the logging of push/pull data errors. */
37 #define ADF_C62X_PPERR_EN (BIT(2))
45 #define ADF_C62X_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
[all …]

12345678910>>...45