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/linux/Documentation/devicetree/bindings/firmware/
H A Dthead,th1520-aon.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/thead,th1520-aon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-HEAD TH1520 AON (Always-On) Firmware
10 The Always-On (AON) subsystem in the TH1520 SoC is responsible for managing
11 low-power states, system wakeup events, and power management tasks. It is
15 At the heart of the AON subsystem is the E902, a low-power core that executes
18 SoC and the AON subsystem is handled through a mailbox interface, which
19 enables message-based interactions with the AON firmware.
[all …]
/linux/drivers/clk/sprd/
H A Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
[all …]
/linux/Documentation/devicetree/bindings/timestamp/
H A Dnvidia,tegra194-hte.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dipen Patel <dipenp@nvidia.com>
19 GPIO lines from the AON (always on) GPIO controller.
24 - nvidia,tegra194-gte-aon
25 - nvidia,tegra194-gte-lic
26 - nvidia,tegra234-gte-aon
27 - nvidia,tegra234-gte-lic
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/linux/Documentation/devicetree/bindings/mips/brcm/
H A Dsoc.txt5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
6 "brcm,bcm3384-viper", "brcm,bcm33843-viper"
12 The experimental -viper variants are for running Linux on the 3384's
16 ----------------
21 = Always-On control block (AON CTRL)
23 This hardware provides control registers for the "always-on" (even in low-power
27 - compatible : should be one of
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
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/linux/drivers/clk/ti/
H A Dclk-33xx.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Tero Kristo (t-kristo@ti.com)
12 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/am3.h>
19 "clk-24mhz-clkctrl:0000:0",
151 "l3-aon-clkctrl:0000:19",
152 "l3-aon-clkctrl:0000:30",
157 "l3-aon-clkctrl:0000:20",
167 "l3-aon-clkctrl:0000:22",
192 { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
[all …]
/linux/include/linux/firmware/imx/
H A Dsm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
14 #define SCMI_IMX95_CTRL_PDM_CLK_SEL 0 /* AON PDM clock sel */
15 #define SCMI_IMX95_CTRL_MQS1_SETTINGS 1 /* AON MQS settings */
16 #define SCMI_IMX95_CTRL_SAI1_MCLK 2 /* AON SAI1 MCLK */
21 #define SCMI_IMX94_CTRL_PDM_CLK_SEL 0U /*!< AON PDM clock sel */
22 #define SCMI_IMX94_CTRL_MQS1_SETTINGS 1U /*!< AON MQS settings */
24 #define SCMI_IMX94_CTRL_SAI1_MCLK 3U /*!< AON SAI1 MCLK */
35 return -EOPNOTSUPP; in scmi_imx_misc_ctrl_get()
40 return -EOPNOTSUPP; in scmi_imx_misc_ctrl_set()
52 return -EOPNOTSUPP; in scmi_imx_cpu_start()
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/linux/Documentation/devicetree/bindings/clock/
H A Dsprd,sc9860-clk.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/sprd,sc9860-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
17 - sprd,sc9860-agcp-gate
18 - sprd,sc9860-aonsecure-clk
19 - sprd,sc9860-aon-gate
[all …]
H A Dbrcm,kona-ccu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/brcm,kona-ccu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <florian.fainelli@broadcom.com>
11 - Ray Jui <rjui@broadcom.com>
12 - Scott Branden <sbranden@broadcom.com>
19 - include/dt-bindings/clock/bcm281xx.h for BCM281XX family
20 - include/dt-bindings/clock/bcm21664.h for BCM21664 family
25 - brcm,bcm11351-aon-ccu
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra234-pinmux-aon.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-aon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra234 AON Pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-pinmux-aon
21 "^pinmux(-[a-z0-9-]+)?$":
26 $ref: nvidia,tegra234-pinmux-common.yaml
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H A Dstarfive,jh7110-aon-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 AON Pin Controller
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
18 - Hal Feng <hal.feng@starfivetech.com>
22 const: starfive,jh7110-aon-pinctrl
33 interrupt-controller: true
35 '#interrupt-cells':
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/linux/drivers/clk/bcm/
H A Dclk-iproc-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
90 return -EINVAL; in pll_calc_param()
92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
102 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
103 vco_out->ndiv_frac = ndiv_frac; in pll_calc_param()
104 vco_out->pdiv = 1; in pll_calc_param()
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H A Dclk-sr.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
37 .aon = AON_VAL(0x0, 5, 1, 0),
88 iproc_pll_clk_setup(pdev->dev.of_node, in sr_genpll0_clk_init()
97 .aon = AON_VAL(0x0, 1, 13, 12),
147 iproc_pll_clk_setup(pdev->dev.of_node, in sr_genpll2_clk_init()
156 .aon = AON_VAL(0x0, 1, 19, 18),
186 CLK_OF_DECLARE(sr_genpll3_clk, "brcm,sr-genpll3", sr_genpll3_clk_init);
[all …]
H A Dclk-bcm281xx.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
8 #include "dt-bindings/clock/bcm281xx.h"
31 /* AON CCU */
61 BCM281XX_CCU_COMMON(aon, AON),
64 KONA_CLK(aon, hub_timer, peri),
66 KONA_CLK(aon, pmu_bsc, peri),
68 KONA_CLK(aon, pmu_bsc_var, peri),
H A Dclk-bcm21664.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
8 #include "dt-bindings/clock/bcm21664.h"
30 /* AON CCU */
43 BCM21664_CCU_COMMON(aon, AON),
50 KONA_CLK(aon, hub_timer, peri),
/linux/Documentation/devicetree/bindings/soc/starfive/
H A Dstarfive,jh7110-syscon.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Qiu <william.qiu@starfivetech.com>
19 - items:
20 - const: starfive,jh7110-sys-syscon
21 - const: syscon
22 - const: simple-mfd
23 - items:
[all …]
/linux/drivers/pinctrl/starfive/
H A Dpinctrl-starfive-jh7110-aon.c1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl / GPIO driver for StarFive JH7110 SoC aon controller
16 #include <linux/pinctrl/pinconf-generic.h>
24 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
29 #include "pinctrl-starfive-jh7110.h"
81 if (pin < sfp->gc.ngpio && func == 0) in jh7110_aon_set_one_pin_mux()
93 return -1; in jh7110_aon_get_padcfg_base()
105 mis = readl_relaxed(sfp->base + JH7110_AON_GPIOMIS); in jh7110_aon_irq_handler()
107 generic_handle_domain_irq(sfp->gc.irq.domain, pin); in jh7110_aon_irq_handler()
118 writel_relaxed(0, sfp->base + JH7110_AON_GPIOIE); in jh7110_aon_init_hw()
[all …]
/linux/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,brcmstb.txt2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
[all …]
/linux/include/dt-bindings/clock/
H A Dbcm21664.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #define BCM21664_DT_ROOT_CCU_COMPAT "brcm,bcm21664-root-ccu"
17 #define BCM21664_DT_AON_CCU_COMPAT "brcm,bcm21664-aon-ccu"
18 #define BCM21664_DT_MASTER_CCU_COMPAT "brcm,bcm21664-master-ccu"
19 #define BCM21664_DT_SLAVE_CCU_COMPAT "brcm,bcm21664-slave-ccu"
26 /* aon CCU clock ids */
H A Dbcm281xx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
21 #define BCM281XX_DT_ROOT_CCU_COMPAT "brcm,bcm11351-root-ccu"
22 #define BCM281XX_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu"
23 #define BCM281XX_DT_HUB_CCU_COMPAT "brcm,bcm11351-hub-ccu"
24 #define BCM281XX_DT_MASTER_CCU_COMPAT "brcm,bcm11351-master-ccu"
25 #define BCM281XX_DT_SLAVE_CCU_COMPAT "brcm,bcm11351-slave-ccu"
32 /* aon CCU clock ids */
/linux/Documentation/devicetree/bindings/arm/omap/
H A Dprcm.txt11 - compatible: Must be one of:
12 "ti,am3-prcm"
13 "ti,am4-prcm"
14 "ti,omap2-prcm"
15 "ti,omap3-prm"
16 "ti,omap3-cm"
17 "ti,omap4-cm1"
18 "ti,omap4-prm"
19 "ti,omap4-cm2"
20 "ti,omap4-scrm"
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dqcom,spi-qpic-snand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Md sadre Alam <quic_mdalam@quicinc.com>
13 The QCOM QPIC-SPI-NAND flash controller is an extended version of
15 and parallel mode. It supports typical SPI-NAND page cache
20 - $ref: /schemas/spi/spi-controller.yaml#
25 - items:
26 - enum:
[all …]
/linux/Documentation/devicetree/bindings/ufs/
H A Dsprd,ums9620-ufs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ufs/sprd,ums9620-ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Zhe Wang <zhe.wang1@unisoc.com>
13 - $ref: ufs-common.yaml
17 const: sprd,ums9620-ufs
25 clock-names:
27 - const: controller_eb
28 - const: cfg_eb
[all …]
/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra234-cbb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <sumitg@nvidia.com>
15 of multiple sub-blocks connected to each other to create a topology.
17 which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and
41 pattern: "^[a-z]+-fabric@[0-9a-f]+$"
45 - nvidia,tegra234-aon-fabric
46 - nvidia,tegra234-bpmp-fabric
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm7445.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #address-cells = <2>;
6 #size-cells = <2>;
9 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "brcm,brahma-b15";
22 enable-method = "brcm,brahma-b15";
27 compatible = "brcm,brahma-b15";
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
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