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/linux/arch/arm64/crypto/
H A Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
37 * The SHA-512 round constants
85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
90 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
91 add v\i3\().2d, v\i3\().2d, v5.2d
93 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
[all …]
H A Dsha2-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions
12 .arch armv8-a+crypto
32 add t1.4s, v\s0\().4s, \rc\().4s
37 add t0.4s, v\s0\().4s, \rc\().4s
45 sha256su0 v\s0\().4s, v\s1\().4s
47 sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s
51 * The SHA-256 round constants
81 ld1 { v0.4s- v3.4s}, [x8], #64
82 ld1 { v4.4s- v7.4s}, [x8], #64
[all …]
/linux/arch/alpha/kernel/
H A Dentry.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Kernel entry-points.
8 #include <asm/asm-offsets.h>
35 .size \func, . - \func
39 * This defines the normal kernel pt-regs layout.
41 * regs 9-15 preserved by C code
42 * regs 16-18 saved by PAL-code
43 * regs 29-30 saved and set up by PAL-code
44 * JRP - Save regs 16-18 in a special area of the stack, so that
45 * the palcode-provided values are available to the signal handler.
[all …]
/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu2_hw_h264_dec.c1 // SPDX-License-Identifier: GPL-2.0
6 * Hertz Wong <hertz.wong@rock-chips.com>
7 * Herman Chen <herman.chen@rock-chips.com>
16 #include <media/v4l2-mem2mem.h>
28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
[all …]
H A Dhantro_g1_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define G1_REG_CONFIG_DEC_OUTSWAP32_E BIT(19)
56 #define G1_REG_DEC_CTRL0_PIC_TOPFIELD_E BIT(19)
75 #define G1_REG_DEC_CTRL1_MB_WIDTH_OFF(x) (((x) & 0xf) << 19)
88 #define G1_REG_DEC_CTRL2_CH_QP_OFFSET(x) (((x) & 0x1f) << 19)
147 #define G1_REG_DEC_CTRL4_TTMBF BIT(19)
179 #define G1_REG_DEC_CTRL5_REF_DIST_FWD(x) (((x) & 0x1f) << 19)
196 #define G1_REG_DEC_CTRL6_REFIDX1_ACTIVE(x) (((x) & 0x1f) << 19)
293 #define G1_REG_REF_BUF_CTRL_REFBU_THR(x) (((x) & 0xfff) << 19)
300 #define G1_REG_REF_BUF_CTRL2_REFBU2_THR(x) (((x) & 0xfff) << 19)
[all …]
H A Dhantro_g1_mpeg2_dec.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <media/v4l2-mem2mem.h>
25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
[all …]
/linux/drivers/media/platform/sunxi/sun6i-csi/
H A Dsun6i_csi_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing)
5 * Copyright 2021-2022 Bootlin
18 #define SUN6I_CSI_EN_PTN_CYCLE(v) (((v) << 16) & GENMASK(23, 16)) argument
29 #define SUN6I_CSI_IF_CFG_FIELD_DT_PCLK_SHIFT(v) (((v) << 24) & GENMASK(27, 24)) argument
33 #define SUN6I_CSI_IF_CFG_FIELD_POSITIVE (0 << 19)
34 #define SUN6I_CSI_IF_CFG_FIELD_NEGATIVE (1 << 19)
57 #define SUN6I_CSI_CAP_MASK(v) (((v) << 2) & GENMASK(5, 2)) argument
70 #define SUN6I_CSI_CH_CFG_PAD_VAL(v) (((v) << 24) & GENMASK(31, 24)) argument
71 #define SUN6I_CSI_CH_CFG_INPUT_FMT(v) (((v) << 20) & GENMASK(23, 20)) argument
[all …]
/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
28 mode "640x480-60"
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
52 mode "640x480-75"
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
[all …]
/linux/sound/soc/fsl/
H A Dfsl_esai.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * fsl_esai.h - ALSA ESAI interface for the Freescale i.MX SoC
52 /* ESAI Control Register -- REG_ESAI_ECR 0x8 */
53 #define ESAI_ECR_ETI_SHIFT 19
72 /* ESAI Status Register -- REG_ESAI_ESR 0xC */
108 * Transmit FIFO Configuration Register -- REG_ESAI_TFCR 0x10
109 * Receive FIFO Configuration Register -- REG_ESAI_RFCR 0x18
111 #define ESAI_xFCR_TIEN_SHIFT 19
114 #define ESAI_xFCR_REXT_SHIFT 19
119 #define ESAI_xFCR_xWA_MASK (((1 << ESAI_xFCR_xWA_WIDTH) - 1) << ESAI_xFCR_xWA_SHIFT)
[all …]
/linux/include/linux/
H A Dinet.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * $Id: Space.c,v 0.8.4.5 1992/12/12 19:25:04 bir7 Exp $
13 * $Id: arp.c,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
14 * $Id: arp.h,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
15 * $Id: dev.c,v 0.8.4.13 1993/01/23 18:00:11 bir7 Exp $
16 * $Id: dev.h,v 0.8.4.7 1993/01/23 18:00:11 bir7 Exp $
17 * $Id: eth.c,v 0.8.4.4 1993/01/22 23:21:38 bir7 Exp $
18 * $Id: eth.h,v 0.8.4.1 1992/11/10 00:17:18 bir7 Exp $
19 * $Id: icmp.c,v 0.8.4.9 1993/01/23 18:00:11 bir7 Exp $
20 * $Id: icmp.h,v 0.8.4.2 1992/11/15 14:55:30 bir7 Exp $
[all …]
/linux/drivers/media/dvb-frontends/
H A Dlnbp21.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * lnbp21.h - driver for lnb supply and control ic lnbp21
21 /* [RW] 0=low voltage (13/14V, vert pol)
22 1=high voltage (18/19V,horiz pol) */
24 /* [RW] increase LNB voltage by 1V:
25 0=13/18V; 1=14/19V */
31 0:Iout=500-650mA Isc=300mA
32 1:Iout=400-550mA Isc=200mA */
34 /* [RW] short-circuit protect:
/linux/sound/soc/qcom/
H A Dlpass-sc7280.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
5 * lpass-sc7180.c -- ALSA SoC platform-machine driver for QTi LPASS
13 #include <dt-bindings/sound/sc7180-lpass.h>
15 #include "lpass-lpaif-reg.h"
113 const struct lpass_variant *v = drvdata->variant; in sc7280_lpass_alloc_dma_channel() local
119 chan = find_first_zero_bit(&drvdata->dma_ch_bit_map, in sc7280_lpass_alloc_dma_channel()
120 v->rdma_channels); in sc7280_lpass_alloc_dma_channel()
122 if (chan >= v->rdma_channels) in sc7280_lpass_alloc_dma_channel()
123 return -EBUSY; in sc7280_lpass_alloc_dma_channel()
[all …]
H A Dlpass-lpaif-reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
11 #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \ argument
12 (v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
14 #define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port)) argument
41 #define LPAIF_I2SCTL_MODE_8CH_2 19
68 #define LPAIF_IRQ_REG_ADDR(v, addr, port) \ argument
69 (v->irq_reg_base + (addr) + v->irq_reg_stride * (port))
73 #define LPAIF_IRQEN_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x0, (port)) argument
74 #define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port)) argument
[all …]
/linux/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/
H A Dsun8i_a83t_mipi_csi2_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2020-2022 Bootlin
33 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LS_LE_ERR_DT3 BIT(19)
58 #define SUN8I_A83T_MIPI_CSI2_INT_STA1_LS_LE_ERR_DT7 BIT(19)
88 #define SUN8I_A83T_MIPI_CSI2_INT_MSK0_LS_LE_ERR_DT3 BIT(19)
134 #define SUN8I_A83T_MIPI_CSI2_CFG_SYNC_DLY_CYCLE(v) (((v) << 18) & \ argument
136 #define SUN8I_A83T_MIPI_CSI2_CFG_N_CHANNEL(v) ((((v) - 1) << 16) & \ argument
138 #define SUN8I_A83T_MIPI_CSI2_CFG_N_LANE(v) ((((v) - 1) << 4) & \ argument
147 (((ch) - 4) * 8 + 6))
149 (((ch) - 4) * 8))
/linux/drivers/irqchip/
H A Dirq-sun6i-r.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * bit 0 bits 1-15^ bits 19-31
9 * +---------+ +---------+ +---------+ +---------+
11 * +---------+ +---------+ +---------+ +---------+
14 * +------V------+ +------------+ | | | +--V------V--+ |
17 * +-------------+ +------------+ | | | +------------+ |
19 * +--V-------V--+ +--V--+ | +--V--+ | +--V--+
22 * +-------------+ | N+d | | | m | | | m+7 |
23 * | | +-----+ | +-----+ | +-----+
25 * +-------V-+ +-V----------+ +---------V--+ +--------V--------+
[all …]
/linux/drivers/staging/media/sunxi/cedrus/
H A Dcedrus_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (c) 2013-2016 Jens Kuske <jenskuske@gmail.com>
6 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
18 * * VLD : Variable-Length Decoder
96 #define VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(x, y) (24 - 4 * (y) - 8 * (x))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dregs-scaler.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* drivers/gpu/drm/exynos/regs-scaler.h
60 * 5 b0 b4 b8 bc 190 194 198 19c
127 #define SCALER_MASK(hi_b, lo_b) ((1 << ((hi_b) - (lo_b) + 1)) - 1)
154 #define SCALER_INT_EN_ILLEGAL_DST_H_POS (1 << 19)
182 #define SCALER_INT_STATUS_ILLEGAL_DST_H_POS (1 << 19)
206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
225 #define SCALER_YUV444_2P_VU 19
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
[all …]
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dhead.c44 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask), in nv50_head_flush_clr()
47 if (clr.olut) head->func->olut_clr(head); in nv50_head_flush_clr()
48 if (clr.core) head->func->core_clr(head); in nv50_head_flush_clr()
49 if (clr.curs) head->func->curs_clr(head); in nv50_head_flush_clr()
55 if (asyh->set.curs ) head->func->curs_set(head, asyh); in nv50_head_flush_set_wndw()
56 if (asyh->set.olut ) { in nv50_head_flush_set_wndw()
57 asyh->olut.offset = nv50_lut_load(&head->olut, in nv50_head_flush_set_wndw()
58 asyh->olut.buffer, in nv50_head_flush_set_wndw()
59 asyh->state.gamma_lut, in nv50_head_flush_set_wndw()
60 asyh->olut.load); in nv50_head_flush_set_wndw()
[all …]
/linux/lib/crypto/
H A Dcurve25519-fiat32.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2015-2016 The fiat-crypto Authors.
4 * Copyright (C) 2018-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
6 * This is a machine-generated formally verified implementation of Curve25519
7 * ECDH from: <https://github.com/mit-plv/fiat-crypto>. Though originally
9 * It is optimized for 32-bit machines and machines that cannot work efficiently
10 * with 128-bit integer types.
17 /* fe means field element. Here the field is \Z/(2^255-19). An element t,
23 typedef struct fe { u32 v[10]; } fe; member
28 typedef struct fe_loose { u32 v[10]; } fe_loose; member
[all …]
/linux/tools/usb/
H A Dhcd-tests.sh2 # SPDX-License-Identifier: GPL-2.0
6 # - control: any device can do this
7 # - out, in: out needs 'bulk sink' firmware, in needs 'bulk src'
8 # - iso-out, iso-in: out needs 'iso sink' firmware, in needs 'iso src'
9 # - halt: needs bulk sink+src, tests halt set/clear from host
10 # - unlink: needs bulk sink and/or src, test HCD unlink processing
11 # - loop: needs firmware that will buffer N transfers
25 # - include unlink tests
26 # - add some ${RANDOM}ness
27 # - connect several devices concurrently (same HC)
[all …]
/linux/drivers/usb/musb/
H A Dtusb6010.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* VLYNQ control register. 32-bit at offset 0x000 */
15 /* Mentor Graphics OTG core registers. 8,- 16- and 32-bit at offset 0x400 */
18 /* FIFO registers 32-bit at offset 0x600 */
21 /* Device System & Control registers. 32-bit at offset 0x800 */
34 #define TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN (1 << 19)
45 #define TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL(v) (((v) & 3) << 7) argument
69 # define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff) argument
75 #define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16) argument
79 #define TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v) (((v) & 0xf) << 25) argument
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Danalogix,anx7625.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Xin Ji <xji@analogixsemi.com>
14 The ANX7625 is an ultra-low power 4K Mobile HD Transmitter
28 enable-gpios:
32 reset-gpios:
36 vdd10-supply:
37 description: Regulator that provides the supply 1.0V power.
39 vdd18-supply:
[all …]
/linux/drivers/media/usb/dvb-usb/
H A Dvp7045.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * - TwinhanDTV Alpha/MagicBoxII USB2.0 DVB-T receiver
4 * - DigitalNow TinyUSB2 DVB-t receiver
6 * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@posteo.de)
10 * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
17 MODULE_PARM_DESC(debug, "set debugging level (1=info,xfer=2,rc=4 (or-able))." DVB_USB_DEBUG_STATUS);
28 u8 *buf = d->priv; in vp7045_usb_op()
32 if (outlen > 19) in vp7045_usb_op()
33 outlen = 19; in vp7045_usb_op()
38 ret = mutex_lock_interruptible(&d->usb_mutex); in vp7045_usb_op()
[all …]
/linux/drivers/comedi/drivers/
H A Ddac02.c1 // SPDX-License-Identifier: GPL-2.0+
11 * COMEDI - Linux Control and Measurement Device Interface
18 * Devices: [Keithley Metrabyte] DAC-02 (dac02)
20 * Updated: Tue, 11 Mar 2014 11:27:19 -0700
24 * [0] - I/O port base
34 * ------------- ------ ------------- -----------------
35 * 0 to 5V 0 21 to 22 24
37 * 0 to 10V 0 20 to 22 24
39 * +/-5V 0 21 to 22 23
41 * +/-10V 0 20 to 22 23
[all …]
/linux/arch/sparc/kernel/
H A Dptrace_32.c1 // SPDX-License-Identifier: GPL-2.0
9 * Added Linux support -miguel (weird, eh?, the original code was meant
51 unsigned long reg_window = regs->u_regs[UREG_I6]; in regwindow32_get()
56 return -EFAULT; in regwindow32_get()
60 return -EFAULT; in regwindow32_get()
69 unsigned long reg_window = regs->u_regs[UREG_I6]; in regwindow32_set()
74 return -EFAULT; in regwindow32_set()
78 return -EFAULT; in regwindow32_set()
87 const struct pt_regs *regs = target->thread.kregs; in genregs32_get()
93 membuf_write(&to, regs->u_regs, 16 * sizeof(u32)); in genregs32_get()
[all …]

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