Lines Matching +full:- +full:19 +full:v
1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* VLYNQ control register. 32-bit at offset 0x000 */
15 /* Mentor Graphics OTG core registers. 8,- 16- and 32-bit at offset 0x400 */
18 /* FIFO registers 32-bit at offset 0x600 */
21 /* Device System & Control registers. 32-bit at offset 0x800 */
34 #define TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN (1 << 19)
45 #define TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL(v) (((v) & 3) << 7) argument
69 # define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff) argument
75 #define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16) argument
79 #define TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v) (((v) & 0xf) << 25) argument
81 #define TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(v) (((v) & 0xf) << 20) argument
82 #define TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN (1 << 19)
94 /* Wake-up source clear and mask registers */
188 #define TUSB_INT_CTRL_CONF_INT_RELCYC(v) (((v) & 0x7) << 18) argument
191 #define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24) argument
192 #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26) argument
193 #define TUSB_DMA_REQ_CONF_DMA_REQ_EN(v) (((v) & 0x3f) << 20) argument
194 #define TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(v) (((v) & 0xf) << 16) argument
197 #define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f) argument
199 #define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff) argument
205 #define TUSB_DIDR1_HI_CHIP_REV(v) (((v) >> 17) & 0xf) argument