Lines Matching +full:- +full:19 +full:v
44 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask),
47 if (clr.olut) head->func->olut_clr(head);
48 if (clr.core) head->func->core_clr(head);
49 if (clr.curs) head->func->curs_clr(head);
55 if (asyh->set.curs ) head->func->curs_set(head, asyh);
56 if (asyh->set.olut ) {
57 asyh->olut.offset = nv50_lut_load(&head->olut,
58 asyh->olut.buffer,
59 asyh->state.gamma_lut,
60 asyh->olut.load);
61 head->func->olut_set(head, asyh);
68 if (asyh->set.view ) head->func->view (head, asyh);
69 if (asyh->set.mode ) head->func->mode (head, asyh);
70 if (asyh->set.core ) head->func->core_set(head, asyh);
71 if (asyh->set.base ) head->func->base (head, asyh);
72 if (asyh->set.ovly ) head->func->ovly (head, asyh);
73 if (asyh->set.dither ) head->func->dither (head, asyh);
74 if (asyh->set.procamp) head->func->procamp (head, asyh);
75 if (asyh->set.crc ) nv50_crc_atomic_set (head, asyh);
76 if (asyh->set.or ) head->func->or (head, asyh);
84 const int vib = asyc->procamp.color_vibrance - 100;
85 const int hue = asyc->procamp.vibrant_hue - 90;
87 asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
88 asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
89 asyh->set.procamp = true;
99 if (asyc->dither.mode) {
100 if (asyc->dither.mode == DITHERING_MODE_AUTO) {
101 if (asyh->base.depth > asyh->or.bpc * 3)
104 mode = asyc->dither.mode;
107 if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
108 if (asyh->or.bpc >= 8)
111 mode |= asyc->dither.depth;
115 asyh->dither.enable = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, ENABLE);
116 asyh->dither.bits = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, BITS);
117 asyh->dither.mode = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, MODE);
118 asyh->set.dither = true;
126 struct drm_connector *connector = asyc->state.connector;
127 struct drm_display_mode *omode = &asyh->state.adjusted_mode;
128 struct drm_display_mode *umode = &asyh->state.mode;
129 int mode = asyc->scaler.mode;
132 if (!asyc->scaler.full) {
136 /* Non-EDID LVDS/eDP mode. */
140 /* For the user-specified mode, we must ignore doublescan and
143 umode_vdisplay = umode->vdisplay;
144 if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
145 umode_vdisplay += umode->vtotal;
146 asyh->view.iW = umode->hdisplay;
147 asyh->view.iH = umode_vdisplay;
150 asyh->view.oW = omode_hdisplay;
151 asyh->view.oH = omode_vdisplay;
157 if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
158 (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
159 connector->display_info.is_hdmi))) {
160 u32 bX = asyc->scaler.underscan.hborder;
161 u32 bY = asyc->scaler.underscan.vborder;
162 u32 r = (asyh->view.oH << 19) / asyh->view.oW;
165 asyh->view.oW -= (bX * 2);
166 if (bY) asyh->view.oH -= (bY * 2);
167 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
169 asyh->view.oW -= (asyh->view.oW >> 4) + 32;
170 if (bY) asyh->view.oH -= (bY * 2);
171 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
183 asyh->view.oW = min(asyh->view.iW, asyh->view.oW);
184 asyh->view.oH = min(asyh->view.iH, asyh->view.oH);
202 if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) {
204 u32 r = (asyh->view.iW << 19) / asyh->view.iH;
205 asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
208 u32 r = (asyh->view.iH << 19) / asyh->view.iW;
209 asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
216 asyh->set.view = true;
223 struct drm_device *dev = head->base.base.dev;
224 struct drm_crtc *crtc = &head->base.base;
227 struct drm_property_blob *olut = asyh->state.gamma_lut,
228 *ilut = asyh->state.degamma_lut;
234 if (!head->func->ilut_check(size)) {
236 size, crtc->base.id, crtc->name);
237 return -EINVAL;
246 if (asyh->wndw.olut) {
250 if (asyh->wndw.olut != asyh->wndw.mask)
251 return -EINVAL;
257 if (!head->func->olut_identity) {
258 asyh->olut.handle = 0;
266 if (!head->func->olut(head, asyh, size)) {
268 size, crtc->base.id, crtc->name);
269 return -EINVAL;
271 asyh->olut.handle = disp->core->chan.vram.handle;
272 asyh->olut.buffer = !asyh->olut.buffer;
280 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
281 struct nv50_head_mode *m = &asyh->mode;
293 m->h.active = mode->crtc_htotal;
294 m->h.synce = mode->crtc_hsync_end - mode->crtc_hsync_start - 1;
295 m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1;
296 m->h.blanks = m->h.blanke + mode->crtc_hdisplay;
298 m->v.active = mode->crtc_vtotal;
299 m->v.synce = mode->crtc_vsync_end - mode->crtc_vsync_start - 1;
300 m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1;
301 m->v.blanks = m->v.blanke + mode->crtc_vdisplay;
304 blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active;
306 blankus /= mode->crtc_clock;
307 m->v.blankus = blankus;
309 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
310 m->v.blank2e = m->v.active + m->v.blanke;
311 m->v.blank2s = m->v.blank2e + mode->crtc_vdisplay;
312 m->v.active = (m->v.active * 2) + 1;
313 m->interlace = true;
315 m->v.blank2e = 0;
316 m->v.blank2s = 1;
317 m->interlace = false;
319 m->clock = mode->crtc_clock;
321 asyh->or.nhsync = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
322 asyh->or.nvsync = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
323 asyh->set.or = head->func->or != NULL;
324 asyh->set.mode = true;
334 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
342 bool check_lut = asyh->state.color_mgmt_changed ||
343 memcmp(&armh->wndw, &asyh->wndw, sizeof(asyh->wndw));
345 NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
353 if (asyh->state.active) {
354 for_each_new_connector_in_state(asyh->state.state, conn, conns, i) {
355 if (conns->crtc == crtc) {
361 if (armh->state.active) {
363 if (asyh->state.mode_changed)
364 asyc->set.scaler = true;
365 if (armh->base.depth != asyh->base.depth)
366 asyc->set.dither = true;
370 asyc->set.mask = ~0;
371 asyh->set.mask = ~0;
372 asyh->set.or = head->func->or != NULL;
375 if (asyh->state.mode_changed || asyh->state.connectors_changed)
379 asyh->olut.visible = asyh->olut.handle != 0;
382 if (asyc->set.scaler)
384 if (asyc->set.dither)
386 if (asyc->set.procamp)
390 if (head->func->core_calc) {
391 head->func->core_calc(head, asyh);
392 if (!asyh->core.visible)
393 asyh->olut.visible = false;
396 asyh->set.base = armh->base.cpp != asyh->base.cpp;
397 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
399 asyh->olut.visible = false;
400 asyh->core.visible = false;
401 asyh->curs.visible = false;
402 asyh->base.cpp = 0;
403 asyh->ovly.cpp = 0;
406 if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
407 if (asyh->core.visible) {
408 if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
409 asyh->set.core = true;
411 if (armh->core.visible) {
412 asyh->clr.core = true;
415 if (asyh->curs.visible) {
416 if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
417 asyh->set.curs = true;
419 if (armh->curs.visible) {
420 asyh->clr.curs = true;
423 if (asyh->olut.visible) {
424 if (memcmp(&armh->olut, &asyh->olut, sizeof(asyh->olut)))
425 asyh->set.olut = true;
427 if (armh->olut.visible) {
428 asyh->clr.olut = true;
431 asyh->clr.olut = armh->olut.visible;
432 asyh->clr.core = armh->core.visible;
433 asyh->clr.curs = armh->curs.visible;
434 asyh->set.olut = asyh->olut.visible;
435 asyh->set.core = asyh->core.visible;
436 asyh->set.curs = asyh->curs.visible;
443 if (asyh->clr.mask || asyh->set.mask)
444 nv50_atom(asyh->state.state)->lock_core = true;
459 __drm_atomic_helper_crtc_destroy_state(&asyh->state);
466 struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
470 __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
471 asyh->wndw = armh->wndw;
472 asyh->view = armh->view;
473 asyh->mode = armh->mode;
474 asyh->olut = armh->olut;
475 asyh->core = armh->core;
476 asyh->curs = armh->curs;
477 asyh->base = armh->base;
478 asyh->ovly = armh->ovly;
479 asyh->dither = armh->dither;
480 asyh->procamp = armh->procamp;
481 asyh->crc = armh->crc;
482 asyh->or = armh->or;
483 asyh->dp = armh->dp;
484 asyh->clr.mask = 0;
485 asyh->set.mask = 0;
486 return &asyh->state;
497 if (crtc->state)
498 nv50_head_atomic_destroy_state(crtc, crtc->state);
500 __drm_atomic_helper_crtc_reset(crtc, &asyh->state);
514 nvif_event_dtor(&head->base.vblank);
515 nvif_head_dtor(&head->base.head);
516 nv50_lut_fini(&head->olut);
557 if (drm_crtc_handle_vblank(&nv_crtc->base))
558 nv50_crc_handle_vblank(nv50_head(&nv_crtc->base));
577 return ERR_PTR(-ENOMEM);
579 head->func = disp->core->func->head;
580 head->disp = disp;
581 head->base.index = index;
583 if (disp->disp->object.oclass < GF110_DISP)
588 if (disp->disp->object.oclass < GV100_DISP) {
589 ret = nv50_base_new(drm, head->base.index, &base);
590 ret = nv50_ovly_new(drm, head->base.index, &ovly);
593 head->base.index * 2 + 0, &base);
595 head->base.index * 2 + 1, &ovly);
598 ret = nv50_curs_new(drm, head->base.index, &curs);
604 nv_crtc = &head->base;
605 crtc = &nv_crtc->base;
606 drm_crtc_init_with_planes(dev, crtc, &base->plane, &curs->plane,
607 funcs, "head-%d", head->base.index);
611 drm_crtc_enable_color_mgmt(crtc, base->func->ilut_size,
612 disp->disp->object.oclass >= GF110_DISP,
613 head->func->olut_size);
615 if (head->func->olut_set) {
616 ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut);
623 ret = nvif_head_ctor(disp->disp, head->base.base.name, head->base.index, &head->base.head);
627 ret = nvif_head_vblank_event_ctor(&head->base.head, "kmsVbl", nv50_head_vblank_handler,
628 false, &nv_crtc->vblank);