1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2015 - 2025 Beijing WangXun Technology Co., Ltd. */
3 /* Copyright (c) 1999 - 2025 Intel Corporation. */
4
5 #include <linux/ptp_classify.h>
6 #include <linux/clocksource.h>
7 #include <linux/pci.h>
8
9 #include "wx_type.h"
10 #include "wx_ptp.h"
11 #include "wx_hw.h"
12
13 #define WX_INCVAL_10GB 0xCCCCCC
14 #define WX_INCVAL_1GB 0x800000
15 #define WX_INCVAL_100 0xA00000
16 #define WX_INCVAL_10 0xC7F380
17 #define WX_INCVAL_EM 0x2000000
18 #define WX_INCVAL_AML 0xA00000
19
20 #define WX_INCVAL_SHIFT_10GB 20
21 #define WX_INCVAL_SHIFT_1GB 18
22 #define WX_INCVAL_SHIFT_100 15
23 #define WX_INCVAL_SHIFT_10 12
24 #define WX_INCVAL_SHIFT_EM 22
25 #define WX_INCVAL_SHIFT_AML 21
26
27 #define WX_OVERFLOW_PERIOD (HZ * 30)
28 #define WX_PTP_TX_TIMEOUT (HZ)
29
30 #define WX_1588_PPS_WIDTH_EM 120
31
32 #define WX_NS_PER_SEC 1000000000ULL
33
wx_ptp_timecounter_cyc2time(struct wx * wx,u64 timestamp)34 static u64 wx_ptp_timecounter_cyc2time(struct wx *wx, u64 timestamp)
35 {
36 unsigned int seq;
37 u64 ns;
38
39 do {
40 seq = read_seqbegin(&wx->hw_tc_lock);
41 ns = timecounter_cyc2time(&wx->hw_tc, timestamp);
42 } while (read_seqretry(&wx->hw_tc_lock, seq));
43
44 return ns;
45 }
46
wx_ptp_readtime(struct wx * wx,struct ptp_system_timestamp * sts)47 static u64 wx_ptp_readtime(struct wx *wx, struct ptp_system_timestamp *sts)
48 {
49 u32 timeh1, timeh2, timel;
50
51 timeh1 = rd32ptp(wx, WX_TSC_1588_SYSTIMH);
52 ptp_read_system_prets(sts);
53 timel = rd32ptp(wx, WX_TSC_1588_SYSTIML);
54 ptp_read_system_postts(sts);
55 timeh2 = rd32ptp(wx, WX_TSC_1588_SYSTIMH);
56
57 if (timeh1 != timeh2) {
58 ptp_read_system_prets(sts);
59 timel = rd32ptp(wx, WX_TSC_1588_SYSTIML);
60 ptp_read_system_prets(sts);
61 }
62 return (u64)timel | (u64)timeh2 << 32;
63 }
64
wx_ptp_adjfine(struct ptp_clock_info * ptp,long ppb)65 static int wx_ptp_adjfine(struct ptp_clock_info *ptp, long ppb)
66 {
67 struct wx *wx = container_of(ptp, struct wx, ptp_caps);
68 u64 incval, mask;
69
70 smp_mb(); /* Force any pending update before accessing. */
71 incval = READ_ONCE(wx->base_incval);
72 incval = adjust_by_scaled_ppm(incval, ppb);
73
74 mask = (wx->mac.type == wx_mac_em) ? 0x7FFFFFF : 0xFFFFFF;
75 incval &= mask;
76 if (wx->mac.type != wx_mac_em)
77 incval |= 2 << 24;
78
79 wr32ptp(wx, WX_TSC_1588_INC, incval);
80
81 return 0;
82 }
83
wx_ptp_adjtime(struct ptp_clock_info * ptp,s64 delta)84 static int wx_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
85 {
86 struct wx *wx = container_of(ptp, struct wx, ptp_caps);
87 unsigned long flags;
88
89 write_seqlock_irqsave(&wx->hw_tc_lock, flags);
90 timecounter_adjtime(&wx->hw_tc, delta);
91 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags);
92
93 if (wx->ptp_setup_sdp)
94 wx->ptp_setup_sdp(wx);
95
96 return 0;
97 }
98
wx_ptp_gettimex64(struct ptp_clock_info * ptp,struct timespec64 * ts,struct ptp_system_timestamp * sts)99 static int wx_ptp_gettimex64(struct ptp_clock_info *ptp,
100 struct timespec64 *ts,
101 struct ptp_system_timestamp *sts)
102 {
103 struct wx *wx = container_of(ptp, struct wx, ptp_caps);
104 u64 ns, stamp;
105
106 stamp = wx_ptp_readtime(wx, sts);
107 ns = wx_ptp_timecounter_cyc2time(wx, stamp);
108 *ts = ns_to_timespec64(ns);
109
110 return 0;
111 }
112
wx_ptp_settime64(struct ptp_clock_info * ptp,const struct timespec64 * ts)113 static int wx_ptp_settime64(struct ptp_clock_info *ptp,
114 const struct timespec64 *ts)
115 {
116 struct wx *wx = container_of(ptp, struct wx, ptp_caps);
117 unsigned long flags;
118 u64 ns;
119
120 ns = timespec64_to_ns(ts);
121 /* reset the timecounter */
122 write_seqlock_irqsave(&wx->hw_tc_lock, flags);
123 timecounter_init(&wx->hw_tc, &wx->hw_cc, ns);
124 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags);
125
126 if (wx->ptp_setup_sdp)
127 wx->ptp_setup_sdp(wx);
128
129 return 0;
130 }
131
132 /**
133 * wx_ptp_clear_tx_timestamp - utility function to clear Tx timestamp state
134 * @wx: the private board structure
135 *
136 * This function should be called whenever the state related to a Tx timestamp
137 * needs to be cleared. This helps ensure that all related bits are reset for
138 * the next Tx timestamp event.
139 */
wx_ptp_clear_tx_timestamp(struct wx * wx)140 static void wx_ptp_clear_tx_timestamp(struct wx *wx)
141 {
142 rd32ptp(wx, WX_TSC_1588_STMPH);
143 if (wx->ptp_tx_skb) {
144 dev_kfree_skb_any(wx->ptp_tx_skb);
145 wx->ptp_tx_skb = NULL;
146 }
147 clear_bit_unlock(WX_STATE_PTP_TX_IN_PROGRESS, wx->state);
148 }
149
150 /**
151 * wx_ptp_convert_to_hwtstamp - convert register value to hw timestamp
152 * @wx: private board structure
153 * @hwtstamp: stack timestamp structure
154 * @timestamp: unsigned 64bit system time value
155 *
156 * We need to convert the adapter's RX/TXSTMP registers into a hwtstamp value
157 * which can be used by the stack's ptp functions.
158 *
159 * The lock is used to protect consistency of the cyclecounter and the SYSTIME
160 * registers. However, it does not need to protect against the Rx or Tx
161 * timestamp registers, as there can't be a new timestamp until the old one is
162 * unlatched by reading.
163 *
164 * In addition to the timestamp in hardware, some controllers need a software
165 * overflow cyclecounter, and this function takes this into account as well.
166 **/
wx_ptp_convert_to_hwtstamp(struct wx * wx,struct skb_shared_hwtstamps * hwtstamp,u64 timestamp)167 static void wx_ptp_convert_to_hwtstamp(struct wx *wx,
168 struct skb_shared_hwtstamps *hwtstamp,
169 u64 timestamp)
170 {
171 u64 ns;
172
173 ns = wx_ptp_timecounter_cyc2time(wx, timestamp);
174 hwtstamp->hwtstamp = ns_to_ktime(ns);
175 }
176
177 /**
178 * wx_ptp_tx_hwtstamp - utility function which checks for TX time stamp
179 * @wx: the private board struct
180 *
181 * if the timestamp is valid, we convert it into the timecounter ns
182 * value, then store that result into the shhwtstamps structure which
183 * is passed up the network stack
184 */
wx_ptp_tx_hwtstamp(struct wx * wx)185 static void wx_ptp_tx_hwtstamp(struct wx *wx)
186 {
187 struct skb_shared_hwtstamps shhwtstamps;
188 struct sk_buff *skb = wx->ptp_tx_skb;
189 u64 regval = 0;
190
191 regval |= (u64)rd32ptp(wx, WX_TSC_1588_STMPL);
192 regval |= (u64)rd32ptp(wx, WX_TSC_1588_STMPH) << 32;
193
194 wx_ptp_convert_to_hwtstamp(wx, &shhwtstamps, regval);
195
196 wx->ptp_tx_skb = NULL;
197 clear_bit_unlock(WX_STATE_PTP_TX_IN_PROGRESS, wx->state);
198 skb_tstamp_tx(skb, &shhwtstamps);
199 dev_kfree_skb_any(skb);
200 wx->tx_hwtstamp_pkts++;
201 }
202
wx_ptp_tx_hwtstamp_work(struct wx * wx)203 static int wx_ptp_tx_hwtstamp_work(struct wx *wx)
204 {
205 u32 tsynctxctl;
206
207 /* we have to have a valid skb to poll for a timestamp */
208 if (!wx->ptp_tx_skb) {
209 wx_ptp_clear_tx_timestamp(wx);
210 return 0;
211 }
212
213 /* stop polling once we have a valid timestamp */
214 tsynctxctl = rd32ptp(wx, WX_TSC_1588_CTL);
215 if (tsynctxctl & WX_TSC_1588_CTL_VALID) {
216 wx_ptp_tx_hwtstamp(wx);
217 return 0;
218 }
219
220 return -1;
221 }
222
223 /**
224 * wx_ptp_overflow_check - watchdog task to detect SYSTIME overflow
225 * @wx: pointer to wx struct
226 *
227 * this watchdog task periodically reads the timecounter
228 * in order to prevent missing when the system time registers wrap
229 * around. This needs to be run approximately twice a minute for the fastest
230 * overflowing hardware. We run it for all hardware since it shouldn't have a
231 * large impact.
232 */
wx_ptp_overflow_check(struct wx * wx)233 static void wx_ptp_overflow_check(struct wx *wx)
234 {
235 bool timeout = time_is_before_jiffies(wx->last_overflow_check +
236 WX_OVERFLOW_PERIOD);
237 unsigned long flags;
238
239 if (timeout) {
240 /* Update the timecounter */
241 write_seqlock_irqsave(&wx->hw_tc_lock, flags);
242 timecounter_read(&wx->hw_tc);
243 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags);
244
245 wx->last_overflow_check = jiffies;
246 }
247 }
248
249 /**
250 * wx_ptp_rx_hang - detect error case when Rx timestamp registers latched
251 * @wx: pointer to wx struct
252 *
253 * this watchdog task is scheduled to detect error case where hardware has
254 * dropped an Rx packet that was timestamped when the ring is full. The
255 * particular error is rare but leaves the device in a state unable to
256 * timestamp any future packets.
257 */
wx_ptp_rx_hang(struct wx * wx)258 static void wx_ptp_rx_hang(struct wx *wx)
259 {
260 struct wx_ring *rx_ring;
261 unsigned long rx_event;
262 u32 tsyncrxctl;
263 int n;
264
265 tsyncrxctl = rd32(wx, WX_PSR_1588_CTL);
266
267 /* if we don't have a valid timestamp in the registers, just update the
268 * timeout counter and exit
269 */
270 if (!(tsyncrxctl & WX_PSR_1588_CTL_VALID)) {
271 wx->last_rx_ptp_check = jiffies;
272 return;
273 }
274
275 /* determine the most recent watchdog or rx_timestamp event */
276 rx_event = wx->last_rx_ptp_check;
277 for (n = 0; n < wx->num_rx_queues; n++) {
278 rx_ring = wx->rx_ring[n];
279 if (time_after(rx_ring->last_rx_timestamp, rx_event))
280 rx_event = rx_ring->last_rx_timestamp;
281 }
282
283 /* only need to read the high RXSTMP register to clear the lock */
284 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
285 rd32(wx, WX_PSR_1588_STMPH);
286 wx->last_rx_ptp_check = jiffies;
287
288 wx->rx_hwtstamp_cleared++;
289 dev_warn(&wx->pdev->dev, "clearing RX Timestamp hang");
290 }
291 }
292
293 /**
294 * wx_ptp_tx_hang - detect error case where Tx timestamp never finishes
295 * @wx: private network wx structure
296 */
wx_ptp_tx_hang(struct wx * wx)297 static void wx_ptp_tx_hang(struct wx *wx)
298 {
299 bool timeout = time_is_before_jiffies(wx->ptp_tx_start +
300 WX_PTP_TX_TIMEOUT);
301
302 if (!wx->ptp_tx_skb)
303 return;
304
305 if (!test_bit(WX_STATE_PTP_TX_IN_PROGRESS, wx->state))
306 return;
307
308 /* If we haven't received a timestamp within the timeout, it is
309 * reasonable to assume that it will never occur, so we can unlock the
310 * timestamp bit when this occurs.
311 */
312 if (timeout) {
313 wx_ptp_clear_tx_timestamp(wx);
314 wx->tx_hwtstamp_timeouts++;
315 dev_warn(&wx->pdev->dev, "clearing Tx timestamp hang\n");
316 }
317 }
318
wx_ptp_do_aux_work(struct ptp_clock_info * ptp)319 static long wx_ptp_do_aux_work(struct ptp_clock_info *ptp)
320 {
321 struct wx *wx = container_of(ptp, struct wx, ptp_caps);
322 int ts_done;
323
324 if (!test_bit(WX_STATE_PTP_RUNNING, wx->state))
325 return HZ;
326
327 ts_done = wx_ptp_tx_hwtstamp_work(wx);
328
329 wx_ptp_overflow_check(wx);
330 if (unlikely(test_bit(WX_FLAG_RX_HWTSTAMP_IN_REGISTER,
331 wx->flags)))
332 wx_ptp_rx_hang(wx);
333 wx_ptp_tx_hang(wx);
334
335 return ts_done ? 1 : HZ;
336 }
337
wx_ptp_trigger_calc(struct wx * wx)338 static u64 wx_ptp_trigger_calc(struct wx *wx)
339 {
340 struct cyclecounter *cc = &wx->hw_cc;
341 unsigned long flags;
342 u64 ns = 0;
343 u32 rem;
344
345 /* Read the current clock time, and save the cycle counter value */
346 write_seqlock_irqsave(&wx->hw_tc_lock, flags);
347 ns = timecounter_read(&wx->hw_tc);
348 wx->pps_edge_start = wx->hw_tc.cycle_last;
349 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags);
350 wx->pps_edge_end = wx->pps_edge_start;
351
352 /* Figure out how far past the next second we are */
353 div_u64_rem(ns, WX_NS_PER_SEC, &rem);
354
355 /* Figure out how many nanoseconds to add to round the clock edge up
356 * to the next full second
357 */
358 rem = (WX_NS_PER_SEC - rem);
359
360 /* Adjust the clock edge to align with the next full second. */
361 wx->pps_edge_start += div_u64(((u64)rem << cc->shift), cc->mult);
362 wx->pps_edge_end += div_u64(((u64)(rem + wx->pps_width) <<
363 cc->shift), cc->mult);
364
365 return (ns + rem);
366 }
367
wx_ptp_setup_sdp(struct wx * wx)368 static int wx_ptp_setup_sdp(struct wx *wx)
369 {
370 struct cyclecounter *cc = &wx->hw_cc;
371 u32 tsauxc;
372 u64 nsec;
373
374 if (wx->pps_width >= WX_NS_PER_SEC) {
375 wx_err(wx, "PTP pps width cannot be longer than 1s!\n");
376 return -EINVAL;
377 }
378
379 /* disable the pin first */
380 wr32ptp(wx, WX_TSC_1588_AUX_CTL, 0);
381 WX_WRITE_FLUSH(wx);
382
383 if (!test_bit(WX_FLAG_PTP_PPS_ENABLED, wx->flags)) {
384 if (wx->pps_enabled) {
385 wx->pps_enabled = false;
386 wx_set_pps(wx, false, 0, 0);
387 }
388 return 0;
389 }
390
391 wx->pps_enabled = true;
392 nsec = wx_ptp_trigger_calc(wx);
393 wx_set_pps(wx, wx->pps_enabled, nsec, wx->pps_edge_start);
394
395 tsauxc = WX_TSC_1588_AUX_CTL_PLSG | WX_TSC_1588_AUX_CTL_EN_TT0 |
396 WX_TSC_1588_AUX_CTL_EN_TT1 | WX_TSC_1588_AUX_CTL_EN_TS0;
397 wr32ptp(wx, WX_TSC_1588_TRGT_L(0), (u32)wx->pps_edge_start);
398 wr32ptp(wx, WX_TSC_1588_TRGT_H(0), (u32)(wx->pps_edge_start >> 32));
399 wr32ptp(wx, WX_TSC_1588_TRGT_L(1), (u32)wx->pps_edge_end);
400 wr32ptp(wx, WX_TSC_1588_TRGT_H(1), (u32)(wx->pps_edge_end >> 32));
401 wr32ptp(wx, WX_TSC_1588_SDP(0),
402 WX_TSC_1588_SDP_FUN_SEL_TT0 | WX_TSC_1588_SDP_OUT_LEVEL_H);
403 wr32ptp(wx, WX_TSC_1588_SDP(1), WX_TSC_1588_SDP_FUN_SEL_TS0);
404 wr32ptp(wx, WX_TSC_1588_AUX_CTL, tsauxc);
405 wr32ptp(wx, WX_TSC_1588_INT_EN, WX_TSC_1588_INT_EN_TT1);
406 WX_WRITE_FLUSH(wx);
407
408 /* Adjust the clock edge to align with the next full second. */
409 wx->sec_to_cc = div_u64(((u64)WX_NS_PER_SEC << cc->shift), cc->mult);
410
411 return 0;
412 }
413
wx_ptp_feature_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)414 static int wx_ptp_feature_enable(struct ptp_clock_info *ptp,
415 struct ptp_clock_request *rq, int on)
416 {
417 struct wx *wx = container_of(ptp, struct wx, ptp_caps);
418
419 /**
420 * When PPS is enabled, unmask the interrupt for the ClockOut
421 * feature, so that the interrupt handler can send the PPS
422 * event when the clock SDP triggers. Clear mask when PPS is
423 * disabled
424 */
425 if (rq->type != PTP_CLK_REQ_PEROUT || !wx->ptp_setup_sdp)
426 return -EOPNOTSUPP;
427
428 /* Reject requests with unsupported flags */
429 if (rq->perout.flags & ~(PTP_PEROUT_DUTY_CYCLE |
430 PTP_PEROUT_PHASE))
431 return -EOPNOTSUPP;
432
433 if (rq->perout.phase.sec || rq->perout.phase.nsec) {
434 wx_err(wx, "Absolute start time not supported.\n");
435 return -EINVAL;
436 }
437
438 if (rq->perout.period.sec != 1 || rq->perout.period.nsec) {
439 wx_err(wx, "Only 1pps is supported.\n");
440 return -EINVAL;
441 }
442
443 if (rq->perout.flags & PTP_PEROUT_DUTY_CYCLE) {
444 struct timespec64 ts_on;
445
446 ts_on.tv_sec = rq->perout.on.sec;
447 ts_on.tv_nsec = rq->perout.on.nsec;
448 wx->pps_width = timespec64_to_ns(&ts_on);
449 } else {
450 wx->pps_width = 120000000;
451 }
452
453 if (on)
454 set_bit(WX_FLAG_PTP_PPS_ENABLED, wx->flags);
455 else
456 clear_bit(WX_FLAG_PTP_PPS_ENABLED, wx->flags);
457
458 return wx->ptp_setup_sdp(wx);
459 }
460
wx_ptp_check_pps_event(struct wx * wx)461 void wx_ptp_check_pps_event(struct wx *wx)
462 {
463 u32 tsauxc, int_status;
464
465 /* this check is necessary in case the interrupt was enabled via some
466 * alternative means (ex. debug_fs). Better to check here than
467 * everywhere that calls this function.
468 */
469 if (!wx->ptp_clock)
470 return;
471
472 int_status = rd32ptp(wx, WX_TSC_1588_INT_ST);
473 if (int_status & WX_TSC_1588_INT_ST_TT1) {
474 /* disable the pin first */
475 wr32ptp(wx, WX_TSC_1588_AUX_CTL, 0);
476 WX_WRITE_FLUSH(wx);
477
478 wx_ptp_trigger_calc(wx);
479
480 tsauxc = WX_TSC_1588_AUX_CTL_PLSG | WX_TSC_1588_AUX_CTL_EN_TT0 |
481 WX_TSC_1588_AUX_CTL_EN_TT1 | WX_TSC_1588_AUX_CTL_EN_TS0;
482 wr32ptp(wx, WX_TSC_1588_TRGT_L(0), (u32)wx->pps_edge_start);
483 wr32ptp(wx, WX_TSC_1588_TRGT_H(0), (u32)(wx->pps_edge_start >> 32));
484 wr32ptp(wx, WX_TSC_1588_TRGT_L(1), (u32)wx->pps_edge_end);
485 wr32ptp(wx, WX_TSC_1588_TRGT_H(1), (u32)(wx->pps_edge_end >> 32));
486 wr32ptp(wx, WX_TSC_1588_AUX_CTL, tsauxc);
487 WX_WRITE_FLUSH(wx);
488 }
489 }
490 EXPORT_SYMBOL(wx_ptp_check_pps_event);
491
wx_ptp_create_clock(struct wx * wx)492 static long wx_ptp_create_clock(struct wx *wx)
493 {
494 struct net_device *netdev = wx->netdev;
495 long err;
496
497 /* do nothing if we already have a clock device */
498 if (!IS_ERR_OR_NULL(wx->ptp_clock))
499 return 0;
500
501 snprintf(wx->ptp_caps.name, sizeof(wx->ptp_caps.name),
502 "%s", netdev->name);
503 wx->ptp_caps.owner = THIS_MODULE;
504 wx->ptp_caps.n_alarm = 0;
505 wx->ptp_caps.n_ext_ts = 0;
506 wx->ptp_caps.pps = 0;
507 wx->ptp_caps.adjfine = wx_ptp_adjfine;
508 wx->ptp_caps.adjtime = wx_ptp_adjtime;
509 wx->ptp_caps.gettimex64 = wx_ptp_gettimex64;
510 wx->ptp_caps.settime64 = wx_ptp_settime64;
511 wx->ptp_caps.do_aux_work = wx_ptp_do_aux_work;
512 switch (wx->mac.type) {
513 case wx_mac_aml:
514 case wx_mac_aml40:
515 wx->ptp_caps.max_adj = 250000000;
516 wx->ptp_caps.n_per_out = 1;
517 wx->ptp_setup_sdp = wx_ptp_setup_sdp;
518 wx->ptp_caps.enable = wx_ptp_feature_enable;
519 break;
520 case wx_mac_sp:
521 wx->ptp_caps.max_adj = 250000000;
522 wx->ptp_caps.n_per_out = 0;
523 wx->ptp_setup_sdp = NULL;
524 break;
525 case wx_mac_em:
526 wx->ptp_caps.max_adj = 500000000;
527 wx->ptp_caps.n_per_out = 1;
528 wx->ptp_setup_sdp = wx_ptp_setup_sdp;
529 wx->ptp_caps.enable = wx_ptp_feature_enable;
530 break;
531 default:
532 return -EOPNOTSUPP;
533 }
534
535 wx->ptp_clock = ptp_clock_register(&wx->ptp_caps, &wx->pdev->dev);
536 if (IS_ERR(wx->ptp_clock)) {
537 err = PTR_ERR(wx->ptp_clock);
538 wx->ptp_clock = NULL;
539 wx_err(wx, "ptp clock register failed\n");
540 return err;
541 } else if (wx->ptp_clock) {
542 dev_info(&wx->pdev->dev, "registered PHC device on %s\n",
543 netdev->name);
544 }
545
546 /* Set the default timestamp mode to disabled here. We do this in
547 * create_clock instead of initialization, because we don't want to
548 * override the previous settings during a suspend/resume cycle.
549 */
550 wx->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
551 wx->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
552
553 return 0;
554 }
555
wx_ptp_set_timestamp_mode(struct wx * wx,struct kernel_hwtstamp_config * config)556 static int wx_ptp_set_timestamp_mode(struct wx *wx,
557 struct kernel_hwtstamp_config *config)
558 {
559 u32 tsync_tx_ctl = WX_TSC_1588_CTL_ENABLED;
560 u32 tsync_rx_ctl = WX_PSR_1588_CTL_ENABLED;
561 u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
562 bool rx_tstamp = false;
563 bool is_l2 = false;
564 u32 regval;
565
566 switch (config->tx_type) {
567 case HWTSTAMP_TX_OFF:
568 tsync_tx_ctl = 0;
569 break;
570 case HWTSTAMP_TX_ON:
571 break;
572 default:
573 return -ERANGE;
574 }
575
576 switch (config->rx_filter) {
577 case HWTSTAMP_FILTER_NONE:
578 tsync_rx_ctl = 0;
579 tsync_rx_mtrl = 0;
580 break;
581 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
582 tsync_rx_ctl |= WX_PSR_1588_CTL_TYPE_L4_V1;
583 tsync_rx_mtrl |= WX_PSR_1588_MSG_V1_SYNC;
584 rx_tstamp = true;
585 break;
586 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
587 tsync_rx_ctl |= WX_PSR_1588_CTL_TYPE_L4_V1;
588 tsync_rx_mtrl |= WX_PSR_1588_MSG_V1_DELAY_REQ;
589 rx_tstamp = true;
590 break;
591 case HWTSTAMP_FILTER_PTP_V2_EVENT:
592 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
593 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
594 case HWTSTAMP_FILTER_PTP_V2_SYNC:
595 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
596 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
597 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
598 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
599 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
600 tsync_rx_ctl |= WX_PSR_1588_CTL_TYPE_EVENT_V2;
601 is_l2 = true;
602 rx_tstamp = true;
603 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
604 break;
605 default:
606 /* register PSR_1588_MSG must be set in order to do V1 packets,
607 * therefore it is not possible to time stamp both V1 Sync and
608 * Delay_Req messages unless hardware supports timestamping all
609 * packets => return error
610 */
611 config->rx_filter = HWTSTAMP_FILTER_NONE;
612 return -ERANGE;
613 }
614
615 /* define ethertype filter for timestamping L2 packets */
616 if (is_l2)
617 wr32(wx, WX_PSR_ETYPE_SWC(WX_PSR_ETYPE_SWC_FILTER_1588),
618 (WX_PSR_ETYPE_SWC_FILTER_EN | /* enable filter */
619 WX_PSR_ETYPE_SWC_1588 | /* enable timestamping */
620 ETH_P_1588)); /* 1588 eth protocol type */
621 else
622 wr32(wx, WX_PSR_ETYPE_SWC(WX_PSR_ETYPE_SWC_FILTER_1588), 0);
623
624 /* enable/disable TX */
625 regval = rd32ptp(wx, WX_TSC_1588_CTL);
626 regval &= ~WX_TSC_1588_CTL_ENABLED;
627 regval |= tsync_tx_ctl;
628 wr32ptp(wx, WX_TSC_1588_CTL, regval);
629
630 /* enable/disable RX */
631 regval = rd32(wx, WX_PSR_1588_CTL);
632 regval &= ~(WX_PSR_1588_CTL_ENABLED | WX_PSR_1588_CTL_TYPE_MASK);
633 regval |= tsync_rx_ctl;
634 wr32(wx, WX_PSR_1588_CTL, regval);
635
636 /* define which PTP packets are time stamped */
637 wr32(wx, WX_PSR_1588_MSG, tsync_rx_mtrl);
638
639 WX_WRITE_FLUSH(wx);
640
641 /* configure adapter flags only when HW is actually configured */
642 assign_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, wx->flags, rx_tstamp);
643 assign_bit(WX_FLAG_RX_HWTSTAMP_IN_REGISTER, wx->flags, rx_tstamp);
644
645 /* clear TX/RX timestamp state, just to be sure */
646 wx_ptp_clear_tx_timestamp(wx);
647 rd32(wx, WX_PSR_1588_STMPH);
648
649 return 0;
650 }
651
wx_ptp_read(struct cyclecounter * hw_cc)652 static u64 wx_ptp_read(struct cyclecounter *hw_cc)
653 {
654 struct wx *wx = container_of(hw_cc, struct wx, hw_cc);
655
656 return wx_ptp_readtime(wx, NULL);
657 }
658
wx_ptp_link_speed_adjust(struct wx * wx,u32 * shift,u32 * incval)659 static void wx_ptp_link_speed_adjust(struct wx *wx, u32 *shift, u32 *incval)
660 {
661 switch (wx->mac.type) {
662 case wx_mac_aml:
663 case wx_mac_aml40:
664 *shift = WX_INCVAL_SHIFT_AML;
665 *incval = WX_INCVAL_AML;
666 return;
667 case wx_mac_em:
668 *shift = WX_INCVAL_SHIFT_EM;
669 *incval = WX_INCVAL_EM;
670 return;
671 default:
672 break;
673 }
674
675 switch (wx->speed) {
676 case SPEED_10:
677 *shift = WX_INCVAL_SHIFT_10;
678 *incval = WX_INCVAL_10;
679 break;
680 case SPEED_100:
681 *shift = WX_INCVAL_SHIFT_100;
682 *incval = WX_INCVAL_100;
683 break;
684 case SPEED_1000:
685 *shift = WX_INCVAL_SHIFT_1GB;
686 *incval = WX_INCVAL_1GB;
687 break;
688 case SPEED_10000:
689 default:
690 *shift = WX_INCVAL_SHIFT_10GB;
691 *incval = WX_INCVAL_10GB;
692 break;
693 }
694 }
695
696 /**
697 * wx_ptp_reset_cyclecounter - create the cycle counter from hw
698 * @wx: pointer to the wx structure
699 *
700 * This function should be called to set the proper values for the TSC_1588_INC
701 * register and tell the cyclecounter structure what the tick rate of SYSTIME
702 * is. It does not directly modify SYSTIME registers or the timecounter
703 * structure. It should be called whenever a new TSC_1588_INC value is
704 * necessary, such as during initialization or when the link speed changes.
705 */
wx_ptp_reset_cyclecounter(struct wx * wx)706 void wx_ptp_reset_cyclecounter(struct wx *wx)
707 {
708 u32 incval = 0, mask = 0;
709 struct cyclecounter cc;
710 unsigned long flags;
711
712 /* For some of the boards below this mask is technically incorrect.
713 * The timestamp mask overflows at approximately 61bits. However the
714 * particular hardware does not overflow on an even bitmask value.
715 * Instead, it overflows due to conversion of upper 32bits billions of
716 * cycles. Timecounters are not really intended for this purpose so
717 * they do not properly function if the overflow point isn't 2^N-1.
718 * However, the actual SYSTIME values in question take ~138 years to
719 * overflow. In practice this means they won't actually overflow. A
720 * proper fix to this problem would require modification of the
721 * timecounter delta calculations.
722 */
723 cc.mask = CLOCKSOURCE_MASK(64);
724 cc.mult = 1;
725 cc.shift = 0;
726
727 cc.read = wx_ptp_read;
728 wx_ptp_link_speed_adjust(wx, &cc.shift, &incval);
729
730 /* update the base incval used to calculate frequency adjustment */
731 WRITE_ONCE(wx->base_incval, incval);
732
733 mask = (wx->mac.type == wx_mac_em) ? 0x7FFFFFF : 0xFFFFFF;
734 incval &= mask;
735 if (wx->mac.type != wx_mac_em)
736 incval |= 2 << 24;
737 wr32ptp(wx, WX_TSC_1588_INC, incval);
738
739 smp_mb(); /* Force the above update. */
740
741 /* need lock to prevent incorrect read while modifying cyclecounter */
742 write_seqlock_irqsave(&wx->hw_tc_lock, flags);
743 memcpy(&wx->hw_cc, &cc, sizeof(wx->hw_cc));
744 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags);
745 }
746 EXPORT_SYMBOL(wx_ptp_reset_cyclecounter);
747
wx_ptp_reset(struct wx * wx)748 void wx_ptp_reset(struct wx *wx)
749 {
750 unsigned long flags;
751
752 /* reset the hardware timestamping mode */
753 wx_ptp_set_timestamp_mode(wx, &wx->tstamp_config);
754 wx_ptp_reset_cyclecounter(wx);
755
756 wr32ptp(wx, WX_TSC_1588_SYSTIML, 0);
757 wr32ptp(wx, WX_TSC_1588_SYSTIMH, 0);
758 WX_WRITE_FLUSH(wx);
759
760 write_seqlock_irqsave(&wx->hw_tc_lock, flags);
761 timecounter_init(&wx->hw_tc, &wx->hw_cc,
762 ktime_to_ns(ktime_get_real()));
763 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags);
764
765 wx->last_overflow_check = jiffies;
766 ptp_schedule_worker(wx->ptp_clock, HZ);
767
768 /* Now that the shift has been calculated and the systime
769 * registers reset, (re-)enable the Clock out feature
770 */
771 if (wx->ptp_setup_sdp)
772 wx->ptp_setup_sdp(wx);
773 }
774 EXPORT_SYMBOL(wx_ptp_reset);
775
wx_ptp_init(struct wx * wx)776 void wx_ptp_init(struct wx *wx)
777 {
778 /* Initialize the seqlock_t first, since the user might call the clock
779 * functions any time after we've initialized the ptp clock device.
780 */
781 seqlock_init(&wx->hw_tc_lock);
782
783 /* obtain a ptp clock device, or re-use an existing device */
784 if (wx_ptp_create_clock(wx))
785 return;
786
787 wx->tx_hwtstamp_pkts = 0;
788 wx->tx_hwtstamp_timeouts = 0;
789 wx->tx_hwtstamp_skipped = 0;
790 wx->tx_hwtstamp_errors = 0;
791 wx->rx_hwtstamp_cleared = 0;
792 /* reset the ptp related hardware bits */
793 wx_ptp_reset(wx);
794
795 /* enter the WX_STATE_PTP_RUNNING state */
796 set_bit(WX_STATE_PTP_RUNNING, wx->state);
797 }
798 EXPORT_SYMBOL(wx_ptp_init);
799
800 /**
801 * wx_ptp_suspend - stop ptp work items
802 * @wx: pointer to wx struct
803 *
804 * This function suspends ptp activity, and prevents more work from being
805 * generated, but does not destroy the clock device.
806 */
wx_ptp_suspend(struct wx * wx)807 void wx_ptp_suspend(struct wx *wx)
808 {
809 /* leave the WX_STATE_PTP_RUNNING STATE */
810 if (!test_and_clear_bit(WX_STATE_PTP_RUNNING, wx->state))
811 return;
812
813 clear_bit(WX_FLAG_PTP_PPS_ENABLED, wx->flags);
814 if (wx->ptp_setup_sdp)
815 wx->ptp_setup_sdp(wx);
816
817 wx_ptp_clear_tx_timestamp(wx);
818 }
819 EXPORT_SYMBOL(wx_ptp_suspend);
820
821 /**
822 * wx_ptp_stop - destroy the ptp_clock device
823 * @wx: pointer to wx struct
824 *
825 * Completely destroy the ptp_clock device, and disable all PTP related
826 * features. Intended to be run when the device is being closed.
827 */
wx_ptp_stop(struct wx * wx)828 void wx_ptp_stop(struct wx *wx)
829 {
830 /* first, suspend ptp activity */
831 wx_ptp_suspend(wx);
832
833 /* now destroy the ptp clock device */
834 if (wx->ptp_clock) {
835 ptp_clock_unregister(wx->ptp_clock);
836 wx->ptp_clock = NULL;
837 dev_info(&wx->pdev->dev, "removed PHC on %s\n", wx->netdev->name);
838 }
839 }
840 EXPORT_SYMBOL(wx_ptp_stop);
841
wx_ptp_quiesce(struct wx * wx)842 void wx_ptp_quiesce(struct wx *wx)
843 {
844 if (!test_and_clear_bit(WX_STATE_PTP_RUNNING, wx->state))
845 return;
846
847 clear_bit(WX_FLAG_PTP_PPS_ENABLED, wx->flags);
848
849 if (wx->ptp_clock)
850 ptp_cancel_worker_sync(wx->ptp_clock);
851
852 if (wx->ptp_tx_skb) {
853 dev_kfree_skb_any(wx->ptp_tx_skb);
854 wx->ptp_tx_skb = NULL;
855 }
856 clear_bit_unlock(WX_STATE_PTP_TX_IN_PROGRESS, wx->state);
857
858 if (wx->ptp_clock) {
859 ptp_clock_unregister(wx->ptp_clock);
860 wx->ptp_clock = NULL;
861 dev_info(&wx->pdev->dev, "removed PHC on %s\n", wx->netdev->name);
862 }
863 }
864 EXPORT_SYMBOL(wx_ptp_quiesce);
865
866 /**
867 * wx_ptp_rx_hwtstamp - utility function which checks for RX time stamp
868 * @wx: pointer to wx struct
869 * @skb: particular skb to send timestamp with
870 *
871 * if the timestamp is valid, we convert it into the timecounter ns
872 * value, then store that result into the shhwtstamps structure which
873 * is passed up the network stack
874 */
wx_ptp_rx_hwtstamp(struct wx * wx,struct sk_buff * skb)875 void wx_ptp_rx_hwtstamp(struct wx *wx, struct sk_buff *skb)
876 {
877 u64 regval = 0;
878 u32 tsyncrxctl;
879
880 /* Read the tsyncrxctl register afterwards in order to prevent taking an
881 * I/O hit on every packet.
882 */
883 tsyncrxctl = rd32(wx, WX_PSR_1588_CTL);
884 if (!(tsyncrxctl & WX_PSR_1588_CTL_VALID))
885 return;
886
887 regval |= (u64)rd32(wx, WX_PSR_1588_STMPL);
888 regval |= (u64)rd32(wx, WX_PSR_1588_STMPH) << 32;
889
890 wx_ptp_convert_to_hwtstamp(wx, skb_hwtstamps(skb), regval);
891 }
892
wx_hwtstamp_get(struct net_device * dev,struct kernel_hwtstamp_config * cfg)893 int wx_hwtstamp_get(struct net_device *dev,
894 struct kernel_hwtstamp_config *cfg)
895 {
896 struct wx *wx = netdev_priv(dev);
897
898 if (!netif_running(dev))
899 return -EINVAL;
900
901 *cfg = wx->tstamp_config;
902
903 return 0;
904 }
905 EXPORT_SYMBOL(wx_hwtstamp_get);
906
wx_hwtstamp_set(struct net_device * dev,struct kernel_hwtstamp_config * cfg,struct netlink_ext_ack * extack)907 int wx_hwtstamp_set(struct net_device *dev,
908 struct kernel_hwtstamp_config *cfg,
909 struct netlink_ext_ack *extack)
910 {
911 struct wx *wx = netdev_priv(dev);
912 int err;
913
914 if (!netif_running(dev))
915 return -EINVAL;
916
917 err = wx_ptp_set_timestamp_mode(wx, cfg);
918 if (err)
919 return err;
920
921 /* save these settings for future reference */
922 memcpy(&wx->tstamp_config, cfg, sizeof(wx->tstamp_config));
923
924 return 0;
925 }
926 EXPORT_SYMBOL(wx_hwtstamp_set);
927