1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 4 #include <linux/component.h> 5 #include <linux/cleanup.h> 6 #include <linux/delay.h> 7 #include <linux/device.h> 8 #include <linux/gpio/consumer.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <sound/jack.h> 18 #include <sound/pcm_params.h> 19 #include <sound/pcm.h> 20 #include <sound/soc-dapm.h> 21 #include <sound/soc.h> 22 #include <sound/tlv.h> 23 24 #include "wcd-clsh-v2.h" 25 #include "wcd-common.h" 26 #include "wcd-mbhc-v2.h" 27 #include "wcd937x.h" 28 29 #define CHIPID_WCD9370 0x0 30 #define CHIPID_WCD9375 0x5 31 32 /* Z value defined in milliohm */ 33 #define WCD937X_ZDET_VAL_32 (32000) 34 #define WCD937X_ZDET_VAL_400 (400000) 35 #define WCD937X_ZDET_VAL_1200 (1200000) 36 #define WCD937X_ZDET_VAL_100K (100000000) 37 /* Z floating defined in ohms */ 38 #define WCD937X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 39 #define WCD937X_ZDET_NUM_MEASUREMENTS (900) 40 #define WCD937X_MBHC_GET_C1(c) (((c) & 0xC000) >> 14) 41 #define WCD937X_MBHC_GET_X1(x) ((x) & 0x3FFF) 42 /* Z value compared in milliOhm */ 43 #define WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z) (((z) > 400000) || ((z) < 32000)) 44 #define WCD937X_MBHC_ZDET_CONST (86 * 16384) 45 #define WCD937X_MBHC_MOISTURE_RREF R_24_KOHM 46 #define WCD_MBHC_HS_V_MAX 1600 47 #define EAR_RX_PATH_AUX 1 48 #define WCD937X_MBHC_MAX_BUTTONS 8 49 50 #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 51 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 52 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ 53 SNDRV_PCM_RATE_384000) 54 55 /* Fractional Rates */ 56 #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 57 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) 58 59 #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |\ 60 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 61 62 enum { 63 ALLOW_BUCK_DISABLE, 64 HPH_COMP_DELAY, 65 HPH_PA_DELAY, 66 AMIC2_BCS_ENABLE, 67 }; 68 69 enum { 70 AIF1_PB = 0, 71 AIF1_CAP, 72 NUM_CODEC_DAIS, 73 }; 74 75 struct wcd937x_priv { 76 struct sdw_slave *tx_sdw_dev; 77 struct wcd937x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 78 struct device *txdev; 79 struct device *rxdev; 80 struct device_node *rxnode; 81 struct device_node *txnode; 82 struct regmap *regmap; 83 /* micb setup lock */ 84 struct mutex micb_lock; 85 /* mbhc module */ 86 struct wcd_mbhc *wcd_mbhc; 87 struct wcd_mbhc_config mbhc_cfg; 88 struct wcd_mbhc_intr intr_ids; 89 struct wcd_clsh_ctrl *clsh_info; 90 struct wcd_common common; 91 struct irq_domain *virq; 92 struct regmap_irq_chip_data *irq_chip; 93 struct snd_soc_jack *jack; 94 unsigned long status_mask; 95 s32 micb_ref[WCD937X_MAX_MICBIAS]; 96 s32 pullup_ref[WCD937X_MAX_MICBIAS]; 97 u32 hph_mode; 98 int ear_rx_path; 99 int hphr_pdm_wd_int; 100 int hphl_pdm_wd_int; 101 int aux_pdm_wd_int; 102 bool comp1_enable; 103 bool comp2_enable; 104 105 struct gpio_desc *us_euro_gpio; 106 struct gpio_desc *reset_gpio; 107 108 atomic_t rx_clk_cnt; 109 atomic_t ana_clk_count; 110 }; 111 112 static const char * const wcd937x_supplies[] = { 113 "vdd-rxtx", "vdd-px", "vdd-mic-bias", "vdd-buck", 114 }; 115 116 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 117 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 118 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 119 120 struct wcd937x_mbhc_zdet_param { 121 u16 ldo_ctl; 122 u16 noff; 123 u16 nshift; 124 u16 btn5; 125 u16 btn6; 126 u16 btn7; 127 }; 128 129 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 130 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD937X_ANA_MBHC_MECH, 0x80), 131 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD937X_ANA_MBHC_MECH, 0x40), 132 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD937X_ANA_MBHC_MECH, 0x20), 133 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 134 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD937X_ANA_MBHC_ELECT, 0x08), 135 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 136 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD937X_ANA_MBHC_MECH, 0x04), 137 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x10), 138 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x08), 139 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD937X_ANA_MBHC_MECH, 0x01), 140 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD937X_ANA_MBHC_ELECT, 0x06), 141 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD937X_ANA_MBHC_ELECT, 0x80), 142 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 143 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD937X_MBHC_NEW_CTL_1, 0x03), 144 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD937X_MBHC_NEW_CTL_2, 0x03), 145 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x08), 146 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD937X_ANA_MBHC_RESULT_3, 0x10), 147 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x20), 148 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x80), 149 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x40), 150 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD937X_HPH_OCP_CTL, 0x10), 151 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x07), 152 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD937X_ANA_MBHC_ELECT, 0x70), 153 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0xFF), 154 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD937X_ANA_MICB2, 0xC0), 155 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD937X_HPH_CNP_WG_TIME, 0xFF), 156 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD937X_ANA_HPH, 0x40), 157 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD937X_ANA_HPH, 0x80), 158 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD937X_ANA_HPH, 0xC0), 159 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD937X_ANA_MBHC_RESULT_3, 0x10), 160 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD937X_MBHC_CTL_BCS, 0x02), 161 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x01), 162 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD937X_MBHC_NEW_CTL_2, 0x70), 163 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x20), 164 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD937X_HPH_PA_CTL2, 0x40), 165 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD937X_HPH_PA_CTL2, 0x10), 166 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD937X_HPH_L_TEST, 0x01), 167 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD937X_HPH_R_TEST, 0x01), 168 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x80), 169 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x20), 170 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD937X_MBHC_NEW_CTL_1, 0x08), 171 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD937X_MBHC_NEW_FSM_STATUS, 0x40), 172 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD937X_MBHC_NEW_FSM_STATUS, 0x80), 173 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD937X_MBHC_NEW_ADC_RESULT, 0xFF), 174 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD937X_ANA_MICB2, 0x3F), 175 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD937X_MBHC_NEW_CTL_1, 0x10), 176 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD937X_MBHC_NEW_CTL_1, 0x04), 177 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD937X_ANA_MBHC_ZDET, 0x02), 178 }; 179 180 static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = { 181 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, BIT(0)), 182 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, BIT(1)), 183 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, BIT(2)), 184 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, BIT(3)), 185 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, BIT(4)), 186 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, BIT(5)), 187 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, BIT(6)), 188 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, BIT(7)), 189 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, BIT(0)), 190 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, BIT(1)), 191 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, BIT(2)), 192 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, BIT(3)), 193 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, BIT(4)), 194 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, BIT(5)), 195 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, BIT(6)), 196 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, BIT(7)), 197 REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, BIT(0)), 198 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, BIT(1)), 199 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, BIT(2)), 200 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, BIT(3)), 201 }; 202 203 static int wcd937x_handle_post_irq(void *data) 204 { 205 struct wcd937x_priv *wcd937x; 206 207 if (data) 208 wcd937x = (struct wcd937x_priv *)data; 209 else 210 return IRQ_HANDLED; 211 212 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_0, 0); 213 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_1, 0); 214 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_2, 0); 215 216 return IRQ_HANDLED; 217 } 218 219 static const u32 wcd937x_config_regs[] = { 220 WCD937X_DIGITAL_INTR_LEVEL_0, 221 }; 222 223 static const struct regmap_irq_chip wcd937x_regmap_irq_chip = { 224 .name = "wcd937x", 225 .irqs = wcd937x_irqs, 226 .num_irqs = ARRAY_SIZE(wcd937x_irqs), 227 .num_regs = 3, 228 .status_base = WCD937X_DIGITAL_INTR_STATUS_0, 229 .mask_base = WCD937X_DIGITAL_INTR_MASK_0, 230 .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0, 231 .use_ack = 1, 232 .clear_ack = 1, 233 .config_base = wcd937x_config_regs, 234 .num_config_bases = ARRAY_SIZE(wcd937x_config_regs), 235 .num_config_regs = 1, 236 .runtime_pm = true, 237 .handle_post_irq = wcd937x_handle_post_irq, 238 .irq_drv_data = NULL, 239 }; 240 241 static void wcd937x_reset(struct wcd937x_priv *wcd937x) 242 { 243 gpiod_set_value(wcd937x->reset_gpio, 1); 244 usleep_range(20, 30); 245 gpiod_set_value(wcd937x->reset_gpio, 0); 246 usleep_range(20, 30); 247 } 248 249 static void wcd937x_io_init(struct regmap *regmap) 250 { 251 u32 val = 0, temp = 0, temp1 = 0; 252 253 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_29, &val); 254 255 val = val & 0x0F; 256 257 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &temp); 258 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_17, &temp1); 259 260 if (temp == 0x02 || temp1 > 0x09) 261 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0E, val); 262 else 263 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0e, 0x0e); 264 265 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x80, 0x80); 266 usleep_range(1000, 1010); 267 268 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x40, 0x40); 269 usleep_range(1000, 1010); 270 271 regmap_update_bits(regmap, WCD937X_LDORXTX_CONFIG, BIT(4), 0x00); 272 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xf0, BIT(7)); 273 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(7), BIT(7)); 274 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), BIT(6)); 275 usleep_range(10000, 10010); 276 277 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), 0x00); 278 regmap_update_bits(regmap, WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xff, 0xd9); 279 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_1, 0xff, 0xfa); 280 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_1, 0xff, 0xfa); 281 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_1, 0xff, 0xfa); 282 283 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_2, 0x38, 0x00); 284 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_2, 0x38, 0x00); 285 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_2, 0x38, 0x00); 286 287 /* Set Bandgap Fine Adjustment to +5mV for Tanggu SMIC part */ 288 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &val); 289 if (val == 0x01) { 290 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); 291 } else if (val == 0x02) { 292 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x1F, 0x04); 293 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x1F, 0x04); 294 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); 295 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL, 0xF0, 0x50); 296 } 297 } 298 299 static int wcd937x_rx_clk_enable(struct snd_soc_component *component) 300 { 301 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 302 303 if (atomic_read(&wcd937x->rx_clk_cnt)) 304 return 0; 305 306 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(3), BIT(3)); 307 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), BIT(0)); 308 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), BIT(0)); 309 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX0_CTL, BIT(6), 0x00); 310 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX1_CTL, BIT(6), 0x00); 311 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX2_CTL, BIT(6), 0x00); 312 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), BIT(1)); 313 314 atomic_inc(&wcd937x->rx_clk_cnt); 315 316 return 0; 317 } 318 319 static int wcd937x_rx_clk_disable(struct snd_soc_component *component) 320 { 321 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 322 323 if (!atomic_read(&wcd937x->rx_clk_cnt)) { 324 dev_err(component->dev, "clk already disabled\n"); 325 return 0; 326 } 327 328 atomic_dec(&wcd937x->rx_clk_cnt); 329 330 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), 0x00); 331 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), 0x00); 332 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), 0x00); 333 334 return 0; 335 } 336 337 static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 338 struct snd_kcontrol *kcontrol, 339 int event) 340 { 341 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 342 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 343 int hph_mode = wcd937x->hph_mode; 344 345 switch (event) { 346 case SND_SOC_DAPM_PRE_PMU: 347 wcd937x_rx_clk_enable(component); 348 snd_soc_component_update_bits(component, 349 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 350 BIT(0), BIT(0)); 351 snd_soc_component_update_bits(component, 352 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 353 BIT(2), BIT(2)); 354 snd_soc_component_update_bits(component, 355 WCD937X_HPH_RDAC_CLK_CTL1, 356 BIT(7), 0x00); 357 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 358 break; 359 case SND_SOC_DAPM_POST_PMU: 360 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 361 snd_soc_component_update_bits(component, 362 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 363 0x0f, BIT(1)); 364 else if (hph_mode == CLS_H_LOHIFI) 365 snd_soc_component_update_bits(component, 366 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 367 0x0f, 0x06); 368 369 if (wcd937x->comp1_enable) { 370 snd_soc_component_update_bits(component, 371 WCD937X_DIGITAL_CDC_COMP_CTL_0, 372 BIT(1), BIT(1)); 373 snd_soc_component_update_bits(component, 374 WCD937X_HPH_L_EN, 375 BIT(5), 0x00); 376 377 if (wcd937x->comp2_enable) { 378 snd_soc_component_update_bits(component, 379 WCD937X_DIGITAL_CDC_COMP_CTL_0, 380 BIT(0), BIT(0)); 381 snd_soc_component_update_bits(component, 382 WCD937X_HPH_R_EN, BIT(5), 0x00); 383 } 384 385 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) { 386 usleep_range(5000, 5110); 387 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 388 } 389 } else { 390 snd_soc_component_update_bits(component, 391 WCD937X_DIGITAL_CDC_COMP_CTL_0, 392 BIT(1), 0x00); 393 snd_soc_component_update_bits(component, 394 WCD937X_HPH_L_EN, 395 BIT(5), BIT(5)); 396 } 397 398 snd_soc_component_update_bits(component, 399 WCD937X_HPH_NEW_INT_HPH_TIMER1, 400 BIT(1), 0x00); 401 break; 402 case SND_SOC_DAPM_POST_PMD: 403 snd_soc_component_update_bits(component, 404 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 405 0x0f, BIT(0)); 406 break; 407 } 408 409 return 0; 410 } 411 412 static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 413 struct snd_kcontrol *kcontrol, 414 int event) 415 { 416 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 417 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 418 int hph_mode = wcd937x->hph_mode; 419 420 switch (event) { 421 case SND_SOC_DAPM_PRE_PMU: 422 wcd937x_rx_clk_enable(component); 423 snd_soc_component_update_bits(component, 424 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(1), BIT(1)); 425 snd_soc_component_update_bits(component, 426 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, BIT(3), BIT(3)); 427 snd_soc_component_update_bits(component, 428 WCD937X_HPH_RDAC_CLK_CTL1, BIT(7), 0x00); 429 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 430 break; 431 case SND_SOC_DAPM_POST_PMU: 432 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 433 snd_soc_component_update_bits(component, 434 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 435 0x0f, BIT(1)); 436 else if (hph_mode == CLS_H_LOHIFI) 437 snd_soc_component_update_bits(component, 438 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 439 0x0f, 0x06); 440 if (wcd937x->comp2_enable) { 441 snd_soc_component_update_bits(component, 442 WCD937X_DIGITAL_CDC_COMP_CTL_0, 443 BIT(0), BIT(0)); 444 snd_soc_component_update_bits(component, 445 WCD937X_HPH_R_EN, BIT(5), 0x00); 446 if (wcd937x->comp1_enable) { 447 snd_soc_component_update_bits(component, 448 WCD937X_DIGITAL_CDC_COMP_CTL_0, 449 BIT(1), BIT(1)); 450 snd_soc_component_update_bits(component, 451 WCD937X_HPH_L_EN, 452 BIT(5), 0x00); 453 } 454 455 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) { 456 usleep_range(5000, 5110); 457 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 458 } 459 } else { 460 snd_soc_component_update_bits(component, 461 WCD937X_DIGITAL_CDC_COMP_CTL_0, 462 BIT(0), 0x00); 463 snd_soc_component_update_bits(component, 464 WCD937X_HPH_R_EN, 465 BIT(5), BIT(5)); 466 } 467 snd_soc_component_update_bits(component, 468 WCD937X_HPH_NEW_INT_HPH_TIMER1, 469 BIT(1), 0x00); 470 break; 471 case SND_SOC_DAPM_POST_PMD: 472 snd_soc_component_update_bits(component, 473 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 474 0x0f, BIT(0)); 475 break; 476 } 477 478 return 0; 479 } 480 481 static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 482 struct snd_kcontrol *kcontrol, 483 int event) 484 { 485 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 486 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 487 int hph_mode = wcd937x->hph_mode; 488 489 switch (event) { 490 case SND_SOC_DAPM_PRE_PMU: 491 wcd937x_rx_clk_enable(component); 492 snd_soc_component_update_bits(component, 493 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 494 BIT(2), BIT(2)); 495 snd_soc_component_update_bits(component, 496 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 497 BIT(0), BIT(0)); 498 499 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 500 snd_soc_component_update_bits(component, 501 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 502 0x0f, BIT(1)); 503 else if (hph_mode == CLS_H_LOHIFI) 504 snd_soc_component_update_bits(component, 505 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 506 0x0f, 0x06); 507 if (wcd937x->comp1_enable) 508 snd_soc_component_update_bits(component, 509 WCD937X_DIGITAL_CDC_COMP_CTL_0, 510 BIT(1), BIT(1)); 511 usleep_range(5000, 5010); 512 513 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, BIT(2), 0x00); 514 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 515 WCD_CLSH_EVENT_PRE_DAC, 516 WCD_CLSH_STATE_EAR, 517 hph_mode); 518 519 break; 520 case SND_SOC_DAPM_POST_PMD: 521 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI || 522 hph_mode == CLS_H_HIFI) 523 snd_soc_component_update_bits(component, 524 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 525 0x0f, BIT(0)); 526 if (wcd937x->comp1_enable) 527 snd_soc_component_update_bits(component, 528 WCD937X_DIGITAL_CDC_COMP_CTL_0, 529 BIT(1), 0x00); 530 break; 531 } 532 533 return 0; 534 } 535 536 static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 537 struct snd_kcontrol *kcontrol, 538 int event) 539 { 540 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 541 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 542 int hph_mode = wcd937x->hph_mode; 543 544 switch (event) { 545 case SND_SOC_DAPM_PRE_PMU: 546 wcd937x_rx_clk_enable(component); 547 snd_soc_component_update_bits(component, 548 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 549 BIT(2), BIT(2)); 550 snd_soc_component_update_bits(component, 551 WCD937X_AUX_AUXPA, 552 BIT(4), BIT(4)); 553 snd_soc_component_update_bits(component, 554 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 555 BIT(2), BIT(2)); 556 snd_soc_component_update_bits(component, 557 WCD937X_DIGITAL_CDC_AUX_GAIN_CTL, 558 BIT(0), BIT(0)); 559 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 560 WCD_CLSH_EVENT_PRE_DAC, 561 WCD_CLSH_STATE_AUX, 562 hph_mode); 563 564 break; 565 case SND_SOC_DAPM_POST_PMD: 566 snd_soc_component_update_bits(component, 567 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 568 BIT(2), 0x00); 569 snd_soc_component_update_bits(component, 570 WCD937X_AUX_AUXPA, 571 BIT(4), 0x00); 572 break; 573 } 574 575 return 0; 576 } 577 578 static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 579 struct snd_kcontrol *kcontrol, 580 int event) 581 { 582 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 583 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 584 int hph_mode = wcd937x->hph_mode; 585 586 switch (event) { 587 case SND_SOC_DAPM_PRE_PMU: 588 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 589 WCD_CLSH_EVENT_PRE_DAC, 590 WCD_CLSH_STATE_HPHR, 591 hph_mode); 592 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 593 BIT(4), BIT(4)); 594 usleep_range(100, 110); 595 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 596 snd_soc_component_update_bits(component, 597 WCD937X_DIGITAL_PDM_WD_CTL1, 598 0x07, 0x03); 599 break; 600 case SND_SOC_DAPM_POST_PMU: 601 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 602 if (wcd937x->comp2_enable) 603 usleep_range(7000, 7100); 604 else 605 usleep_range(20000, 20100); 606 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 607 } 608 609 snd_soc_component_update_bits(component, 610 WCD937X_HPH_NEW_INT_HPH_TIMER1, 611 BIT(1), BIT(1)); 612 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 613 snd_soc_component_update_bits(component, 614 WCD937X_ANA_RX_SUPPLIES, 615 BIT(1), BIT(1)); 616 enable_irq(wcd937x->hphr_pdm_wd_int); 617 break; 618 case SND_SOC_DAPM_PRE_PMD: 619 disable_irq_nosync(wcd937x->hphr_pdm_wd_int); 620 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 621 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHR_PA_OFF); 622 break; 623 case SND_SOC_DAPM_POST_PMD: 624 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 625 if (wcd937x->comp2_enable) 626 usleep_range(7000, 7100); 627 else 628 usleep_range(20000, 20100); 629 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 630 } 631 632 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHR_PA_OFF); 633 snd_soc_component_update_bits(component, 634 WCD937X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00); 635 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 636 BIT(4), 0x00); 637 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 638 WCD_CLSH_EVENT_POST_PA, 639 WCD_CLSH_STATE_HPHR, 640 hph_mode); 641 break; 642 } 643 644 return 0; 645 } 646 647 static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 648 struct snd_kcontrol *kcontrol, 649 int event) 650 { 651 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 652 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 653 int hph_mode = wcd937x->hph_mode; 654 655 switch (event) { 656 case SND_SOC_DAPM_PRE_PMU: 657 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 658 WCD_CLSH_EVENT_PRE_DAC, 659 WCD_CLSH_STATE_HPHL, 660 hph_mode); 661 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 662 BIT(5), BIT(5)); 663 usleep_range(100, 110); 664 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 665 snd_soc_component_update_bits(component, 666 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03); 667 break; 668 case SND_SOC_DAPM_POST_PMU: 669 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 670 if (!wcd937x->comp1_enable) 671 usleep_range(20000, 20100); 672 else 673 usleep_range(7000, 7100); 674 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 675 } 676 677 snd_soc_component_update_bits(component, 678 WCD937X_HPH_NEW_INT_HPH_TIMER1, 679 BIT(1), BIT(1)); 680 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 681 snd_soc_component_update_bits(component, 682 WCD937X_ANA_RX_SUPPLIES, 683 BIT(1), BIT(1)); 684 enable_irq(wcd937x->hphl_pdm_wd_int); 685 break; 686 case SND_SOC_DAPM_PRE_PMD: 687 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 688 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 689 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 690 break; 691 case SND_SOC_DAPM_POST_PMD: 692 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 693 if (!wcd937x->comp1_enable) 694 usleep_range(20000, 20100); 695 else 696 usleep_range(7000, 7100); 697 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 698 } 699 700 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 701 snd_soc_component_update_bits(component, 702 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00); 703 snd_soc_component_update_bits(component, 704 WCD937X_ANA_HPH, BIT(5), 0x00); 705 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 706 WCD_CLSH_EVENT_POST_PA, 707 WCD_CLSH_STATE_HPHL, 708 hph_mode); 709 break; 710 } 711 712 return 0; 713 } 714 715 static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 716 struct snd_kcontrol *kcontrol, 717 int event) 718 { 719 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 720 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 721 int hph_mode = wcd937x->hph_mode; 722 u8 val; 723 724 switch (event) { 725 case SND_SOC_DAPM_PRE_PMU: 726 val = WCD937X_DIGITAL_PDM_WD_CTL2_EN | 727 WCD937X_DIGITAL_PDM_WD_CTL2_TIMEOUT_SEL | 728 WCD937X_DIGITAL_PDM_WD_CTL2_HOLD_OFF; 729 snd_soc_component_update_bits(component, 730 WCD937X_DIGITAL_PDM_WD_CTL2, 731 WCD937X_DIGITAL_PDM_WD_CTL2_MASK, 732 val); 733 break; 734 case SND_SOC_DAPM_POST_PMU: 735 usleep_range(1000, 1010); 736 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 737 snd_soc_component_update_bits(component, 738 WCD937X_ANA_RX_SUPPLIES, 739 BIT(1), BIT(1)); 740 /* Enable AUX PA related RX supplies */ 741 snd_soc_component_update_bits(component, 742 WCD937X_ANA_RX_SUPPLIES, 743 BIT(6), BIT(6)); 744 snd_soc_component_update_bits(component, 745 WCD937X_ANA_RX_SUPPLIES, 746 BIT(7), BIT(7)); 747 enable_irq(wcd937x->aux_pdm_wd_int); 748 break; 749 case SND_SOC_DAPM_PRE_PMD: 750 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 751 snd_soc_component_update_bits(component, 752 WCD937X_ANA_RX_SUPPLIES, 753 BIT(6), 0x00); 754 snd_soc_component_update_bits(component, 755 WCD937X_ANA_RX_SUPPLIES, 756 BIT(7), 0x00); 757 break; 758 case SND_SOC_DAPM_POST_PMD: 759 usleep_range(2000, 2010); 760 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 761 WCD_CLSH_EVENT_POST_PA, 762 WCD_CLSH_STATE_AUX, 763 hph_mode); 764 snd_soc_component_update_bits(component, 765 WCD937X_DIGITAL_PDM_WD_CTL2, 766 WCD937X_DIGITAL_PDM_WD_CTL2_MASK, 767 0x00); 768 break; 769 } 770 771 return 0; 772 } 773 774 static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 775 struct snd_kcontrol *kcontrol, 776 int event) 777 { 778 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 779 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 780 int hph_mode = wcd937x->hph_mode; 781 782 switch (event) { 783 case SND_SOC_DAPM_PRE_PMU: 784 /* Enable watchdog interrupt for HPHL or AUX depending on mux value */ 785 wcd937x->ear_rx_path = snd_soc_component_read(component, 786 WCD937X_DIGITAL_CDC_EAR_PATH_CTL); 787 788 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 789 snd_soc_component_update_bits(component, 790 WCD937X_DIGITAL_PDM_WD_CTL2, 791 BIT(0), BIT(0)); 792 else 793 snd_soc_component_update_bits(component, 794 WCD937X_DIGITAL_PDM_WD_CTL0, 795 0x07, 0x03); 796 if (!wcd937x->comp1_enable) 797 snd_soc_component_update_bits(component, 798 WCD937X_ANA_EAR_COMPANDER_CTL, 799 BIT(7), BIT(7)); 800 break; 801 case SND_SOC_DAPM_POST_PMU: 802 usleep_range(6000, 6010); 803 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 804 snd_soc_component_update_bits(component, 805 WCD937X_ANA_RX_SUPPLIES, 806 BIT(1), BIT(1)); 807 808 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 809 enable_irq(wcd937x->aux_pdm_wd_int); 810 else 811 enable_irq(wcd937x->hphl_pdm_wd_int); 812 break; 813 case SND_SOC_DAPM_PRE_PMD: 814 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 815 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 816 else 817 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 818 break; 819 case SND_SOC_DAPM_POST_PMD: 820 if (!wcd937x->comp1_enable) 821 snd_soc_component_update_bits(component, 822 WCD937X_ANA_EAR_COMPANDER_CTL, 823 BIT(7), 0x00); 824 usleep_range(7000, 7010); 825 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 826 WCD_CLSH_EVENT_POST_PA, 827 WCD_CLSH_STATE_EAR, 828 hph_mode); 829 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, 830 BIT(2), BIT(2)); 831 832 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 833 snd_soc_component_update_bits(component, 834 WCD937X_DIGITAL_PDM_WD_CTL2, 835 BIT(0), 0x00); 836 else 837 snd_soc_component_update_bits(component, 838 WCD937X_DIGITAL_PDM_WD_CTL0, 839 0x07, 0x00); 840 break; 841 } 842 843 return 0; 844 } 845 846 static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w, 847 struct snd_kcontrol *kcontrol, 848 int event) 849 { 850 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 851 852 if (event == SND_SOC_DAPM_POST_PMD) { 853 wcd937x_rx_clk_disable(component); 854 snd_soc_component_update_bits(component, 855 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 856 BIT(0), 0x00); 857 } 858 859 return 0; 860 } 861 862 static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w, 863 struct snd_kcontrol *kcontrol, int event) 864 { 865 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 866 867 if (event == SND_SOC_DAPM_POST_PMD) { 868 wcd937x_rx_clk_disable(component); 869 snd_soc_component_update_bits(component, 870 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 871 BIT(1), 0x00); 872 } 873 874 return 0; 875 } 876 877 static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w, 878 struct snd_kcontrol *kcontrol, 879 int event) 880 { 881 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 882 883 if (event == SND_SOC_DAPM_POST_PMD) { 884 usleep_range(6000, 6010); 885 wcd937x_rx_clk_disable(component); 886 snd_soc_component_update_bits(component, 887 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 888 BIT(2), 0x00); 889 } 890 891 return 0; 892 } 893 894 895 static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 896 struct snd_kcontrol *kcontrol, int event) 897 { 898 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 899 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 900 bool use_amic3 = snd_soc_component_read(component, WCD937X_TX_NEW_TX_CH2_SEL) & BIT(7); 901 902 /* Enable BCS for Headset mic */ 903 if (event == SND_SOC_DAPM_PRE_PMU && strnstr(w->name, "ADC", sizeof("ADC"))) 904 if (w->shift == 1 && !use_amic3) 905 set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask); 906 907 return 0; 908 } 909 910 static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w, 911 struct snd_kcontrol *kcontrol, int event) 912 { 913 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 914 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 915 916 switch (event) { 917 case SND_SOC_DAPM_PRE_PMU: 918 atomic_inc(&wcd937x->ana_clk_count); 919 snd_soc_component_update_bits(component, 920 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(7), BIT(7)); 921 snd_soc_component_update_bits(component, 922 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), BIT(3)); 923 snd_soc_component_update_bits(component, 924 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(4), BIT(4)); 925 break; 926 case SND_SOC_DAPM_POST_PMD: 927 if (w->shift == 1 && test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) 928 clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask); 929 930 snd_soc_component_update_bits(component, 931 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), 0x00); 932 break; 933 } 934 935 return 0; 936 } 937 938 static int wcd937x_enable_req(struct snd_soc_dapm_widget *w, 939 struct snd_kcontrol *kcontrol, int event) 940 { 941 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 942 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 943 944 switch (event) { 945 case SND_SOC_DAPM_PRE_PMU: 946 snd_soc_component_update_bits(component, 947 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(1), BIT(1)); 948 snd_soc_component_update_bits(component, 949 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(0), 0x00); 950 snd_soc_component_update_bits(component, 951 WCD937X_ANA_TX_CH2, BIT(6), BIT(6)); 952 snd_soc_component_update_bits(component, 953 WCD937X_ANA_TX_CH3_HPF, BIT(6), BIT(6)); 954 snd_soc_component_update_bits(component, 955 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70); 956 snd_soc_component_update_bits(component, 957 WCD937X_ANA_TX_CH1, BIT(7), BIT(7)); 958 snd_soc_component_update_bits(component, 959 WCD937X_ANA_TX_CH2, BIT(6), 0x00); 960 snd_soc_component_update_bits(component, 961 WCD937X_ANA_TX_CH2, BIT(7), BIT(7)); 962 snd_soc_component_update_bits(component, 963 WCD937X_ANA_TX_CH3, BIT(7), BIT(7)); 964 break; 965 case SND_SOC_DAPM_POST_PMD: 966 snd_soc_component_update_bits(component, 967 WCD937X_ANA_TX_CH1, BIT(7), 0x00); 968 snd_soc_component_update_bits(component, 969 WCD937X_ANA_TX_CH2, BIT(7), 0x00); 970 snd_soc_component_update_bits(component, 971 WCD937X_ANA_TX_CH3, BIT(7), 0x00); 972 snd_soc_component_update_bits(component, 973 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(4), 0x00); 974 975 atomic_dec(&wcd937x->ana_clk_count); 976 if (atomic_read(&wcd937x->ana_clk_count) <= 0) { 977 snd_soc_component_update_bits(component, 978 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 979 BIT(4), 0x00); 980 atomic_set(&wcd937x->ana_clk_count, 0); 981 } 982 983 snd_soc_component_update_bits(component, 984 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 985 BIT(7), 0x00); 986 break; 987 } 988 989 return 0; 990 } 991 992 static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 993 struct snd_kcontrol *kcontrol, 994 int event) 995 { 996 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 997 u16 dmic_clk_reg; 998 999 switch (w->shift) { 1000 case 0: 1001 case 1: 1002 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL; 1003 break; 1004 case 2: 1005 case 3: 1006 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL; 1007 break; 1008 case 4: 1009 case 5: 1010 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL; 1011 break; 1012 default: 1013 dev_err(component->dev, "Invalid DMIC Selection\n"); 1014 return -EINVAL; 1015 } 1016 1017 switch (event) { 1018 case SND_SOC_DAPM_PRE_PMU: 1019 snd_soc_component_update_bits(component, 1020 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1021 BIT(7), BIT(7)); 1022 snd_soc_component_update_bits(component, 1023 dmic_clk_reg, 0x07, BIT(1)); 1024 snd_soc_component_update_bits(component, 1025 dmic_clk_reg, BIT(3), BIT(3)); 1026 snd_soc_component_update_bits(component, 1027 dmic_clk_reg, 0x70, BIT(5)); 1028 break; 1029 } 1030 1031 return 0; 1032 } 1033 1034 static int wcd937x_micbias_control(struct snd_soc_component *component, 1035 int micb_num, int req, bool is_dapm) 1036 { 1037 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1038 int micb_index = micb_num - 1; 1039 u16 micb_reg; 1040 1041 if (micb_index < 0 || (micb_index > WCD937X_MAX_MICBIAS - 1)) { 1042 dev_err(component->dev, "Invalid micbias index, micb_ind:%d\n", micb_index); 1043 return -EINVAL; 1044 } 1045 switch (micb_num) { 1046 case MIC_BIAS_1: 1047 micb_reg = WCD937X_ANA_MICB1; 1048 break; 1049 case MIC_BIAS_2: 1050 micb_reg = WCD937X_ANA_MICB2; 1051 break; 1052 case MIC_BIAS_3: 1053 micb_reg = WCD937X_ANA_MICB3; 1054 break; 1055 default: 1056 dev_err(component->dev, "Invalid micbias number: %d\n", micb_num); 1057 return -EINVAL; 1058 } 1059 1060 guard(mutex)(&wcd937x->micb_lock); 1061 switch (req) { 1062 case MICB_PULLUP_ENABLE: 1063 wcd937x->pullup_ref[micb_index]++; 1064 if (wcd937x->pullup_ref[micb_index] == 1 && 1065 wcd937x->micb_ref[micb_index] == 0) 1066 snd_soc_component_update_bits(component, micb_reg, 1067 0xc0, BIT(7)); 1068 break; 1069 case MICB_PULLUP_DISABLE: 1070 if (wcd937x->pullup_ref[micb_index] > 0) 1071 wcd937x->pullup_ref[micb_index]++; 1072 if (wcd937x->pullup_ref[micb_index] == 0 && 1073 wcd937x->micb_ref[micb_index] == 0) 1074 snd_soc_component_update_bits(component, micb_reg, 1075 0xc0, 0x00); 1076 break; 1077 case MICB_ENABLE: 1078 wcd937x->micb_ref[micb_index]++; 1079 atomic_inc(&wcd937x->ana_clk_count); 1080 if (wcd937x->micb_ref[micb_index] == 1) { 1081 snd_soc_component_update_bits(component, 1082 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1083 0xf0, 0xf0); 1084 snd_soc_component_update_bits(component, 1085 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1086 BIT(4), BIT(4)); 1087 snd_soc_component_update_bits(component, 1088 WCD937X_MICB1_TEST_CTL_2, 1089 BIT(0), BIT(0)); 1090 snd_soc_component_update_bits(component, 1091 WCD937X_MICB2_TEST_CTL_2, 1092 BIT(0), BIT(0)); 1093 snd_soc_component_update_bits(component, 1094 WCD937X_MICB3_TEST_CTL_2, 1095 BIT(0), BIT(0)); 1096 snd_soc_component_update_bits(component, 1097 micb_reg, 0xc0, BIT(6)); 1098 1099 if (micb_num == MIC_BIAS_2) 1100 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1101 WCD_EVENT_POST_MICBIAS_2_ON); 1102 1103 if (micb_num == MIC_BIAS_2 && is_dapm) 1104 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1105 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 1106 } 1107 break; 1108 case MICB_DISABLE: 1109 atomic_dec(&wcd937x->ana_clk_count); 1110 if (wcd937x->micb_ref[micb_index] > 0) 1111 wcd937x->micb_ref[micb_index]--; 1112 if (wcd937x->micb_ref[micb_index] == 0 && 1113 wcd937x->pullup_ref[micb_index] > 0) 1114 snd_soc_component_update_bits(component, micb_reg, 1115 0xc0, BIT(7)); 1116 else if (wcd937x->micb_ref[micb_index] == 0 && 1117 wcd937x->pullup_ref[micb_index] == 0) { 1118 if (micb_num == MIC_BIAS_2) 1119 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1120 WCD_EVENT_PRE_MICBIAS_2_OFF); 1121 1122 snd_soc_component_update_bits(component, micb_reg, 1123 0xc0, 0x00); 1124 if (micb_num == MIC_BIAS_2) 1125 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1126 WCD_EVENT_POST_MICBIAS_2_OFF); 1127 } 1128 1129 if (is_dapm && micb_num == MIC_BIAS_2) 1130 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1131 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 1132 if (atomic_read(&wcd937x->ana_clk_count) <= 0) { 1133 snd_soc_component_update_bits(component, 1134 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1135 BIT(4), 0x00); 1136 atomic_set(&wcd937x->ana_clk_count, 0); 1137 } 1138 break; 1139 } 1140 1141 return 0; 1142 } 1143 1144 static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1145 int event) 1146 { 1147 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1148 int micb_num = w->shift; 1149 1150 switch (event) { 1151 case SND_SOC_DAPM_PRE_PMU: 1152 wcd937x_micbias_control(component, micb_num, 1153 MICB_ENABLE, true); 1154 break; 1155 case SND_SOC_DAPM_POST_PMU: 1156 usleep_range(1000, 1100); 1157 break; 1158 case SND_SOC_DAPM_POST_PMD: 1159 wcd937x_micbias_control(component, micb_num, 1160 MICB_DISABLE, true); 1161 break; 1162 } 1163 1164 return 0; 1165 } 1166 1167 static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1168 struct snd_kcontrol *kcontrol, 1169 int event) 1170 { 1171 return __wcd937x_codec_enable_micbias(w, event); 1172 } 1173 1174 static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1175 int event) 1176 { 1177 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1178 int micb_num = w->shift; 1179 1180 switch (event) { 1181 case SND_SOC_DAPM_PRE_PMU: 1182 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_ENABLE, true); 1183 break; 1184 case SND_SOC_DAPM_POST_PMU: 1185 usleep_range(1000, 1100); 1186 break; 1187 case SND_SOC_DAPM_POST_PMD: 1188 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_DISABLE, true); 1189 break; 1190 } 1191 1192 return 0; 1193 } 1194 1195 static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1196 struct snd_kcontrol *kcontrol, 1197 int event) 1198 { 1199 return __wcd937x_codec_enable_micbias_pullup(w, event); 1200 } 1201 1202 static int wcd937x_connect_port(struct wcd937x_sdw_priv *wcd, u8 port_idx, u8 ch_id, bool enable) 1203 { 1204 struct sdw_port_config *port_config = &wcd->port_config[port_idx - 1]; 1205 const struct wcd_sdw_ch_info *ch_info = &wcd->ch_info[ch_id]; 1206 u8 port_num = ch_info->port_num; 1207 u8 ch_mask = ch_info->ch_mask; 1208 u8 mstr_port_num, mstr_ch_mask; 1209 struct sdw_slave *sdev = wcd->sdev; 1210 1211 port_config->num = port_num; 1212 1213 mstr_port_num = sdev->m_port_map[port_num]; 1214 mstr_ch_mask = ch_info->master_ch_mask; 1215 1216 if (enable) { 1217 port_config->ch_mask |= ch_mask; 1218 wcd->master_channel_map[mstr_port_num] |= mstr_ch_mask; 1219 } else { 1220 port_config->ch_mask &= ~ch_mask; 1221 wcd->master_channel_map[mstr_port_num] &= ~mstr_ch_mask; 1222 } 1223 1224 return 0; 1225 } 1226 1227 static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 1228 struct snd_ctl_elem_value *ucontrol) 1229 { 1230 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1231 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1232 1233 ucontrol->value.integer.value[0] = wcd937x->hph_mode; 1234 return 0; 1235 } 1236 1237 static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 1238 struct snd_ctl_elem_value *ucontrol) 1239 { 1240 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1241 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1242 u32 mode_val; 1243 1244 mode_val = ucontrol->value.enumerated.item[0]; 1245 1246 if (!mode_val) 1247 mode_val = CLS_AB; 1248 1249 if (mode_val == wcd937x->hph_mode) 1250 return 0; 1251 1252 switch (mode_val) { 1253 case CLS_H_NORMAL: 1254 case CLS_H_HIFI: 1255 case CLS_H_LP: 1256 case CLS_AB: 1257 case CLS_H_LOHIFI: 1258 case CLS_H_ULP: 1259 case CLS_AB_LP: 1260 case CLS_AB_HIFI: 1261 wcd937x->hph_mode = mode_val; 1262 return 1; 1263 } 1264 1265 dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__); 1266 return -EINVAL; 1267 } 1268 1269 static int wcd937x_get_compander(struct snd_kcontrol *kcontrol, 1270 struct snd_ctl_elem_value *ucontrol) 1271 { 1272 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1273 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1274 struct soc_mixer_control *mc; 1275 bool hphr; 1276 1277 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1278 hphr = mc->shift; 1279 1280 ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable : 1281 wcd937x->comp1_enable; 1282 return 0; 1283 } 1284 1285 static int wcd937x_set_compander(struct snd_kcontrol *kcontrol, 1286 struct snd_ctl_elem_value *ucontrol) 1287 { 1288 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1289 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1290 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[AIF1_PB]; 1291 int value = ucontrol->value.integer.value[0]; 1292 struct soc_mixer_control *mc; 1293 int portidx; 1294 bool hphr; 1295 1296 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1297 hphr = mc->shift; 1298 1299 if (hphr) { 1300 if (value == wcd937x->comp2_enable) 1301 return 0; 1302 1303 wcd937x->comp2_enable = value; 1304 } else { 1305 if (value == wcd937x->comp1_enable) 1306 return 0; 1307 1308 wcd937x->comp1_enable = value; 1309 } 1310 1311 portidx = wcd->ch_info[mc->reg].port_num; 1312 1313 if (value) 1314 wcd937x_connect_port(wcd, portidx, mc->reg, true); 1315 else 1316 wcd937x_connect_port(wcd, portidx, mc->reg, false); 1317 1318 return 1; 1319 } 1320 1321 static int wcd937x_get_swr_port(struct snd_kcontrol *kcontrol, 1322 struct snd_ctl_elem_value *ucontrol) 1323 { 1324 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1325 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 1326 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp); 1327 struct wcd937x_sdw_priv *wcd; 1328 int dai_id = mixer->shift; 1329 int ch_idx = mixer->reg; 1330 int portidx; 1331 1332 wcd = wcd937x->sdw_priv[dai_id]; 1333 portidx = wcd->ch_info[ch_idx].port_num; 1334 1335 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 1336 1337 return 0; 1338 } 1339 1340 static int wcd937x_set_swr_port(struct snd_kcontrol *kcontrol, 1341 struct snd_ctl_elem_value *ucontrol) 1342 { 1343 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1344 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 1345 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp); 1346 struct wcd937x_sdw_priv *wcd; 1347 int dai_id = mixer->shift; 1348 int ch_idx = mixer->reg; 1349 int portidx; 1350 bool enable; 1351 1352 wcd = wcd937x->sdw_priv[dai_id]; 1353 1354 portidx = wcd->ch_info[ch_idx].port_num; 1355 1356 enable = ucontrol->value.integer.value[0]; 1357 1358 if (enable == wcd->port_enable[portidx]) { 1359 wcd937x_connect_port(wcd, portidx, ch_idx, enable); 1360 return 0; 1361 } 1362 1363 wcd->port_enable[portidx] = enable; 1364 wcd937x_connect_port(wcd, portidx, ch_idx, enable); 1365 1366 return 1; 1367 } 1368 1369 static const char * const rx_hph_mode_mux_text[] = { 1370 "CLS_H_NORMAL", "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", 1371 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_AB_LP", "CLS_AB_HIFI", 1372 }; 1373 1374 static const struct soc_enum rx_hph_mode_mux_enum = 1375 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), rx_hph_mode_mux_text); 1376 1377 /* MBHC related */ 1378 static void wcd937x_mbhc_clk_setup(struct snd_soc_component *component, 1379 bool enable) 1380 { 1381 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_1, 1382 WCD937X_MBHC_CTL_RCO_EN_MASK, enable); 1383 } 1384 1385 static void wcd937x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 1386 bool enable) 1387 { 1388 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_ELECT, 1389 WCD937X_ANA_MBHC_BIAS_EN, enable); 1390 } 1391 1392 static void wcd937x_mbhc_program_btn_thr(struct snd_soc_component *component, 1393 int *btn_low, int *btn_high, 1394 int num_btn, bool is_micbias) 1395 { 1396 int i, vth; 1397 1398 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 1399 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 1400 __func__, num_btn); 1401 return; 1402 } 1403 1404 for (i = 0; i < num_btn; i++) { 1405 vth = ((btn_high[i] * 2) / 25) & 0x3F; 1406 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_BTN0 + i, 1407 WCD937X_MBHC_BTN_VTH_MASK, vth); 1408 } 1409 } 1410 1411 static bool wcd937x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 1412 { 1413 u8 val; 1414 1415 if (micb_num == MIC_BIAS_2) { 1416 val = snd_soc_component_read_field(component, 1417 WCD937X_ANA_MICB2, 1418 WCD937X_ANA_MICB2_ENABLE_MASK); 1419 if (val == WCD937X_MICB_ENABLE) 1420 return true; 1421 } 1422 return false; 1423 } 1424 1425 static void wcd937x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 1426 int pull_up_cur) 1427 { 1428 /* Default pull up current to 2uA */ 1429 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 1430 pull_up_cur = HS_PULLUP_I_2P0_UA; 1431 1432 snd_soc_component_write_field(component, 1433 WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 1434 WCD937X_HSDET_PULLUP_C_MASK, pull_up_cur); 1435 } 1436 1437 static int wcd937x_mbhc_request_micbias(struct snd_soc_component *component, 1438 int micb_num, int req) 1439 { 1440 return wcd937x_micbias_control(component, micb_num, req, false); 1441 } 1442 1443 static void wcd937x_mbhc_micb_ramp_control(struct snd_soc_component *component, 1444 bool enable) 1445 { 1446 if (enable) { 1447 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1448 WCD937X_RAMP_SHIFT_CTRL_MASK, 0x0C); 1449 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1450 WCD937X_RAMP_EN_MASK, 1); 1451 } else { 1452 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1453 WCD937X_RAMP_EN_MASK, 0); 1454 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1455 WCD937X_RAMP_SHIFT_CTRL_MASK, 0); 1456 } 1457 } 1458 1459 static int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 1460 int req_volt, int micb_num) 1461 { 1462 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1463 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en; 1464 1465 switch (micb_num) { 1466 case MIC_BIAS_1: 1467 micb_reg = WCD937X_ANA_MICB1; 1468 break; 1469 case MIC_BIAS_2: 1470 micb_reg = WCD937X_ANA_MICB2; 1471 break; 1472 case MIC_BIAS_3: 1473 micb_reg = WCD937X_ANA_MICB3; 1474 break; 1475 default: 1476 return -EINVAL; 1477 } 1478 guard(mutex)(&wcd937x->micb_lock); 1479 /* 1480 * If requested micbias voltage is same as current micbias 1481 * voltage, then just return. Otherwise, adjust voltage as 1482 * per requested value. If micbias is already enabled, then 1483 * to avoid slow micbias ramp-up or down enable pull-up 1484 * momentarily, change the micbias value and then re-enable 1485 * micbias. 1486 */ 1487 micb_en = snd_soc_component_read_field(component, micb_reg, 1488 WCD937X_MICB_EN_MASK); 1489 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 1490 WCD937X_MICB_VOUT_MASK); 1491 1492 req_vout_ctl = wcd_get_micb_vout_ctl_val(component->dev, req_volt); 1493 if (req_vout_ctl < 0) 1494 return -EINVAL; 1495 1496 if (cur_vout_ctl == req_vout_ctl) 1497 return 0; 1498 1499 if (micb_en == WCD937X_MICB_ENABLE) 1500 snd_soc_component_write_field(component, micb_reg, 1501 WCD937X_MICB_EN_MASK, 1502 WCD937X_MICB_PULL_UP); 1503 1504 snd_soc_component_write_field(component, micb_reg, 1505 WCD937X_MICB_VOUT_MASK, 1506 req_vout_ctl); 1507 1508 if (micb_en == WCD937X_MICB_ENABLE) { 1509 snd_soc_component_write_field(component, micb_reg, 1510 WCD937X_MICB_EN_MASK, 1511 WCD937X_MICB_ENABLE); 1512 /* 1513 * Add 2ms delay as per HW requirement after enabling 1514 * micbias 1515 */ 1516 usleep_range(2000, 2100); 1517 } 1518 1519 return 0; 1520 } 1521 1522 static int wcd937x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 1523 int micb_num, bool req_en) 1524 { 1525 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1526 int micb_mv; 1527 1528 if (micb_num != MIC_BIAS_2) 1529 return -EINVAL; 1530 /* 1531 * If device tree micbias level is already above the minimum 1532 * voltage needed to detect threshold microphone, then do 1533 * not change the micbias, just return. 1534 */ 1535 if (wcd937x->common.micb_mv[2] >= WCD_MBHC_THR_HS_MICB_MV) 1536 return 0; 1537 1538 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd937x->common.micb_mv[2]; 1539 1540 return wcd937x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 1541 } 1542 1543 static void wcd937x_mbhc_get_result_params(struct snd_soc_component *component, 1544 s16 *d1_a, u16 noff, 1545 int32_t *zdet) 1546 { 1547 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1548 int i; 1549 int val, val1; 1550 s16 c1; 1551 s32 x1, d1; 1552 s32 denom; 1553 static const int minCode_param[] = { 1554 3277, 1639, 820, 410, 205, 103, 52, 26 1555 }; 1556 1557 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x20); 1558 for (i = 0; i < WCD937X_ZDET_NUM_MEASUREMENTS; i++) { 1559 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_2, &val); 1560 if (val & 0x80) 1561 break; 1562 } 1563 val = val << 0x8; 1564 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_1, &val1); 1565 val |= val1; 1566 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x00); 1567 x1 = WCD937X_MBHC_GET_X1(val); 1568 c1 = WCD937X_MBHC_GET_C1(val); 1569 /* If ramp is not complete, give additional 5ms */ 1570 if (c1 < 2 && x1) 1571 usleep_range(5000, 5050); 1572 1573 if (!c1 || !x1) { 1574 dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n", 1575 c1, x1); 1576 goto ramp_down; 1577 } 1578 d1 = d1_a[c1]; 1579 denom = (x1 * d1) - (1 << (14 - noff)); 1580 if (denom > 0) 1581 *zdet = (WCD937X_MBHC_ZDET_CONST * 1000) / denom; 1582 else if (x1 < minCode_param[noff]) 1583 *zdet = WCD937X_ZDET_FLOATING_IMPEDANCE; 1584 1585 dev_err(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n", 1586 __func__, d1, c1, x1, *zdet); 1587 ramp_down: 1588 i = 0; 1589 while (x1) { 1590 regmap_read(wcd937x->regmap, 1591 WCD937X_ANA_MBHC_RESULT_1, &val); 1592 regmap_read(wcd937x->regmap, 1593 WCD937X_ANA_MBHC_RESULT_2, &val1); 1594 val = val << 0x08; 1595 val |= val1; 1596 x1 = WCD937X_MBHC_GET_X1(val); 1597 i++; 1598 if (i == WCD937X_ZDET_NUM_MEASUREMENTS) 1599 break; 1600 } 1601 } 1602 1603 static void wcd937x_mbhc_zdet_ramp(struct snd_soc_component *component, 1604 struct wcd937x_mbhc_zdet_param *zdet_param, 1605 s32 *zl, s32 *zr, s16 *d1_a) 1606 { 1607 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1608 s32 zdet = 0; 1609 1610 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, 1611 WCD937X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 1612 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN5, 1613 WCD937X_VTH_MASK, zdet_param->btn5); 1614 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN6, 1615 WCD937X_VTH_MASK, zdet_param->btn6); 1616 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN7, 1617 WCD937X_VTH_MASK, zdet_param->btn7); 1618 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, 1619 WCD937X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 1620 snd_soc_component_update_bits(component, WCD937X_MBHC_NEW_ZDET_RAMP_CTL, 1621 0x0F, zdet_param->nshift); 1622 1623 if (!zl) 1624 goto z_right; 1625 /* Start impedance measurement for HPH_L */ 1626 regmap_update_bits(wcd937x->regmap, 1627 WCD937X_ANA_MBHC_ZDET, 0x80, 0x80); 1628 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 1629 regmap_update_bits(wcd937x->regmap, 1630 WCD937X_ANA_MBHC_ZDET, 0x80, 0x00); 1631 1632 *zl = zdet; 1633 1634 z_right: 1635 if (!zr) 1636 return; 1637 /* Start impedance measurement for HPH_R */ 1638 regmap_update_bits(wcd937x->regmap, 1639 WCD937X_ANA_MBHC_ZDET, 0x40, 0x40); 1640 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 1641 regmap_update_bits(wcd937x->regmap, 1642 WCD937X_ANA_MBHC_ZDET, 0x40, 0x00); 1643 1644 *zr = zdet; 1645 } 1646 1647 static void wcd937x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 1648 s32 *z_val, int flag_l_r) 1649 { 1650 s16 q1; 1651 int q1_cal; 1652 1653 if (*z_val < (WCD937X_ZDET_VAL_400 / 1000)) 1654 q1 = snd_soc_component_read(component, 1655 WCD937X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 1656 else 1657 q1 = snd_soc_component_read(component, 1658 WCD937X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 1659 if (q1 & 0x80) 1660 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 1661 else 1662 q1_cal = (10000 + (q1 * 25)); 1663 if (q1_cal > 0) 1664 *z_val = ((*z_val) * 10000) / q1_cal; 1665 } 1666 1667 static void wcd937x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 1668 u32 *zl, u32 *zr) 1669 { 1670 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1671 s16 reg0, reg1, reg2, reg3, reg4; 1672 s32 z1l, z1r, z1ls; 1673 int zMono, z_diff1, z_diff2; 1674 bool is_fsm_disable = false; 1675 struct wcd937x_mbhc_zdet_param zdet_param[] = { 1676 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 1677 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 1678 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 1679 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 1680 }; 1681 struct wcd937x_mbhc_zdet_param *zdet_param_ptr = NULL; 1682 s16 d1_a[][4] = { 1683 {0, 30, 90, 30}, 1684 {0, 30, 30, 5}, 1685 {0, 30, 30, 5}, 1686 {0, 30, 30, 5}, 1687 }; 1688 s16 *d1 = NULL; 1689 1690 reg0 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN5); 1691 reg1 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN6); 1692 reg2 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN7); 1693 reg3 = snd_soc_component_read(component, WCD937X_MBHC_CTL_CLK); 1694 reg4 = snd_soc_component_read(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL); 1695 1696 if (snd_soc_component_read(component, WCD937X_ANA_MBHC_ELECT) & 0x80) { 1697 is_fsm_disable = true; 1698 regmap_update_bits(wcd937x->regmap, 1699 WCD937X_ANA_MBHC_ELECT, 0x80, 0x00); 1700 } 1701 1702 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 1703 if (wcd937x->mbhc_cfg.hphl_swh) 1704 regmap_update_bits(wcd937x->regmap, 1705 WCD937X_ANA_MBHC_MECH, 0x80, 0x00); 1706 1707 /* Turn off 100k pull down on HPHL */ 1708 regmap_update_bits(wcd937x->regmap, 1709 WCD937X_ANA_MBHC_MECH, 0x01, 0x00); 1710 1711 /* Disable surge protection before impedance detection. 1712 * This is done to give correct value for high impedance. 1713 */ 1714 regmap_update_bits(wcd937x->regmap, 1715 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 1716 /* 1ms delay needed after disable surge protection */ 1717 usleep_range(1000, 1010); 1718 1719 /* First get impedance on Left */ 1720 d1 = d1_a[1]; 1721 zdet_param_ptr = &zdet_param[1]; 1722 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1); 1723 1724 if (!WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1l)) 1725 goto left_ch_impedance; 1726 1727 /* Second ramp for left ch */ 1728 if (z1l < WCD937X_ZDET_VAL_32) { 1729 zdet_param_ptr = &zdet_param[0]; 1730 d1 = d1_a[0]; 1731 } else if ((z1l > WCD937X_ZDET_VAL_400) && 1732 (z1l <= WCD937X_ZDET_VAL_1200)) { 1733 zdet_param_ptr = &zdet_param[2]; 1734 d1 = d1_a[2]; 1735 } else if (z1l > WCD937X_ZDET_VAL_1200) { 1736 zdet_param_ptr = &zdet_param[3]; 1737 d1 = d1_a[3]; 1738 } 1739 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1); 1740 1741 left_ch_impedance: 1742 if (z1l == WCD937X_ZDET_FLOATING_IMPEDANCE || 1743 z1l > WCD937X_ZDET_VAL_100K) { 1744 *zl = WCD937X_ZDET_FLOATING_IMPEDANCE; 1745 zdet_param_ptr = &zdet_param[1]; 1746 d1 = d1_a[1]; 1747 } else { 1748 *zl = z1l / 1000; 1749 wcd937x_wcd_mbhc_qfuse_cal(component, zl, 0); 1750 } 1751 1752 /* Start of right impedance ramp and calculation */ 1753 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1); 1754 if (WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1r)) { 1755 if ((z1r > WCD937X_ZDET_VAL_1200 && 1756 zdet_param_ptr->noff == 0x6) || 1757 ((*zl) != WCD937X_ZDET_FLOATING_IMPEDANCE)) 1758 goto right_ch_impedance; 1759 /* Second ramp for right ch */ 1760 if (z1r < WCD937X_ZDET_VAL_32) { 1761 zdet_param_ptr = &zdet_param[0]; 1762 d1 = d1_a[0]; 1763 } else if ((z1r > WCD937X_ZDET_VAL_400) && 1764 (z1r <= WCD937X_ZDET_VAL_1200)) { 1765 zdet_param_ptr = &zdet_param[2]; 1766 d1 = d1_a[2]; 1767 } else if (z1r > WCD937X_ZDET_VAL_1200) { 1768 zdet_param_ptr = &zdet_param[3]; 1769 d1 = d1_a[3]; 1770 } 1771 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1); 1772 } 1773 right_ch_impedance: 1774 if (z1r == WCD937X_ZDET_FLOATING_IMPEDANCE || 1775 z1r > WCD937X_ZDET_VAL_100K) { 1776 *zr = WCD937X_ZDET_FLOATING_IMPEDANCE; 1777 } else { 1778 *zr = z1r / 1000; 1779 wcd937x_wcd_mbhc_qfuse_cal(component, zr, 1); 1780 } 1781 1782 /* Mono/stereo detection */ 1783 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) && 1784 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE)) { 1785 dev_err(component->dev, 1786 "%s: plug type is invalid or extension cable\n", 1787 __func__); 1788 goto zdet_complete; 1789 } 1790 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) || 1791 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE) || 1792 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 1793 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 1794 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO); 1795 goto zdet_complete; 1796 } 1797 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST, 1798 WCD937X_HPHPA_GND_OVR_MASK, 1); 1799 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1800 WCD937X_HPHPA_GND_R_MASK, 1); 1801 if (*zl < (WCD937X_ZDET_VAL_32 / 1000)) 1802 wcd937x_mbhc_zdet_ramp(component, &zdet_param[0], &z1ls, NULL, d1); 1803 else 1804 wcd937x_mbhc_zdet_ramp(component, &zdet_param[1], &z1ls, NULL, d1); 1805 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1806 WCD937X_HPHPA_GND_R_MASK, 0); 1807 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST, 1808 WCD937X_HPHPA_GND_OVR_MASK, 0); 1809 z1ls /= 1000; 1810 wcd937x_wcd_mbhc_qfuse_cal(component, &z1ls, 0); 1811 /* Parallel of left Z and 9 ohm pull down resistor */ 1812 zMono = ((*zl) * 9) / ((*zl) + 9); 1813 z_diff1 = (z1ls > zMono) ? (z1ls - zMono) : (zMono - z1ls); 1814 z_diff2 = ((*zl) > z1ls) ? ((*zl) - z1ls) : (z1ls - (*zl)); 1815 if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + zMono))) 1816 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 1817 else 1818 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO); 1819 1820 /* Enable surge protection again after impedance detection */ 1821 regmap_update_bits(wcd937x->regmap, 1822 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 1823 zdet_complete: 1824 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN5, reg0); 1825 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN6, reg1); 1826 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN7, reg2); 1827 /* Turn on 100k pull down on HPHL */ 1828 regmap_update_bits(wcd937x->regmap, 1829 WCD937X_ANA_MBHC_MECH, 0x01, 0x01); 1830 1831 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 1832 if (wcd937x->mbhc_cfg.hphl_swh) 1833 regmap_update_bits(wcd937x->regmap, 1834 WCD937X_ANA_MBHC_MECH, 0x80, 0x80); 1835 1836 snd_soc_component_write(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, reg4); 1837 snd_soc_component_write(component, WCD937X_MBHC_CTL_CLK, reg3); 1838 if (is_fsm_disable) 1839 regmap_update_bits(wcd937x->regmap, 1840 WCD937X_ANA_MBHC_ELECT, 0x80, 0x80); 1841 } 1842 1843 static void wcd937x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 1844 bool enable) 1845 { 1846 if (enable) { 1847 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1848 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 1); 1849 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1850 WCD937X_MBHC_GND_DET_EN_MASK, 1); 1851 } else { 1852 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1853 WCD937X_MBHC_GND_DET_EN_MASK, 0); 1854 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1855 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 0); 1856 } 1857 } 1858 1859 static void wcd937x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 1860 bool enable) 1861 { 1862 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1863 WCD937X_HPHPA_GND_R_MASK, enable); 1864 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1865 WCD937X_HPHPA_GND_L_MASK, enable); 1866 } 1867 1868 static void wcd937x_mbhc_moisture_config(struct snd_soc_component *component) 1869 { 1870 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1871 1872 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) { 1873 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1874 WCD937X_M_RTH_CTL_MASK, R_OFF); 1875 return; 1876 } 1877 1878 /* Do not enable moisture detection if jack type is NC */ 1879 if (!wcd937x->mbhc_cfg.hphl_swh) { 1880 dev_err(component->dev, "%s: disable moisture detection for NC\n", 1881 __func__); 1882 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1883 WCD937X_M_RTH_CTL_MASK, R_OFF); 1884 return; 1885 } 1886 1887 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1888 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref); 1889 } 1890 1891 static void wcd937x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 1892 { 1893 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1894 1895 if (enable) 1896 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1897 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref); 1898 else 1899 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1900 WCD937X_M_RTH_CTL_MASK, R_OFF); 1901 } 1902 1903 static bool wcd937x_mbhc_get_moisture_status(struct snd_soc_component *component) 1904 { 1905 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1906 bool ret = false; 1907 1908 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) { 1909 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1910 WCD937X_M_RTH_CTL_MASK, R_OFF); 1911 goto done; 1912 } 1913 1914 /* Do not enable moisture detection if jack type is NC */ 1915 if (!wcd937x->mbhc_cfg.hphl_swh) { 1916 dev_err(component->dev, "%s: disable moisture detection for NC\n", 1917 __func__); 1918 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1919 WCD937X_M_RTH_CTL_MASK, R_OFF); 1920 goto done; 1921 } 1922 1923 /* 1924 * If moisture_en is already enabled, then skip to plug type 1925 * detection. 1926 */ 1927 if (snd_soc_component_read_field(component, WCD937X_MBHC_NEW_CTL_2, WCD937X_M_RTH_CTL_MASK)) 1928 goto done; 1929 1930 wcd937x_mbhc_moisture_detect_en(component, true); 1931 /* Read moisture comparator status */ 1932 ret = ((snd_soc_component_read(component, WCD937X_MBHC_NEW_FSM_STATUS) 1933 & 0x20) ? 0 : 1); 1934 done: 1935 return ret; 1936 } 1937 1938 static void wcd937x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 1939 bool enable) 1940 { 1941 snd_soc_component_write_field(component, 1942 WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 1943 WCD937X_MOISTURE_EN_POLLING_MASK, enable); 1944 } 1945 1946 static const struct wcd_mbhc_cb mbhc_cb = { 1947 .clk_setup = wcd937x_mbhc_clk_setup, 1948 .mbhc_bias = wcd937x_mbhc_mbhc_bias_control, 1949 .set_btn_thr = wcd937x_mbhc_program_btn_thr, 1950 .micbias_enable_status = wcd937x_mbhc_micb_en_status, 1951 .hph_pull_up_control_v2 = wcd937x_mbhc_hph_l_pull_up_control, 1952 .mbhc_micbias_control = wcd937x_mbhc_request_micbias, 1953 .mbhc_micb_ramp_control = wcd937x_mbhc_micb_ramp_control, 1954 .mbhc_micb_ctrl_thr_mic = wcd937x_mbhc_micb_ctrl_threshold_mic, 1955 .compute_impedance = wcd937x_wcd_mbhc_calc_impedance, 1956 .mbhc_gnd_det_ctrl = wcd937x_mbhc_gnd_det_ctrl, 1957 .hph_pull_down_ctrl = wcd937x_mbhc_hph_pull_down_ctrl, 1958 .mbhc_moisture_config = wcd937x_mbhc_moisture_config, 1959 .mbhc_get_moisture_status = wcd937x_mbhc_get_moisture_status, 1960 .mbhc_moisture_polling_ctrl = wcd937x_mbhc_moisture_polling_ctrl, 1961 .mbhc_moisture_detect_en = wcd937x_mbhc_moisture_detect_en, 1962 }; 1963 1964 static int wcd937x_get_hph_type(struct snd_kcontrol *kcontrol, 1965 struct snd_ctl_elem_value *ucontrol) 1966 { 1967 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1968 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1969 1970 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd937x->wcd_mbhc); 1971 1972 return 0; 1973 } 1974 1975 static int wcd937x_hph_impedance_get(struct snd_kcontrol *kcontrol, 1976 struct snd_ctl_elem_value *ucontrol) 1977 { 1978 u32 zl, zr; 1979 bool hphr; 1980 struct soc_mixer_control *mc; 1981 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1982 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1983 1984 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1985 hphr = mc->shift; 1986 wcd_mbhc_get_impedance(wcd937x->wcd_mbhc, &zl, &zr); 1987 ucontrol->value.integer.value[0] = hphr ? zr : zl; 1988 1989 return 0; 1990 } 1991 1992 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 1993 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 1994 wcd937x_get_hph_type, NULL), 1995 }; 1996 1997 static const struct snd_kcontrol_new impedance_detect_controls[] = { 1998 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 1999 wcd937x_hph_impedance_get, NULL), 2000 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 2001 wcd937x_hph_impedance_get, NULL), 2002 }; 2003 2004 static int wcd937x_mbhc_init(struct snd_soc_component *component) 2005 { 2006 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2007 struct wcd_mbhc_intr *intr_ids = &wcd937x->intr_ids; 2008 2009 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2010 WCD937X_IRQ_MBHC_SW_DET); 2011 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2012 WCD937X_IRQ_MBHC_BUTTON_PRESS_DET); 2013 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2014 WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET); 2015 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2016 WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2017 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2018 WCD937X_IRQ_MBHC_ELECT_INS_REM_DET); 2019 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd937x->irq_chip, 2020 WCD937X_IRQ_HPHL_OCP_INT); 2021 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd937x->irq_chip, 2022 WCD937X_IRQ_HPHR_OCP_INT); 2023 2024 wcd937x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2025 if (IS_ERR(wcd937x->wcd_mbhc)) 2026 return PTR_ERR(wcd937x->wcd_mbhc); 2027 2028 snd_soc_add_component_controls(component, impedance_detect_controls, 2029 ARRAY_SIZE(impedance_detect_controls)); 2030 snd_soc_add_component_controls(component, hph_type_detect_controls, 2031 ARRAY_SIZE(hph_type_detect_controls)); 2032 2033 return 0; 2034 } 2035 2036 static void wcd937x_mbhc_deinit(struct snd_soc_component *component) 2037 { 2038 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2039 2040 wcd_mbhc_deinit(wcd937x->wcd_mbhc); 2041 } 2042 2043 /* END MBHC */ 2044 2045 static const struct snd_kcontrol_new wcd937x_snd_controls[] = { 2046 SOC_SINGLE_TLV("EAR_PA Volume", WCD937X_ANA_EAR_COMPANDER_CTL, 2047 2, 0x10, 0, ear_pa_gain), 2048 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2049 wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put), 2050 2051 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD937X_COMP_L, 0, 1, 0, 2052 wcd937x_get_compander, wcd937x_set_compander), 2053 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD937X_COMP_R, 1, 1, 0, 2054 wcd937x_get_compander, wcd937x_set_compander), 2055 2056 SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain), 2057 SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain), 2058 SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0, analog_gain), 2059 SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0, analog_gain), 2060 SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0, analog_gain), 2061 2062 SOC_SINGLE_EXT("HPHL Switch", WCD937X_HPH_L, 0, 1, 0, 2063 wcd937x_get_swr_port, wcd937x_set_swr_port), 2064 SOC_SINGLE_EXT("HPHR Switch", WCD937X_HPH_R, 0, 1, 0, 2065 wcd937x_get_swr_port, wcd937x_set_swr_port), 2066 SOC_SINGLE_EXT("LO Switch", WCD937X_LO, 0, 1, 0, 2067 wcd937x_get_swr_port, wcd937x_set_swr_port), 2068 SOC_SINGLE_EXT("CLSH PA Switch", WCD937X_CLSH, 0, 1, 0, 2069 wcd937x_get_swr_port, wcd937x_set_swr_port), 2070 SOC_SINGLE_EXT("DSD_L Switch", WCD937X_DSD_L, 0, 1, 0, 2071 wcd937x_get_swr_port, wcd937x_set_swr_port), 2072 SOC_SINGLE_EXT("DSD_R Switch", WCD937X_DSD_R, 0, 1, 0, 2073 wcd937x_get_swr_port, wcd937x_set_swr_port), 2074 SOC_SINGLE_EXT("ADC1 Switch", WCD937X_ADC1, 1, 1, 0, 2075 wcd937x_get_swr_port, wcd937x_set_swr_port), 2076 SOC_SINGLE_EXT("ADC2 Switch", WCD937X_ADC2, 1, 1, 0, 2077 wcd937x_get_swr_port, wcd937x_set_swr_port), 2078 SOC_SINGLE_EXT("ADC3 Switch", WCD937X_ADC3, 1, 1, 0, 2079 wcd937x_get_swr_port, wcd937x_set_swr_port), 2080 SOC_SINGLE_EXT("DMIC0 Switch", WCD937X_DMIC0, 1, 1, 0, 2081 wcd937x_get_swr_port, wcd937x_set_swr_port), 2082 SOC_SINGLE_EXT("DMIC1 Switch", WCD937X_DMIC1, 1, 1, 0, 2083 wcd937x_get_swr_port, wcd937x_set_swr_port), 2084 SOC_SINGLE_EXT("MBHC Switch", WCD937X_MBHC, 1, 1, 0, 2085 wcd937x_get_swr_port, wcd937x_set_swr_port), 2086 SOC_SINGLE_EXT("DMIC2 Switch", WCD937X_DMIC2, 1, 1, 0, 2087 wcd937x_get_swr_port, wcd937x_set_swr_port), 2088 SOC_SINGLE_EXT("DMIC3 Switch", WCD937X_DMIC3, 1, 1, 0, 2089 wcd937x_get_swr_port, wcd937x_set_swr_port), 2090 SOC_SINGLE_EXT("DMIC4 Switch", WCD937X_DMIC4, 1, 1, 0, 2091 wcd937x_get_swr_port, wcd937x_set_swr_port), 2092 SOC_SINGLE_EXT("DMIC5 Switch", WCD937X_DMIC5, 1, 1, 0, 2093 wcd937x_get_swr_port, wcd937x_set_swr_port), 2094 }; 2095 2096 static const struct snd_kcontrol_new adc1_switch[] = { 2097 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2098 }; 2099 2100 static const struct snd_kcontrol_new adc2_switch[] = { 2101 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2102 }; 2103 2104 static const struct snd_kcontrol_new adc3_switch[] = { 2105 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2106 }; 2107 2108 static const struct snd_kcontrol_new dmic1_switch[] = { 2109 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2110 }; 2111 2112 static const struct snd_kcontrol_new dmic2_switch[] = { 2113 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2114 }; 2115 2116 static const struct snd_kcontrol_new dmic3_switch[] = { 2117 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2118 }; 2119 2120 static const struct snd_kcontrol_new dmic4_switch[] = { 2121 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2122 }; 2123 2124 static const struct snd_kcontrol_new dmic5_switch[] = { 2125 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2126 }; 2127 2128 static const struct snd_kcontrol_new dmic6_switch[] = { 2129 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2130 }; 2131 2132 static const struct snd_kcontrol_new ear_rdac_switch[] = { 2133 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2134 }; 2135 2136 static const struct snd_kcontrol_new aux_rdac_switch[] = { 2137 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2138 }; 2139 2140 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 2141 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2142 }; 2143 2144 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 2145 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2146 }; 2147 2148 static const char * const adc2_mux_text[] = { 2149 "INP2", "INP3" 2150 }; 2151 2152 static const char * const rdac3_mux_text[] = { 2153 "RX1", "RX3" 2154 }; 2155 2156 static const struct soc_enum adc2_enum = 2157 SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7, 2158 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 2159 2160 static const struct soc_enum rdac3_enum = 2161 SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0, 2162 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 2163 2164 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 2165 2166 static const struct snd_kcontrol_new rx_rdac3_mux = SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 2167 2168 static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = { 2169 /* Input widgets */ 2170 SND_SOC_DAPM_INPUT("AMIC1"), 2171 SND_SOC_DAPM_INPUT("AMIC2"), 2172 SND_SOC_DAPM_INPUT("AMIC3"), 2173 SND_SOC_DAPM_INPUT("IN1_HPHL"), 2174 SND_SOC_DAPM_INPUT("IN2_HPHR"), 2175 SND_SOC_DAPM_INPUT("IN3_AUX"), 2176 2177 /* TX widgets */ 2178 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 2179 wcd937x_codec_enable_adc, 2180 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2181 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 2182 wcd937x_codec_enable_adc, 2183 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2184 2185 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 2186 NULL, 0, wcd937x_enable_req, 2187 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2188 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0, 2189 NULL, 0, wcd937x_enable_req, 2190 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2191 2192 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 2193 2194 /* TX mixers */ 2195 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, 2196 adc1_switch, ARRAY_SIZE(adc1_switch), 2197 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2198 SND_SOC_DAPM_POST_PMD), 2199 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0, 2200 adc2_switch, ARRAY_SIZE(adc2_switch), 2201 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2202 SND_SOC_DAPM_POST_PMD), 2203 2204 /* MIC_BIAS widgets */ 2205 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2206 wcd937x_codec_enable_micbias, 2207 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2208 SND_SOC_DAPM_POST_PMD), 2209 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2210 wcd937x_codec_enable_micbias, 2211 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2212 SND_SOC_DAPM_POST_PMD), 2213 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2214 wcd937x_codec_enable_micbias, 2215 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2216 SND_SOC_DAPM_POST_PMD), 2217 2218 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 2219 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 2220 2221 /* RX widgets */ 2222 SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0, 2223 wcd937x_codec_enable_ear_pa, 2224 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2225 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2226 SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0, 2227 wcd937x_codec_enable_aux_pa, 2228 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2229 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2230 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0, 2231 wcd937x_codec_enable_hphl_pa, 2232 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2233 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2234 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0, 2235 wcd937x_codec_enable_hphr_pa, 2236 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2237 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2238 2239 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 2240 wcd937x_codec_hphl_dac_event, 2241 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2242 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2243 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 2244 wcd937x_codec_hphr_dac_event, 2245 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2246 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2247 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 2248 wcd937x_codec_ear_dac_event, 2249 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2250 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2251 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 2252 wcd937x_codec_aux_dac_event, 2253 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2254 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2255 2256 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 2257 2258 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, 2259 wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU | 2260 SND_SOC_DAPM_POST_PMD), 2261 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, 2262 wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU | 2263 SND_SOC_DAPM_POST_PMD), 2264 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, 2265 wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU | 2266 SND_SOC_DAPM_POST_PMD), 2267 2268 /* RX mixer widgets*/ 2269 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 2270 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 2271 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 2272 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 2273 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 2274 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 2275 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 2276 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 2277 2278 /* TX output widgets */ 2279 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 2280 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 2281 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 2282 SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"), 2283 2284 /* RX output widgets */ 2285 SND_SOC_DAPM_OUTPUT("EAR"), 2286 SND_SOC_DAPM_OUTPUT("AUX"), 2287 SND_SOC_DAPM_OUTPUT("HPHL"), 2288 SND_SOC_DAPM_OUTPUT("HPHR"), 2289 2290 /* MIC_BIAS pull up widgets */ 2291 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2292 wcd937x_codec_enable_micbias_pullup, 2293 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2294 SND_SOC_DAPM_POST_PMD), 2295 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2296 wcd937x_codec_enable_micbias_pullup, 2297 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2298 SND_SOC_DAPM_POST_PMD), 2299 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2300 wcd937x_codec_enable_micbias_pullup, 2301 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2302 SND_SOC_DAPM_POST_PMD), 2303 }; 2304 2305 static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = { 2306 /* Input widgets */ 2307 SND_SOC_DAPM_INPUT("AMIC4"), 2308 2309 /* TX widgets */ 2310 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 2311 wcd937x_codec_enable_adc, 2312 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2313 2314 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0, 2315 NULL, 0, wcd937x_enable_req, 2316 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2317 2318 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 2319 wcd937x_codec_enable_dmic, 2320 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2321 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 2322 wcd937x_codec_enable_dmic, 2323 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2324 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 2325 wcd937x_codec_enable_dmic, 2326 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2327 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 2328 wcd937x_codec_enable_dmic, 2329 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2330 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 2331 wcd937x_codec_enable_dmic, 2332 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2333 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 2334 wcd937x_codec_enable_dmic, 2335 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2336 2337 /* TX mixer widgets */ 2338 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 2339 0, dmic1_switch, ARRAY_SIZE(dmic1_switch), 2340 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2341 SND_SOC_DAPM_POST_PMD), 2342 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1, 2343 0, dmic2_switch, ARRAY_SIZE(dmic2_switch), 2344 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2345 SND_SOC_DAPM_POST_PMD), 2346 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2, 2347 0, dmic3_switch, ARRAY_SIZE(dmic3_switch), 2348 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2349 SND_SOC_DAPM_POST_PMD), 2350 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3, 2351 0, dmic4_switch, ARRAY_SIZE(dmic4_switch), 2352 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2353 SND_SOC_DAPM_POST_PMD), 2354 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4, 2355 0, dmic5_switch, ARRAY_SIZE(dmic5_switch), 2356 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2357 SND_SOC_DAPM_POST_PMD), 2358 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5, 2359 0, dmic6_switch, ARRAY_SIZE(dmic6_switch), 2360 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2361 SND_SOC_DAPM_POST_PMD), 2362 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch, 2363 ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl, 2364 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2365 2366 /* Output widgets */ 2367 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 2368 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 2369 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 2370 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 2371 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 2372 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 2373 }; 2374 2375 static const struct snd_soc_dapm_route wcd937x_audio_map[] = { 2376 { "ADC1_OUTPUT", NULL, "ADC1_MIXER" }, 2377 { "ADC1_MIXER", "Switch", "ADC1 REQ" }, 2378 { "ADC1 REQ", NULL, "ADC1" }, 2379 { "ADC1", NULL, "AMIC1" }, 2380 2381 { "ADC2_OUTPUT", NULL, "ADC2_MIXER" }, 2382 { "ADC2_MIXER", "Switch", "ADC2 REQ" }, 2383 { "ADC2 REQ", NULL, "ADC2" }, 2384 { "ADC2", NULL, "ADC2 MUX" }, 2385 { "ADC2 MUX", "INP3", "AMIC3" }, 2386 { "ADC2 MUX", "INP2", "AMIC2" }, 2387 2388 { "IN1_HPHL", NULL, "VDD_BUCK" }, 2389 { "IN1_HPHL", NULL, "CLS_H_PORT" }, 2390 { "RX1", NULL, "IN1_HPHL" }, 2391 { "RDAC1", NULL, "RX1" }, 2392 { "HPHL_RDAC", "Switch", "RDAC1" }, 2393 { "HPHL PGA", NULL, "HPHL_RDAC" }, 2394 { "HPHL", NULL, "HPHL PGA" }, 2395 2396 { "IN2_HPHR", NULL, "VDD_BUCK" }, 2397 { "IN2_HPHR", NULL, "CLS_H_PORT" }, 2398 { "RX2", NULL, "IN2_HPHR" }, 2399 { "RDAC2", NULL, "RX2" }, 2400 { "HPHR_RDAC", "Switch", "RDAC2" }, 2401 { "HPHR PGA", NULL, "HPHR_RDAC" }, 2402 { "HPHR", NULL, "HPHR PGA" }, 2403 2404 { "IN3_AUX", NULL, "VDD_BUCK" }, 2405 { "IN3_AUX", NULL, "CLS_H_PORT" }, 2406 { "RX3", NULL, "IN3_AUX" }, 2407 { "RDAC4", NULL, "RX3" }, 2408 { "AUX_RDAC", "Switch", "RDAC4" }, 2409 { "AUX PGA", NULL, "AUX_RDAC" }, 2410 { "AUX", NULL, "AUX PGA" }, 2411 2412 { "RDAC3_MUX", "RX3", "RX3" }, 2413 { "RDAC3_MUX", "RX1", "RX1" }, 2414 { "RDAC3", NULL, "RDAC3_MUX" }, 2415 { "EAR_RDAC", "Switch", "RDAC3" }, 2416 { "EAR PGA", NULL, "EAR_RDAC" }, 2417 { "EAR", NULL, "EAR PGA" }, 2418 }; 2419 2420 static const struct snd_soc_dapm_route wcd9375_audio_map[] = { 2421 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }, 2422 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }, 2423 { "ADC3_MIXER", "Switch", "ADC3 REQ" }, 2424 { "ADC3 REQ", NULL, "ADC3" }, 2425 { "ADC3", NULL, "AMIC4" }, 2426 2427 { "DMIC1_OUTPUT", NULL, "DMIC1_MIXER" }, 2428 { "DMIC1_MIXER", "Switch", "DMIC1" }, 2429 2430 { "DMIC2_OUTPUT", NULL, "DMIC2_MIXER" }, 2431 { "DMIC2_MIXER", "Switch", "DMIC2" }, 2432 2433 { "DMIC3_OUTPUT", NULL, "DMIC3_MIXER" }, 2434 { "DMIC3_MIXER", "Switch", "DMIC3" }, 2435 2436 { "DMIC4_OUTPUT", NULL, "DMIC4_MIXER" }, 2437 { "DMIC4_MIXER", "Switch", "DMIC4" }, 2438 2439 { "DMIC5_OUTPUT", NULL, "DMIC5_MIXER" }, 2440 { "DMIC5_MIXER", "Switch", "DMIC5" }, 2441 2442 { "DMIC6_OUTPUT", NULL, "DMIC6_MIXER" }, 2443 { "DMIC6_MIXER", "Switch", "DMIC6" }, 2444 }; 2445 2446 static void wcd937x_set_micbias_data(struct device *dev, struct wcd937x_priv *wcd937x) 2447 { 2448 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, WCD937X_ANA_MICB_VOUT, 2449 wcd937x->common.micb_vout[0]); 2450 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, WCD937X_ANA_MICB_VOUT, 2451 wcd937x->common.micb_vout[1]); 2452 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, WCD937X_ANA_MICB_VOUT, 2453 wcd937x->common.micb_vout[2]); 2454 } 2455 2456 static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data) 2457 { 2458 return IRQ_HANDLED; 2459 } 2460 2461 static const struct irq_chip wcd_irq_chip = { 2462 .name = "WCD937x", 2463 }; 2464 2465 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 2466 irq_hw_number_t hw) 2467 { 2468 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 2469 irq_set_nested_thread(virq, 1); 2470 irq_set_noprobe(virq); 2471 2472 return 0; 2473 } 2474 2475 static const struct irq_domain_ops wcd_domain_ops = { 2476 .map = wcd_irq_chip_map, 2477 }; 2478 2479 static int wcd937x_irq_init(struct wcd937x_priv *wcd, struct device *dev) 2480 { 2481 wcd->virq = irq_domain_create_linear(NULL, 1, &wcd_domain_ops, NULL); 2482 if (!(wcd->virq)) { 2483 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 2484 return -EINVAL; 2485 } 2486 2487 return devm_regmap_add_irq_chip(dev, wcd->regmap, 2488 irq_create_mapping(wcd->virq, 0), 2489 IRQF_ONESHOT, 0, &wcd937x_regmap_irq_chip, 2490 &wcd->irq_chip); 2491 } 2492 2493 static int wcd937x_soc_codec_probe(struct snd_soc_component *component) 2494 { 2495 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2496 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2497 struct device *dev = component->dev; 2498 int i, ret; 2499 u32 chipid; 2500 2501 ret = sdw_slave_wait_for_init(wcd937x->tx_sdw_dev, 5000); 2502 if (ret) 2503 return ret; 2504 2505 snd_soc_component_init_regmap(component, wcd937x->regmap); 2506 ret = pm_runtime_resume_and_get(dev); 2507 if (ret < 0) 2508 return ret; 2509 2510 chipid = (snd_soc_component_read(component, 2511 WCD937X_DIGITAL_EFUSE_REG_0) & 0x1e) >> 1; 2512 if (chipid != CHIPID_WCD9370 && chipid != CHIPID_WCD9375) { 2513 dev_err(dev, "Got unknown chip id: 0x%x\n", chipid); 2514 pm_runtime_put(dev); 2515 return -EINVAL; 2516 } 2517 2518 wcd937x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD937X); 2519 if (IS_ERR(wcd937x->clsh_info)) { 2520 pm_runtime_put(dev); 2521 return PTR_ERR(wcd937x->clsh_info); 2522 } 2523 2524 wcd937x_io_init(wcd937x->regmap); 2525 /* Set all interrupts as edge triggered */ 2526 for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++) 2527 regmap_write(wcd937x->regmap, (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0); 2528 2529 pm_runtime_put(dev); 2530 2531 wcd937x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2532 WCD937X_IRQ_HPHR_PDM_WD_INT); 2533 wcd937x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2534 WCD937X_IRQ_HPHL_PDM_WD_INT); 2535 wcd937x->aux_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2536 WCD937X_IRQ_AUX_PDM_WD_INT); 2537 2538 /* Request for watchdog interrupt */ 2539 ret = devm_request_threaded_irq(dev, wcd937x->hphr_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2540 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2541 "HPHR PDM WDOG INT", wcd937x); 2542 if (ret) 2543 dev_err(dev, "Failed to request HPHR watchdog interrupt (%d)\n", ret); 2544 2545 ret = devm_request_threaded_irq(dev, wcd937x->hphl_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2546 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2547 "HPHL PDM WDOG INT", wcd937x); 2548 if (ret) 2549 dev_err(dev, "Failed to request HPHL watchdog interrupt (%d)\n", ret); 2550 2551 ret = devm_request_threaded_irq(dev, wcd937x->aux_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2552 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2553 "AUX PDM WDOG INT", wcd937x); 2554 if (ret) 2555 dev_err(dev, "Failed to request Aux watchdog interrupt (%d)\n", ret); 2556 2557 /* Disable watchdog interrupt for HPH and AUX */ 2558 disable_irq_nosync(wcd937x->hphr_pdm_wd_int); 2559 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 2560 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 2561 2562 if (chipid == CHIPID_WCD9375) { 2563 ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets, 2564 ARRAY_SIZE(wcd9375_dapm_widgets)); 2565 if (ret < 0) { 2566 dev_err(component->dev, "Failed to add snd_ctls\n"); 2567 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2568 return ret; 2569 } 2570 2571 ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map, 2572 ARRAY_SIZE(wcd9375_audio_map)); 2573 if (ret < 0) { 2574 dev_err(component->dev, "Failed to add routes\n"); 2575 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2576 return ret; 2577 } 2578 } 2579 2580 ret = wcd937x_mbhc_init(component); 2581 if (ret) 2582 dev_err(component->dev, "mbhc initialization failed\n"); 2583 2584 return ret; 2585 } 2586 2587 static void wcd937x_soc_codec_remove(struct snd_soc_component *component) 2588 { 2589 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2590 2591 wcd937x_mbhc_deinit(component); 2592 free_irq(wcd937x->aux_pdm_wd_int, wcd937x); 2593 free_irq(wcd937x->hphl_pdm_wd_int, wcd937x); 2594 free_irq(wcd937x->hphr_pdm_wd_int, wcd937x); 2595 2596 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2597 } 2598 2599 static int wcd937x_codec_set_jack(struct snd_soc_component *comp, 2600 struct snd_soc_jack *jack, void *data) 2601 { 2602 struct wcd937x_priv *wcd = dev_get_drvdata(comp->dev); 2603 int ret = 0; 2604 2605 if (jack) 2606 ret = wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 2607 else 2608 wcd_mbhc_stop(wcd->wcd_mbhc); 2609 2610 return ret; 2611 } 2612 2613 static const struct snd_soc_component_driver soc_codec_dev_wcd937x = { 2614 .name = "wcd937x_codec", 2615 .probe = wcd937x_soc_codec_probe, 2616 .remove = wcd937x_soc_codec_remove, 2617 .controls = wcd937x_snd_controls, 2618 .num_controls = ARRAY_SIZE(wcd937x_snd_controls), 2619 .dapm_widgets = wcd937x_dapm_widgets, 2620 .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets), 2621 .dapm_routes = wcd937x_audio_map, 2622 .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map), 2623 .set_jack = wcd937x_codec_set_jack, 2624 .endianness = 1, 2625 }; 2626 2627 static bool wcd937x_swap_gnd_mic(struct snd_soc_component *component) 2628 { 2629 int value; 2630 struct wcd937x_priv *wcd937x; 2631 2632 wcd937x = snd_soc_component_get_drvdata(component); 2633 2634 value = gpiod_get_value(wcd937x->us_euro_gpio); 2635 gpiod_set_value(wcd937x->us_euro_gpio, !value); 2636 2637 return true; 2638 } 2639 2640 static int wcd937x_codec_hw_params(struct snd_pcm_substream *substream, 2641 struct snd_pcm_hw_params *params, 2642 struct snd_soc_dai *dai) 2643 { 2644 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2645 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2646 2647 return wcd937x_sdw_hw_params(wcd, substream, params, dai); 2648 } 2649 2650 static int wcd937x_codec_free(struct snd_pcm_substream *substream, 2651 struct snd_soc_dai *dai) 2652 { 2653 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2654 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2655 2656 return sdw_stream_remove_slave(wcd->sdev, wcd->sruntime); 2657 } 2658 2659 static int wcd937x_codec_set_sdw_stream(struct snd_soc_dai *dai, 2660 void *stream, int direction) 2661 { 2662 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2663 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2664 2665 wcd->sruntime = stream; 2666 2667 return 0; 2668 } 2669 2670 static int wcd937x_get_channel_map(const struct snd_soc_dai *dai, 2671 unsigned int *tx_num, unsigned int *tx_slot, 2672 unsigned int *rx_num, unsigned int *rx_slot) 2673 { 2674 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2675 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2676 int i; 2677 2678 switch (dai->id) { 2679 case AIF1_PB: 2680 if (!rx_slot || !rx_num) { 2681 dev_err(dai->dev, "Invalid rx_slot %p or rx_num %p\n", 2682 rx_slot, rx_num); 2683 return -EINVAL; 2684 } 2685 2686 for (i = 0; i < SDW_MAX_PORTS; i++) 2687 rx_slot[i] = wcd->master_channel_map[i]; 2688 2689 *rx_num = i; 2690 break; 2691 case AIF1_CAP: 2692 if (!tx_slot || !tx_num) { 2693 dev_err(dai->dev, "Invalid tx_slot %p or tx_num %p\n", 2694 tx_slot, tx_num); 2695 return -EINVAL; 2696 } 2697 2698 for (i = 0; i < SDW_MAX_PORTS; i++) 2699 tx_slot[i] = wcd->master_channel_map[i]; 2700 2701 *tx_num = i; 2702 break; 2703 default: 2704 break; 2705 } 2706 2707 return 0; 2708 } 2709 2710 static const struct snd_soc_dai_ops wcd937x_sdw_dai_ops = { 2711 .hw_params = wcd937x_codec_hw_params, 2712 .hw_free = wcd937x_codec_free, 2713 .set_stream = wcd937x_codec_set_sdw_stream, 2714 .get_channel_map = wcd937x_get_channel_map, 2715 }; 2716 2717 static struct snd_soc_dai_driver wcd937x_dais[] = { 2718 [0] = { 2719 .name = "wcd937x-sdw-rx", 2720 .playback = { 2721 .stream_name = "WCD AIF Playback", 2722 .rates = WCD937X_RATES | WCD937X_FRAC_RATES, 2723 .formats = WCD937X_FORMATS, 2724 .rate_min = 8000, 2725 .rate_max = 384000, 2726 .channels_min = 1, 2727 .channels_max = 4, 2728 }, 2729 .ops = &wcd937x_sdw_dai_ops, 2730 }, 2731 [1] = { 2732 .name = "wcd937x-sdw-tx", 2733 .capture = { 2734 .stream_name = "WCD AIF Capture", 2735 .rates = WCD937X_RATES, 2736 .formats = WCD937X_FORMATS, 2737 .rate_min = 8000, 2738 .rate_max = 192000, 2739 .channels_min = 1, 2740 .channels_max = 4, 2741 }, 2742 .ops = &wcd937x_sdw_dai_ops, 2743 }, 2744 }; 2745 2746 static int wcd937x_bind(struct device *dev) 2747 { 2748 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2749 int ret; 2750 2751 /* Give the SDW subdevices some more time to settle */ 2752 usleep_range(5000, 5010); 2753 2754 ret = component_bind_all(dev, wcd937x); 2755 if (ret) { 2756 dev_err(dev, "Slave bind failed, ret = %d\n", ret); 2757 return ret; 2758 } 2759 2760 wcd937x->rxdev = of_sdw_find_device_by_node(wcd937x->rxnode); 2761 if (!wcd937x->rxdev) { 2762 dev_err(dev, "could not find slave with matching of node\n"); 2763 ret = -EINVAL; 2764 goto err_component_unbind; 2765 } 2766 2767 wcd937x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd937x->rxdev); 2768 wcd937x->sdw_priv[AIF1_PB]->wcd937x = wcd937x; 2769 2770 wcd937x->txdev = of_sdw_find_device_by_node(wcd937x->txnode); 2771 if (!wcd937x->txdev) { 2772 dev_err(dev, "could not find txslave with matching of node\n"); 2773 ret = -EINVAL; 2774 goto err_put_rxdev; 2775 } 2776 2777 wcd937x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd937x->txdev); 2778 wcd937x->sdw_priv[AIF1_CAP]->wcd937x = wcd937x; 2779 wcd937x->tx_sdw_dev = dev_to_sdw_dev(wcd937x->txdev); 2780 2781 /* 2782 * As TX is the main CSR reg interface, which should not be suspended first. 2783 * expicilty add the dependency link 2784 */ 2785 if (!device_link_add(wcd937x->rxdev, wcd937x->txdev, 2786 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2787 dev_err(dev, "Could not devlink TX and RX\n"); 2788 ret = -EINVAL; 2789 goto err_put_txdev; 2790 } 2791 2792 if (!device_link_add(dev, wcd937x->txdev, 2793 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2794 dev_err(dev, "Could not devlink WCD and TX\n"); 2795 ret = -EINVAL; 2796 goto err_remove_link1; 2797 } 2798 2799 if (!device_link_add(dev, wcd937x->rxdev, 2800 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2801 dev_err(dev, "Could not devlink WCD and RX\n"); 2802 ret = -EINVAL; 2803 goto err_remove_link2; 2804 } 2805 2806 wcd937x->regmap = wcd937x->sdw_priv[AIF1_CAP]->regmap; 2807 if (!wcd937x->regmap) { 2808 dev_err(dev, "could not get TX device regmap\n"); 2809 ret = -EINVAL; 2810 goto err_remove_link3; 2811 } 2812 2813 ret = wcd937x_irq_init(wcd937x, dev); 2814 if (ret) { 2815 dev_err(dev, "IRQ init failed: %d\n", ret); 2816 goto err_remove_link3; 2817 } 2818 2819 wcd937x->sdw_priv[AIF1_PB]->slave_irq = wcd937x->virq; 2820 wcd937x->sdw_priv[AIF1_CAP]->slave_irq = wcd937x->virq; 2821 2822 wcd937x_set_micbias_data(dev, wcd937x); 2823 2824 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x, 2825 wcd937x_dais, ARRAY_SIZE(wcd937x_dais)); 2826 if (ret) { 2827 dev_err(dev, "Codec registration failed\n"); 2828 goto err_remove_link3; 2829 } 2830 2831 return ret; 2832 2833 err_remove_link3: 2834 device_link_remove(dev, wcd937x->rxdev); 2835 err_remove_link2: 2836 device_link_remove(dev, wcd937x->txdev); 2837 err_remove_link1: 2838 device_link_remove(wcd937x->rxdev, wcd937x->txdev); 2839 err_put_txdev: 2840 put_device(wcd937x->txdev); 2841 err_put_rxdev: 2842 put_device(wcd937x->rxdev); 2843 err_component_unbind: 2844 component_unbind_all(dev, wcd937x); 2845 return ret; 2846 } 2847 2848 static void wcd937x_unbind(struct device *dev) 2849 { 2850 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2851 2852 snd_soc_unregister_component(dev); 2853 device_link_remove(dev, wcd937x->txdev); 2854 device_link_remove(dev, wcd937x->rxdev); 2855 device_link_remove(wcd937x->rxdev, wcd937x->txdev); 2856 component_unbind_all(dev, wcd937x); 2857 mutex_destroy(&wcd937x->micb_lock); 2858 put_device(wcd937x->txdev); 2859 put_device(wcd937x->rxdev); 2860 } 2861 2862 static const struct component_master_ops wcd937x_comp_ops = { 2863 .bind = wcd937x_bind, 2864 .unbind = wcd937x_unbind, 2865 }; 2866 2867 static int wcd937x_add_slave_components(struct wcd937x_priv *wcd937x, 2868 struct device *dev, 2869 struct component_match **matchptr) 2870 { 2871 struct device_node *np = dev->of_node; 2872 2873 wcd937x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 2874 if (!wcd937x->rxnode) { 2875 dev_err(dev, "Couldn't parse phandle to qcom,rx-device!\n"); 2876 return -ENODEV; 2877 } 2878 2879 component_match_add_release(dev, matchptr, component_release_of, 2880 component_compare_of, wcd937x->rxnode); 2881 2882 wcd937x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 2883 if (!wcd937x->txnode) { 2884 dev_err(dev, "Couldn't parse phandle to qcom,tx-device\n"); 2885 return -ENODEV; 2886 } 2887 2888 component_match_add_release(dev, matchptr, component_release_of, 2889 component_compare_of, wcd937x->txnode); 2890 2891 return 0; 2892 } 2893 2894 static int wcd937x_probe(struct platform_device *pdev) 2895 { 2896 struct component_match *match = NULL; 2897 struct device *dev = &pdev->dev; 2898 struct wcd937x_priv *wcd937x; 2899 struct wcd_mbhc_config *cfg; 2900 int ret; 2901 2902 wcd937x = devm_kzalloc(dev, sizeof(*wcd937x), GFP_KERNEL); 2903 if (!wcd937x) 2904 return -ENOMEM; 2905 2906 dev_set_drvdata(dev, wcd937x); 2907 mutex_init(&wcd937x->micb_lock); 2908 wcd937x->common.dev = dev; 2909 wcd937x->common.max_bias = 3; 2910 2911 wcd937x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 2912 if (IS_ERR(wcd937x->reset_gpio)) 2913 return dev_err_probe(dev, PTR_ERR(wcd937x->reset_gpio), 2914 "failed to reset wcd gpio\n"); 2915 2916 wcd937x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", GPIOD_OUT_LOW); 2917 if (IS_ERR(wcd937x->us_euro_gpio)) 2918 return dev_err_probe(dev, PTR_ERR(wcd937x->us_euro_gpio), 2919 "us-euro swap Control GPIO not found\n"); 2920 2921 cfg = &wcd937x->mbhc_cfg; 2922 cfg->swap_gnd_mic = wcd937x_swap_gnd_mic; 2923 2924 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(wcd937x_supplies), 2925 wcd937x_supplies); 2926 if (ret) 2927 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n"); 2928 2929 ret = wcd_dt_parse_micbias_info(&wcd937x->common); 2930 if (ret) 2931 return dev_err_probe(dev, ret, "Failed to get micbias\n"); 2932 2933 cfg->mbhc_micbias = MIC_BIAS_2; 2934 cfg->anc_micbias = MIC_BIAS_2; 2935 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 2936 cfg->num_btn = WCD937X_MBHC_MAX_BUTTONS; 2937 cfg->micb_mv = wcd937x->common.micb_mv[2]; 2938 cfg->linein_th = 5000; 2939 cfg->hs_thr = 1700; 2940 cfg->hph_thr = 50; 2941 2942 wcd_dt_parse_mbhc_data(dev, &wcd937x->mbhc_cfg); 2943 2944 ret = wcd937x_add_slave_components(wcd937x, dev, &match); 2945 if (ret) 2946 return ret; 2947 2948 wcd937x_reset(wcd937x); 2949 2950 ret = component_master_add_with_match(dev, &wcd937x_comp_ops, match); 2951 if (ret) 2952 return ret; 2953 2954 pm_runtime_set_autosuspend_delay(dev, 1000); 2955 pm_runtime_use_autosuspend(dev); 2956 pm_runtime_mark_last_busy(dev); 2957 pm_runtime_set_active(dev); 2958 pm_runtime_enable(dev); 2959 pm_runtime_idle(dev); 2960 2961 return 0; 2962 } 2963 2964 static void wcd937x_remove(struct platform_device *pdev) 2965 { 2966 struct device *dev = &pdev->dev; 2967 2968 component_master_del(&pdev->dev, &wcd937x_comp_ops); 2969 2970 pm_runtime_disable(dev); 2971 pm_runtime_set_suspended(dev); 2972 pm_runtime_dont_use_autosuspend(dev); 2973 } 2974 2975 #if defined(CONFIG_OF) 2976 static const struct of_device_id wcd937x_of_match[] = { 2977 { .compatible = "qcom,wcd9370-codec" }, 2978 { .compatible = "qcom,wcd9375-codec" }, 2979 { } 2980 }; 2981 MODULE_DEVICE_TABLE(of, wcd937x_of_match); 2982 #endif 2983 2984 static struct platform_driver wcd937x_codec_driver = { 2985 .probe = wcd937x_probe, 2986 .remove = wcd937x_remove, 2987 .driver = { 2988 .name = "wcd937x_codec", 2989 .of_match_table = of_match_ptr(wcd937x_of_match), 2990 .suppress_bind_attrs = true, 2991 }, 2992 }; 2993 2994 module_platform_driver(wcd937x_codec_driver); 2995 MODULE_DESCRIPTION("WCD937X Codec driver"); 2996 MODULE_LICENSE("GPL"); 2997